dsi_phy_20nm.xml

  1<?xml version="1.0" encoding="UTF-8"?>
  2<database xmlns="http://nouveau.freedesktop.org/"
  3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
  4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
  5<import file="freedreno_copyright.xml"/>
  6
  7<domain name="DSI_20nm_PHY" width="32">
  8	<array offset="0x00000" name="LN" length="4" stride="0x40">
  9		<reg32 offset="0x00" name="CFG_0"/>
 10		<reg32 offset="0x04" name="CFG_1"/>
 11		<reg32 offset="0x08" name="CFG_2"/>
 12		<reg32 offset="0x0c" name="CFG_3"/>
 13		<reg32 offset="0x10" name="CFG_4"/>
 14		<reg32 offset="0x14" name="TEST_DATAPATH"/>
 15		<reg32 offset="0x18" name="DEBUG_SEL"/>
 16		<reg32 offset="0x1c" name="TEST_STR_0"/>
 17		<reg32 offset="0x20" name="TEST_STR_1"/>
 18	</array>
 19
 20	<reg32 offset="0x00100" name="LNCK_CFG_0"/>
 21	<reg32 offset="0x00104" name="LNCK_CFG_1"/>
 22	<reg32 offset="0x00108" name="LNCK_CFG_2"/>
 23	<reg32 offset="0x0010c" name="LNCK_CFG_3"/>
 24	<reg32 offset="0x00110" name="LNCK_CFG_4"/>
 25	<reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
 26	<reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
 27	<reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
 28	<reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
 29
 30	<reg32 offset="0x00140" name="TIMING_CTRL_0">
 31		<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
 32	</reg32>
 33	<reg32 offset="0x00144" name="TIMING_CTRL_1">
 34		<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
 35	</reg32>
 36	<reg32 offset="0x00148" name="TIMING_CTRL_2">
 37		<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
 38	</reg32>
 39	<reg32 offset="0x0014c" name="TIMING_CTRL_3">
 40		<bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
 41	</reg32>
 42	<reg32 offset="0x00150" name="TIMING_CTRL_4">
 43		<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
 44	</reg32>
 45	<reg32 offset="0x00154" name="TIMING_CTRL_5">
 46		<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
 47	</reg32>
 48	<reg32 offset="0x00158" name="TIMING_CTRL_6">
 49		<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
 50	</reg32>
 51	<reg32 offset="0x0015c" name="TIMING_CTRL_7">
 52		<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
 53	</reg32>
 54	<reg32 offset="0x00160" name="TIMING_CTRL_8">
 55		<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
 56	</reg32>
 57	<reg32 offset="0x00164" name="TIMING_CTRL_9">
 58		<bitfield name="TA_GO" low="0" high="2" type="uint"/>
 59		<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
 60	</reg32>
 61	<reg32 offset="0x00168" name="TIMING_CTRL_10">
 62		<bitfield name="TA_GET" low="0" high="2" type="uint"/>
 63	</reg32>
 64	<reg32 offset="0x0016c" name="TIMING_CTRL_11">
 65		<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
 66	</reg32>
 67
 68	<reg32 offset="0x00170" name="CTRL_0"/>
 69	<reg32 offset="0x00174" name="CTRL_1"/>
 70	<reg32 offset="0x00178" name="CTRL_2"/>
 71	<reg32 offset="0x0017c" name="CTRL_3"/>
 72	<reg32 offset="0x00180" name="CTRL_4"/>
 73
 74	<reg32 offset="0x00184" name="STRENGTH_0"/>
 75	<reg32 offset="0x00188" name="STRENGTH_1"/>
 76
 77	<reg32 offset="0x001b4" name="BIST_CTRL_0"/>
 78	<reg32 offset="0x001b8" name="BIST_CTRL_1"/>
 79	<reg32 offset="0x001bc" name="BIST_CTRL_2"/>
 80	<reg32 offset="0x001c0" name="BIST_CTRL_3"/>
 81	<reg32 offset="0x001c4" name="BIST_CTRL_4"/>
 82	<reg32 offset="0x001c8" name="BIST_CTRL_5"/>
 83
 84	<reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
 85		<bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
 86	</reg32>
 87	<reg32 offset="0x001dc" name="LDO_CNTRL"/>
 88</domain>
 89
 90<domain name="DSI_20nm_PHY_REGULATOR" width="32">
 91	<reg32 offset="0x00000" name="CTRL_0"/>
 92	<reg32 offset="0x00004" name="CTRL_1"/>
 93	<reg32 offset="0x00008" name="CTRL_2"/>
 94	<reg32 offset="0x0000c" name="CTRL_3"/>
 95	<reg32 offset="0x00010" name="CTRL_4"/>
 96	<reg32 offset="0x00014" name="CTRL_5"/>
 97	<reg32 offset="0x00018" name="CAL_PWR_CFG"/>
 98</domain>
 99
100</database>