dsi_phy_14nm.xml

  1<?xml version="1.0" encoding="UTF-8"?>
  2<database xmlns="http://nouveau.freedesktop.org/"
  3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
  4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
  5<import file="freedreno_copyright.xml"/>
  6
  7<domain name="DSI_14nm_PHY_CMN" width="32">
  8	<reg32 offset="0x00000" name="REVISION_ID0"/>
  9	<reg32 offset="0x00004" name="REVISION_ID1"/>
 10	<reg32 offset="0x00008" name="REVISION_ID2"/>
 11	<reg32 offset="0x0000c" name="REVISION_ID3"/>
 12	<reg32 offset="0x00010" name="CLK_CFG0">
 13		<bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
 14		<bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
 15	</reg32>
 16	<reg32 offset="0x00014" name="CLK_CFG1">
 17		<bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
 18	</reg32>
 19	<reg32 offset="0x00018" name="GLBL_TEST_CTRL">
 20		<bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
 21	</reg32>
 22	<reg32 offset="0x0001C" name="CTRL_0"/>
 23	<reg32 offset="0x00020" name="CTRL_1">
 24	</reg32>
 25	<reg32 offset="0x00024" name="HW_TRIGGER"/>
 26	<reg32 offset="0x00028" name="SW_CFG0"/>
 27	<reg32 offset="0x0002C" name="SW_CFG1"/>
 28	<reg32 offset="0x00030" name="SW_CFG2"/>
 29	<reg32 offset="0x00034" name="HW_CFG0"/>
 30	<reg32 offset="0x00038" name="HW_CFG1"/>
 31	<reg32 offset="0x0003C" name="HW_CFG2"/>
 32	<reg32 offset="0x00040" name="HW_CFG3"/>
 33	<reg32 offset="0x00044" name="HW_CFG4"/>
 34	<reg32 offset="0x00048" name="PLL_CNTRL">
 35		<bitfield name="PLL_START" pos="0" type="boolean"/>
 36	</reg32>
 37	<reg32 offset="0x0004C" name="LDO_CNTRL">
 38		<bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
 39	</reg32>
 40</domain>
 41
 42<domain name="DSI_14nm_PHY" width="32">
 43	<array offset="0x00000" name="LN" length="5" stride="0x80">
 44		<reg32 offset="0x00" name="CFG0">
 45			<bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
 46		</reg32>
 47		<reg32 offset="0x04" name="CFG1">
 48			<bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
 49		</reg32>
 50		<reg32 offset="0x08" name="CFG2"/>
 51		<reg32 offset="0x0c" name="CFG3"/>
 52		<reg32 offset="0x10" name="TEST_DATAPATH"/>
 53		<reg32 offset="0x14" name="TEST_STR"/>
 54		<reg32 offset="0x18" name="TIMING_CTRL_4">
 55			<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
 56		</reg32>
 57		<reg32 offset="0x1c" name="TIMING_CTRL_5">
 58			<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
 59		</reg32>
 60		<reg32 offset="0x20" name="TIMING_CTRL_6">
 61			<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
 62		</reg32>
 63		<reg32 offset="0x24" name="TIMING_CTRL_7">
 64			<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
 65		</reg32>
 66		<reg32 offset="0x28" name="TIMING_CTRL_8">
 67			<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
 68		</reg32>
 69		<reg32 offset="0x2c" name="TIMING_CTRL_9">
 70			<bitfield name="TA_GO" low="0" high="2" type="uint"/>
 71			<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
 72		</reg32>
 73		<reg32 offset="0x30" name="TIMING_CTRL_10">
 74			<bitfield name="TA_GET" low="0" high="2" type="uint"/>
 75		</reg32>
 76		<reg32 offset="0x34" name="TIMING_CTRL_11">
 77			<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
 78		</reg32>
 79		<reg32 offset="0x38" name="STRENGTH_CTRL_0"/>
 80		<reg32 offset="0x3c" name="STRENGTH_CTRL_1"/>
 81		<reg32 offset="0x64" name="VREG_CNTRL"/>
 82	</array>
 83</domain>
 84
 85<domain name="DSI_14nm_PHY_PLL" width="32">
 86	<reg32 offset="0x000" name="IE_TRIM"/>
 87	<reg32 offset="0x004" name="IP_TRIM"/>
 88	<reg32 offset="0x010" name="IPTAT_TRIM"/>
 89	<reg32 offset="0x01c" name="CLKBUFLR_EN"/>
 90	<reg32 offset="0x028" name="SYSCLK_EN_RESET"/>
 91	<reg32 offset="0x02c" name="RESETSM_CNTRL"/>
 92	<reg32 offset="0x030" name="RESETSM_CNTRL2"/>
 93	<reg32 offset="0x034" name="RESETSM_CNTRL3"/>
 94	<reg32 offset="0x038" name="RESETSM_CNTRL4"/>
 95	<reg32 offset="0x03c" name="RESETSM_CNTRL5"/>
 96	<reg32 offset="0x040" name="KVCO_DIV_REF1"/>
 97	<reg32 offset="0x044" name="KVCO_DIV_REF2"/>
 98	<reg32 offset="0x048" name="KVCO_COUNT1"/>
 99	<reg32 offset="0x04c" name="KVCO_COUNT2"/>
100	<reg32 offset="0x05c" name="VREF_CFG1"/>
101	<reg32 offset="0x058" name="KVCO_CODE"/>
102	<reg32 offset="0x06c" name="VCO_DIV_REF1"/>
103	<reg32 offset="0x070" name="VCO_DIV_REF2"/>
104	<reg32 offset="0x074" name="VCO_COUNT1"/>
105	<reg32 offset="0x078" name="VCO_COUNT2"/>
106	<reg32 offset="0x07c" name="PLLLOCK_CMP1"/>
107	<reg32 offset="0x080" name="PLLLOCK_CMP2"/>
108	<reg32 offset="0x084" name="PLLLOCK_CMP3"/>
109	<reg32 offset="0x088" name="PLLLOCK_CMP_EN"/>
110	<reg32 offset="0x08c" name="PLL_VCO_TUNE"/>
111	<reg32 offset="0x090" name="DEC_START"/>
112	<reg32 offset="0x094" name="SSC_EN_CENTER"/>
113	<reg32 offset="0x098" name="SSC_ADJ_PER1"/>
114	<reg32 offset="0x09c" name="SSC_ADJ_PER2"/>
115	<reg32 offset="0x0a0" name="SSC_PER1"/>
116	<reg32 offset="0x0a4" name="SSC_PER2"/>
117	<reg32 offset="0x0a8" name="SSC_STEP_SIZE1"/>
118	<reg32 offset="0x0ac" name="SSC_STEP_SIZE2"/>
119	<reg32 offset="0x0b4" name="DIV_FRAC_START1"/>
120	<reg32 offset="0x0b8" name="DIV_FRAC_START2"/>
121	<reg32 offset="0x0bc" name="DIV_FRAC_START3"/>
122	<reg32 offset="0x0c0" name="TXCLK_EN"/>
123	<reg32 offset="0x0c4" name="PLL_CRCTRL"/>
124	<reg32 offset="0x0cc" name="RESET_SM_READY_STATUS"/>
125	<reg32 offset="0x0e8" name="PLL_MISC1"/>
126	<reg32 offset="0x0f0" name="CP_SET_CUR"/>
127	<reg32 offset="0x0f4" name="PLL_ICPMSET"/>
128	<reg32 offset="0x0f8" name="PLL_ICPCSET"/>
129	<reg32 offset="0x0fc" name="PLL_ICP_SET"/>
130	<reg32 offset="0x100" name="PLL_LPF1"/>
131	<reg32 offset="0x104" name="PLL_LPF2_POSTDIV"/>
132	<reg32 offset="0x108" name="PLL_BANDGAP"/>
133</domain>
134
135</database>