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adreno_pm4.xml
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linux-6.19.14/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7 8<enum name="vgt_event_type" varset="chip"> 9 <value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/> 10 <value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/> 11 <value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/> 12 <value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/> 13 <doc> 14 Flushes dirty data from UCHE, and also writes a GPU timestamp to 15 the address if one is provided. 16 </doc> 17 <value name="CACHE_FLUSH_TS" value="0x04"/> 18 <value name="CONTEXT_DONE" value="0x05"/> 19 <value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/> 20 <value name="VIZQUERY_START" value="0x07" variants="A2XX"/> 21 <value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/> 22 <value name="VIZQUERY_END" value="0x08" variants="A2XX"/> 23 <value name="SC_WAIT_WC" value="0x09" variants="A2XX"/> 24 <value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/> 25 <value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/> 26 <value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/> 27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> 28 <value name="RST_PIX_CNT" value="0x0d" variants="A2XX-A4XX"/> 29 <value name="RST_VTX_CNT" value="0x0e" variants="A2XX-A4XX"/> 30 <value name="TILE_FLUSH" value="0x0f" variants="A2XX-A4XX"/> 31 <value name="STAT_EVENT" value="0x10" variants="A2XX-A4XX"/> 32 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="0x14" variants="A2XX-A4XX"/> 33 <doc> 34 If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed 35 sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main 36 memory, skipping UCHE. 37 </doc> 38 <value name="ZPASS_DONE" value="0x15"/> 39 <value name="CACHE_FLUSH_AND_INV_EVENT" value="0x16" variants="A2XX"/> 40 41 <doc> 42 Writes the GPU timestamp to the address that follows, once RB 43 access and flushes are complete. 44 </doc> 45 <value name="RB_DONE_TS" value="0x16" variants="A3XX-"/> 46 47 <value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/> 48 <value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/> 49 <value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/> 50 <value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/> 51 52 <!-- a5xx events --> 53 <value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/> 54 <value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/> 55 <value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/> 56 <value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/> 57 <value name="STOP_COMPUTE_CTRS" value="0x10" variants="A5XX-"/> 58 <value name="FLUSH_SO_0" value="0x11" variants="A5XX-"/> 59 <value name="FLUSH_SO_1" value="0x12" variants="A5XX-"/> 60 <value name="FLUSH_SO_2" value="0x13" variants="A5XX-"/> 61 <value name="FLUSH_SO_3" value="0x14" variants="A5XX-"/> 62 63 <doc> 64 Invalidates depth attachment data from the CCU. We assume this 65 happens in the last stage. 66 </doc> 67 <value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/> 68 69 <doc> 70 Invalidates color attachment data from the CCU. We assume this 71 happens in the last stage. 72 </doc> 73 <value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/> 74 75 <doc> 76 Flushes the small cache used by CP_EVENT_WRITE::BLIT (which, 77 along with its registers, would be better named RESOLVE). 78 </doc> 79 <value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/> 80 81 <doc> 82 Flushes depth attachment data from the CCU. We assume this 83 happens in the last stage. 84 </doc> 85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/> 86 87 <doc> 88 Flushes color attachment data from the CCU. We assume this 89 happens in the last stage. 90 </doc> 91 <value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/> 92 93 <doc> 94 Triggers a resolve (GMEM to sysmem) or unresolve (sysmem to 95 GMEM) or clear blit, depending on CCU programming. 96 </doc> 97 <value name="CCU_RESOLVE" value="0x1e" variants="A5XX-"/> 98 99 <doc> 100 Flip between the primary and secondary LRZ buffers. This is used 101 for concurrent binning, so that BV can write to one buffer while 102 BR reads from the other. 103 </doc> 104 <value name="LRZ_FLIP_BUFFER" value="0x24" variants="A7XX-"/> 105 106 <doc> 107 Clears based on GRAS_LRZ_CNTL configuration, could clear 108 fast-clear buffer or LRZ direction. 109 LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which 110 could be expressed by enum: 111 CUR_DIR_DISABLED = 0x0 112 CUR_DIR_GE = 0x1 113 CUR_DIR_LE = 0x2 114 CUR_DIR_UNSET = 0x3 115 Clear of direction means setting the direction to CUR_DIR_UNSET. 116 </doc> 117 <value name="LRZ_CLEAR" value="0x25" variants="A5XX-"/> 118 119 <value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/> 120 <value name="LRZ_CACHE_FLUSH" value="0x26" variants="A7XX-"/> 121 <value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-A6XX"/> 122 <value name="BLIT_OP_COPY_2D" value="0x28" variants="A5XX-A6XX"/> 123 <value name="LRZ_CACHE_INVALIDATE" value="0x28" variants="A7XX-"/> 124 <value name="LRZ_Q_CACHE_INVALIDATE" value="0x29" variants="A7XX-"/> 125 <value name="BLIT_OP_SCALE_2D" value="0x2a" variants="A5XX-"/> 126 <value name="CONTEXT_DONE_2D" value="0x2b" variants="A5XX-"/> 127 <value name="VSC_BINNING_START" value="0x2c" variants="A5XX-"/> 128 <value name="VSC_BINNING_END" value="0x2d" variants="A5XX-"/> 129 130 <!-- a6xx events --> 131 <doc> 132 Invalidates UCHE. 133 </doc> 134 <value name="CACHE_INVALIDATE" value="0x31" variants="A6XX"/> 135 136 <value name="DEBUG_LABEL" value="0x3f" variants="A6XX-"/> 137 138 <!-- note, some of these are the same as a6xx, just named differently --> 139 140 <doc> Doesn't seem to do anything </doc> 141 <value name="DUMMY_EVENT" value="0x01" variants="A7XX-"/> 142 <value name="CCU_INVALIDATE_DEPTH" value="0x18" variants="A7XX-"/> 143 <value name="CCU_INVALIDATE_COLOR" value="0x19" variants="A7XX-"/> 144 <value name="CCU_RESOLVE_CLEAN" value="0x1a" variants="A7XX-"/> 145 <value name="CCU_FLUSH_DEPTH" value="0x1c" variants="A7XX-"/> 146 <value name="CCU_FLUSH_COLOR" value="0x1d" variants="A7XX-"/> 147 <value name="CCU_END_RESOLVE_GROUP" value="0x1f" variants="A7XX-"/> 148 <value name="CCU_CLEAN_DEPTH" value="0x20" variants="A7XX-"/> 149 <value name="CCU_CLEAN_COLOR" value="0x21" variants="A7XX-"/> 150 <value name="CACHE_RESET" value="0x30" variants="A7XX-"/> 151 <value name="CACHE_CLEAN" value="0x31" variants="A7XX-"/> 152 <!-- TODO: deal with name conflicts with other gens --> 153 <value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/> 154 <value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/> 155 <value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/> 156 <value name="CCH_FAST_CLEAR_CLEAN" value="0x1b" variants="A8XX-"/> 157</enum> 158 159<enum name="pc_di_primtype"> 160 <value name="DI_PT_NONE" value="0"/> 161 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: --> 162 <value name="DI_PT_POINTLIST_PSIZE" value="1"/> 163 <value name="DI_PT_LINELIST" value="2"/> 164 <value name="DI_PT_LINESTRIP" value="3"/> 165 <value name="DI_PT_TRILIST" value="4"/> 166 <value name="DI_PT_TRIFAN" value="5"/> 167 <value name="DI_PT_TRISTRIP" value="6"/> 168 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx --> 169 <value name="DI_PT_RECTLIST" value="8"/> 170 <value name="DI_PT_POINTLIST" value="9"/> 171 <value name="DI_PT_LINE_ADJ" value="0xa"/> 172 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> 173 <value name="DI_PT_TRI_ADJ" value="0xc"/> 174 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> 175 176 <value name="DI_PT_PATCHES0" value="0x1f"/> 177 <value name="DI_PT_PATCHES1" value="0x20"/> 178 <value name="DI_PT_PATCHES2" value="0x21"/> 179 <value name="DI_PT_PATCHES3" value="0x22"/> 180 <value name="DI_PT_PATCHES4" value="0x23"/> 181 <value name="DI_PT_PATCHES5" value="0x24"/> 182 <value name="DI_PT_PATCHES6" value="0x25"/> 183 <value name="DI_PT_PATCHES7" value="0x26"/> 184 <value name="DI_PT_PATCHES8" value="0x27"/> 185 <value name="DI_PT_PATCHES9" value="0x28"/> 186 <value name="DI_PT_PATCHES10" value="0x29"/> 187 <value name="DI_PT_PATCHES11" value="0x2a"/> 188 <value name="DI_PT_PATCHES12" value="0x2b"/> 189 <value name="DI_PT_PATCHES13" value="0x2c"/> 190 <value name="DI_PT_PATCHES14" value="0x2d"/> 191 <value name="DI_PT_PATCHES15" value="0x2e"/> 192 <value name="DI_PT_PATCHES16" value="0x2f"/> 193 <value name="DI_PT_PATCHES17" value="0x30"/> 194 <value name="DI_PT_PATCHES18" value="0x31"/> 195 <value name="DI_PT_PATCHES19" value="0x32"/> 196 <value name="DI_PT_PATCHES20" value="0x33"/> 197 <value name="DI_PT_PATCHES21" value="0x34"/> 198 <value name="DI_PT_PATCHES22" value="0x35"/> 199 <value name="DI_PT_PATCHES23" value="0x36"/> 200 <value name="DI_PT_PATCHES24" value="0x37"/> 201 <value name="DI_PT_PATCHES25" value="0x38"/> 202 <value name="DI_PT_PATCHES26" value="0x39"/> 203 <value name="DI_PT_PATCHES27" value="0x3a"/> 204 <value name="DI_PT_PATCHES28" value="0x3b"/> 205 <value name="DI_PT_PATCHES29" value="0x3c"/> 206 <value name="DI_PT_PATCHES30" value="0x3d"/> 207 <value name="DI_PT_PATCHES31" value="0x3e"/> 208</enum> 209 210<enum name="pc_di_src_sel"> 211 <value name="DI_SRC_SEL_DMA" value="0"/> 212 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/> 213 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/> 214 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/> 215</enum> 216 217<enum name="pc_di_face_cull_sel"> 218 <value name="DI_FACE_CULL_NONE" value="0"/> 219 <value name="DI_FACE_CULL_FETCH" value="1"/> 220 <value name="DI_FACE_BACKFACE_CULL" value="2"/> 221 <value name="DI_FACE_FRONTFACE_CULL" value="3"/> 222</enum> 223 224<enum name="pc_di_index_size"> 225 <value name="INDEX_SIZE_IGN" value="0"/> 226 <value name="INDEX_SIZE_16_BIT" value="0"/> 227 <value name="INDEX_SIZE_32_BIT" value="1"/> 228 <value name="INDEX_SIZE_8_BIT" value="2"/> 229 <value name="INDEX_SIZE_INVALID"/> 230</enum> 231 232<enum name="pc_di_vis_cull_mode"> 233 <value name="IGNORE_VISIBILITY" value="0"/> 234 <value name="USE_VISIBILITY" value="1"/> 235</enum> 236 237<enum name="adreno_pm4_packet_type"> 238 <value name="CP_TYPE0_PKT" value="0x00000000"/> 239 <value name="CP_TYPE1_PKT" value="0x40000000"/> 240 <value name="CP_TYPE2_PKT" value="0x80000000"/> 241 <value name="CP_TYPE3_PKT" value="0xc0000000"/> 242 <value name="CP_TYPE4_PKT" value="0x40000000"/> 243 <value name="CP_TYPE7_PKT" value="0x70000000"/> 244</enum> 245 246<!-- 247 Note that in some cases, the same packet id is recycled on a later 248 generation, so variants attribute is used to distinguish. They 249 may not be completely accurate, we would probably have to analyze 250 the pfp and me/pm4 firmware to verify the packet is actually 251 handled on a particular generation. But it is at least enough to 252 disambiguate the packet-id's that were re-used for different 253 packets starting with a5xx. 254 --> 255<enum name="adreno_pm4_type3_packets" varset="chip"> 256 <doc>initialize CP's micro-engine</doc> 257 <value name="CP_ME_INIT" value="0x48"/> 258 <doc>skip N 32-bit words to get to the next packet</doc> 259 <value name="CP_NOP" value="0x10"/> 260 <doc> 261 indirect buffer dispatch. prefetch parser uses this packet 262 type to determine whether to pre-fetch the IB 263 </doc> 264 <value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/> 265 <value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/> 266 <value name="CP_INDIRECT_BUFFER" value="0x3f"/> 267 <doc> 268 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to 269 another buffer at the same level. Must be at the end of IB, and 270 doesn't work with draw state IB's. 271 </doc> 272 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/> 273 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> 274 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> 275 <doc> 276 Waits for the IDLE state of the engine before further drawing. 277 This is pipelined, so the CP may continue. 278 </doc> 279 <value name="CP_WAIT_FOR_IDLE" value="0x26"/> 280 <doc>wait until a register or memory location is a specific value</doc> 281 <value name="CP_WAIT_REG_MEM" value="0x3c"/> 282 <doc>wait until a register location is equal to a specific value</doc> 283 <value name="CP_WAIT_REG_EQ" value="0x52"/> 284 <doc>wait until a register location is >= a specific value</doc> 285 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/> 286 <doc>wait until a read completes</doc> 287 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/> 288 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc> 289 <!-- 290 NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and 291 recycled for something new on a7xx 292 --> 293 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/> 294 <doc>register read/modify/write</doc> 295 <value name="CP_REG_RMW" value="0x21"/> 296 <doc>Set binning configuration registers</doc> 297 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/> 298 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/> 299 <doc>reads register in chip and writes to memory</doc> 300 <value name="CP_REG_TO_MEM" value="0x3e"/> 301 <doc>write N 32-bit words to memory</doc> 302 <value name="CP_MEM_WRITE" value="0x3d"/> 303 <doc>write CP_PROG_COUNTER value to memory</doc> 304 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/> 305 <doc>conditional execution of a sequence of packets</doc> 306 <value name="CP_COND_EXEC" value="0x44"/> 307 <doc>conditional write to memory or register</doc> 308 <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/> 309 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/> 310 <doc>generate an event that creates a write to memory when completed</doc> 311 <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/> 312 <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/> 313 <doc>generate a VS|PS_done event</doc> 314 <value name="CP_EVENT_WRITE_SHD" value="0x58" variants="A2XX"/> 315 <doc>generate a cache flush done event</doc> 316 <value name="CP_EVENT_WRITE_CFL" value="0x59" variants="A2XX"/> 317 <doc>generate a z_pass done event</doc> 318 <value name="CP_EVENT_WRITE_ZPD" value="0x5b" variants="A2XX"/> 319 <doc> 320 not sure the real name, but this seems to be what is used for 321 opencl, instead of CP_DRAW_INDX.. 322 </doc> 323 <value name="CP_RUN_OPENCL" value="0x31"/> 324 <doc>initiate fetch of index buffer and draw</doc> 325 <value name="CP_DRAW_INDX" value="0x22"/> 326 <doc>draw using supplied indices in packet</doc> 327 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx --> 328 <doc>initiate fetch of index buffer and binIDs and draw</doc> 329 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/> 330 <doc>initiate fetch of bin IDs and draw using supplied indices</doc> 331 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/> 332 <doc>begin/end initiator for viz query extent processing</doc> 333 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/> 334 <doc>fetch state sub-blocks and initiate shader code DMAs</doc> 335 <value name="CP_SET_STATE" value="0x25"/> 336 <doc>load constant into chip and to memory</doc> 337 <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/> 338 <doc>load sequencer instruction memory (pointer-based)</doc> 339 <value name="CP_IM_LOAD" value="0x27" variants="A2XX"/> 340 <doc>load sequencer instruction memory (code embedded in packet)</doc> 341 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b" variants="A2XX"/> 342 <doc>load constants from a location in memory</doc> 343 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/> 344 <doc>selective invalidation of state pointers</doc> 345 <value name="CP_INVALIDATE_STATE" value="0x3b"/> 346 <doc>dynamically changes shader instruction memory partition</doc> 347 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/> 348 <doc>sets the 64-bit BIN_MASK register in the PFP</doc> 349 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/> 350 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc> 351 <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/> 352 <doc>updates the current context, if needed</doc> 353 <value name="CP_CONTEXT_UPDATE" value="0x5e"/> 354 <doc>generate interrupt from the command stream</doc> 355 <value name="CP_INTERRUPT" value="0x40"/> 356 <doc>copy sequencer instruction memory to system memory</doc> 357 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/> 358 359 <!-- For a20x --> 360<!-- TODO handle variants.. 361 <doc> 362 Program an offset that will added to the BIN_BASE value of 363 the 3D_DRAW_INDX_BIN packet 364 </doc> 365 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/> 366 --> 367 368 <!-- for a22x --> 369 <doc> 370 sets draw initiator flags register in PFP, gets bitwise-ORed into 371 every draw initiator 372 </doc> 373 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/> 374 <doc>sets the register protection mode</doc> 375 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/> 376 377 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/> 378 379 <!-- for a3xx --> 380 <doc>load high level sequencer command</doc> 381 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> 382 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/> 383 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> 384 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a" variants="A3XX-A5XX"/> 385 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> 386 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> 387 <doc>Load a buffer with pre-fetch enabled</doc> 388 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/> 389 <doc>Set bin (?)</doc> 390 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/> 391 392 <doc>test 2 memory locations to dword values specified</doc> 393 <value name="CP_TEST_TWO_MEMS" value="0x71"/> 394 395 <doc>Write register, ignoring context state for context sensitive registers</doc> 396 <value name="CP_REG_WR_NO_CTXT" value="0x78"/> 397 398 <doc>Record the real-time when this packet is processed by PFP</doc> 399 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/> 400 401 <!-- Used to switch GPU between secure and non-secure modes --> 402 <value name="CP_SET_SECURE_MODE" value="0x66"/> 403 404 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc> 405 <value name="CP_WAIT_FOR_ME" value="0x13"/> 406 407 <!-- for a4xx --> 408 <doc> 409 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple 410 groups of registers. Looks like it can be used to create state 411 objects in GPU memory, and on state change only emit pointer 412 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU 413 overhead: 414 415 (A4x) save PM4 stream pointers to execute upon a visible draw 416 </doc> 417 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/> 418 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/> 419 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/> 420 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/> 421 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/> 422 <value name="CP_DRAW_AUTO" value="0x24"/> 423 424 <doc> 425 Enable or disable predication globally. Also resets the 426 predicate to "passing" and the local bit to enabled when 427 enabling global predication. 428 </doc> 429 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/> 430 431 <doc> 432 Enable or disable predication locally. Unlike globally enabling 433 predication, this packet doesn't touch any other state. 434 Predication only happens when enabled globally and locally and a 435 predicate has been set. This should be used for internal draws 436 which aren't supposed to use the predication state: 437 438 CP_DRAW_PRED_ENABLE_LOCAL(0) 439 ... do draw... 440 CP_DRAW_PRED_ENABLE_LOCAL(1) 441 </doc> 442 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/> 443 444 <doc> 445 Latch a draw predicate into the internal register. 446 </doc> 447 <value name="CP_DRAW_PRED_SET" value="0x4e"/> 448 449 <doc> 450 for A4xx 451 Write to register with address that does not fit into type-0 pkt 452 </doc> 453 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/> 454 455 <doc>copy from ME scratch RAM to a register</doc> 456 <value name="CP_SCRATCH_TO_REG" value="0x4d"/> 457 458 <doc>Copy from REG to ME scratch RAM</doc> 459 <value name="CP_REG_TO_SCRATCH" value="0x4a"/> 460 461 <doc>Wait for memory writes to complete</doc> 462 <value name="CP_WAIT_MEM_WRITES" value="0x12"/> 463 464 <doc>Conditional execution based on register comparison</doc> 465 <value name="CP_COND_REG_EXEC" value="0x47"/> 466 467 <doc>Memory to REG copy</doc> 468 <value name="CP_MEM_TO_REG" value="0x42"/> 469 470 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/> 471 <value name="CP_EXEC_CS" value="0x33"/> 472 473 <doc> 474 for a5xx 475 </doc> 476 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> 477 <!-- switches SMMU pagetable, used on a5xx+ only --> 478 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/> 479 <!-- for a6xx --> 480 <doc>Tells CP the current mode of GPU operation</doc> 481 <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/> 482 <doc>Instruct CP to set a few internal CP registers</doc> 483 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/> 484 <!-- 485 pairs of regid and value.. seems to be used to program some TF 486 related regs: 487 --> 488 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/> 489 <!-- A5XX Enable yield in RB only --> 490 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/> 491 <doc> 492 Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and 493 nothing is left in the visibility stream, then 494 CP_INDIRECT_BUFFER will be skipped, and draws will early return 495 from their IB. 496 </doc> 497 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/> 498 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/> 499 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/> 500 <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/> 501 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/> 502 <!-- Enable/Disable/Defer A5x global preemption model --> 503 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/> 504 <!-- Enable/Disable A5x local preemption model --> 505 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/> 506 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx --> 507 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/> 508 <!-- Inform CP about current render mode (needed for a5xx preemption) --> 509 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/> 510 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/> 511 <!-- check if this works on earlier.. --> 512 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/> 513 514 <doc> 515 General purpose 2D blit engine for image transfers and mipmap 516 generation. Reads through UCHE, writes through the CCU cache in 517 the PS stage. 518 </doc> 519 <value name="CP_BLIT" value="0x2c" variants="A5XX-"/> 520 521 <!-- Test specified bit in specified register and set predicate --> 522 <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/> 523 524 <!-- 525 Seems to set the mode flags which control which CP_SET_DRAW_STATE 526 packets are executed, based on their ENABLE_MASK values 527 528 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 529 packets w/ ENABLE_MASK & 0x6 to execute immediately 530 --> 531 <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/> 532 533 <!-- 534 Seems like there are now separate blocks of state for VS vs FS/CS 535 (probably these amounts to geometry vs fragments so that geometry 536 stage of the pipeline for next draw can start while fragment stage 537 of current draw is still running. The format of the payload of the 538 packets is the same, the only difference is the offsets of the regs 539 the firmware code that handles the packet writes. 540 541 Note that for CL, starting with a6xx, the preferred # of local 542 threads is no longer the same as the max, implying that the shader 543 core can now run warps from unrelated shaders (ie. 544 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs 545 CL_KERNEL_WORK_GROUP_SIZE) 546 --> 547 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/> 548 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/> 549 <!-- 550 Note: For UAV state (Image/SSBOs) which have shared state across 551 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for 552 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are 553 interchangable. 554 --> 555 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/> 556 557 <!-- internal packets: --> 558 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/> 559 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/> 560 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/> 561 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/> 562 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/> 563 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/> 564 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/> 565 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/> 566 567 <!-- internal jumptable entries on a6xx+, possibly a5xx: --> 568 569 <!-- jmptable entry used to handle type4 packet on a5xx+: --> 570 <value name="PKT4" value="0x04" variants="A5XX-"/> 571 <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs --> 572 <value name="IN_IB_END" value="0x0a" variants="A6XX-"/> 573 <!-- handles IFPC save/restore --> 574 <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/> 575 <!-- preemption/context-swtich routine --> 576 <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/> 577 578 <!-- TODO do these exist on A5xx? --> 579 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX-"/> 580 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/> 581 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/> 582 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> 583 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/> 584 <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/> 585 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/> 586 <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values --> 587 <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/> 588 <doc> 589 Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords, 590 and forcibly switch to the indicated context. 591 </doc> 592 <value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/> 593 <value name="CP_SET_AMBLE" value="0x55" variants="A6XX-"/> 594 595 <!-- 596 Seems to always have the payload: 597 00000002 00008801 00004010 598 or: 599 00000002 00008801 00004090 600 or: 601 00000002 00008801 00000010 602 00000002 00008801 00010010 603 00000002 00008801 00d64010 604 ... 605 Note set for compute shaders.. 606 Is 0x8801 a register offset? 607 This appears to be a special sort of register write packet 608 more or less, but the firmware has some special handling.. 609 Seems like it intercepts/modifies certain register offsets, 610 but others are treated like a normal PKT4 reg write. I 611 guess there are some registers that the fw controls certain 612 bits. 613 --> 614 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/> 615 616 <doc> 617 These first appear in a650_sqe.bin. They can in theory be used 618 to loop any sequence of IB1 commands, but in practice they are 619 used to loop over bins. There is a fixed-size per-iteration 620 prefix, used to set per-bin state, and then the following IB1 621 commands are executed until CP_END_BIN which are always the same 622 for each iteration and usually contain a list of 623 CP_INDIRECT_BUFFER calls to IB2 commands which setup state and 624 execute restore/draw/save commands. This replaces the previous 625 technique of just repeating the CP_INDIRECT_BUFFER calls and 626 "unrolling" the loop. 627 </doc> 628 <value name="CP_START_BIN" value="0x50" variants="A6XX-"/> 629 <value name="CP_END_BIN" value="0x51" variants="A6XX-"/> 630 631 <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc> 632 <value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/> 633 634 <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/> 635 <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword --> 636 <value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 --> 637 <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/> 638 <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?--> 639 <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/> 640 <doc> Can clear BV/BR counters, or wait until one catches up to another </doc> 641 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/> 642 <doc> Clears, adds to local, or adds to global timestamp </doc> 643 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/> 644 <value name="CP_NON_CONTEXT_REG_BUNCH" value="0x5d" variants="A7XX-"/> 645 <doc> 646 Write to a scratch memory that is read by CP_REG_TEST with 647 SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. 648 However it uses the same memory space. 649 </doc> 650 <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/> 651 652 <doc> 653 Executes an array of fixed-size command buffers where each 654 buffer is assumed to have one draw call, skipping buffers with 655 non-visible draw calls. 656 </doc> 657 <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/> 658 659 <doc>Reset various on-chip state used for synchronization</doc> 660 <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/> 661 662 <doc>Invalidates the "CCHE" introduced on a740</doc> 663 <value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/> 664 665 <value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/> 666 667 <value name="CP_SKIP_IB_MODE" value="0x27" variants="A7XX-"/> 668 669 <value name="CP_MEMORY_MAP_UPDATE" value="0x58" variants="A8XX-"/> 670 671 <value name="CP_BARRIER" value="0x59" variants="A8XX-"/> 672</enum> 673 674 675<domain name="CP_LOAD_STATE" width="32"> 676 <doc>Load state, a3xx (and later?)</doc> 677 <enum name="adreno_state_block"> 678 <value name="SB_VERT_TEX" value="0"/> 679 <value name="SB_VERT_MIPADDR" value="1"/> 680 <value name="SB_FRAG_TEX" value="2"/> 681 <value name="SB_FRAG_MIPADDR" value="3"/> 682 <value name="SB_VERT_SHADER" value="4"/> 683 <value name="SB_GEOM_SHADER" value="5"/> 684 <value name="SB_FRAG_SHADER" value="6"/> 685 <value name="SB_COMPUTE_SHADER" value="7"/> 686 </enum> 687 <enum name="adreno_state_type"> 688 <value name="ST_SHADER" value="0"/> 689 <value name="ST_CONSTANTS" value="1"/> 690 </enum> 691 <enum name="adreno_state_src"> 692 <value name="SS_DIRECT" value="0"> 693 <doc>inline with the CP_LOAD_STATE packet</doc> 694 </value> 695 <value name="SS_INVALID_ALL_IC" value="2"/> 696 <value name="SS_INVALID_PART_IC" value="3"/> 697 <value name="SS_INDIRECT" value="4"> 698 <doc>in buffer pointed to by EXT_SRC_ADDR</doc> 699 </value> 700 <value name="SS_INDIRECT_TCM" value="5"/> 701 <value name="SS_INDIRECT_STM" value="6"/> 702 </enum> 703 <reg32 offset="0" name="0"> 704 <bitfield name="DST_OFF" low="0" high="15" type="uint"/> 705 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/> 706 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/> 707 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 708 </reg32> 709 <reg32 offset="1" name="1"> 710 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/> 711 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 712 </reg32> 713</domain> 714 715<domain name="CP_LOAD_STATE4" width="32" varset="chip"> 716 <doc>Load state, a4xx+</doc> 717 <enum name="a4xx_state_block"> 718 <!-- 719 unknown: 0x7 and 0xf <- seen in compute shader 720 721 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? 722 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains 723 the gpuaddr of the following shader constants block. DST_OFF seems 724 to specify which shader stage: 725 726 16 -> vert 727 36 -> tcs 728 56 -> tes 729 76 -> geom 730 96 -> frag 731 732 Example: 733 734opcode: CP_LOAD_STATE4 (30) (12 dwords) 735 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } 736 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 } 737 { EXT_SRC_ADDR_HI = 0 } 738 0000: c0264100 00000000 00000000 00000000 739 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000 740 741opcode: CP_LOAD_STATE4 (30) (4 dwords) 742 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 743 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 } 744 { EXT_SRC_ADDR_HI = 0 } 745 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 746 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 747 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 748 749 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords. 750 751 --> 752 <value name="SB4_VS_TEX" value="0x0"/> 753 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS --> 754 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES --> 755 <value name="SB4_GS_TEX" value="0x3"/> 756 <value name="SB4_FS_TEX" value="0x4"/> 757 <value name="SB4_CS_TEX" value="0x5"/> 758 <value name="SB4_VS_SHADER" value="0x8"/> 759 <value name="SB4_HS_SHADER" value="0x9"/> 760 <value name="SB4_DS_SHADER" value="0xa"/> 761 <value name="SB4_GS_SHADER" value="0xb"/> 762 <value name="SB4_FS_SHADER" value="0xc"/> 763 <value name="SB4_CS_SHADER" value="0xd"/> 764 <!-- 765 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each), 766 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each) 767 768 Compute has it's own dedicated SSBO state, it seems, but the rest 769 of the stages share state 770 --> 771 <value name="SB4_SSBO" value="0xe"/> 772 <value name="SB4_CS_SSBO" value="0xf"/> 773 </enum> 774 <enum name="a4xx_state_type"> 775 <value name="ST4_SHADER" value="0"/> 776 <value name="ST4_CONSTANTS" value="1"/> 777 <value name="ST4_UBO" value="2"/> 778 </enum> 779 <enum name="a4xx_state_src"> 780 <value name="SS4_DIRECT" value="0"/> 781 <value name="SS4_INDIRECT" value="2"/> 782 </enum> 783 <reg32 offset="0" name="0"> 784 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 785 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/> 786 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/> 787 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 788 </reg32> 789 <reg32 offset="1" name="1"> 790 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/> 791 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 792 </reg32> 793 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 794 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 795 </reg32> 796</domain> 797 798<!-- looks basically same CP_LOAD_STATE4 --> 799<domain name="CP_LOAD_STATE6" width="32" varset="chip"> 800 <doc>Load state, a6xx+</doc> 801 <enum name="a6xx_state_block"> 802 <value name="SB6_VS_TEX" value="0x0"/> 803 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS --> 804 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES --> 805 <value name="SB6_GS_TEX" value="0x3"/> 806 <value name="SB6_FS_TEX" value="0x4"/> 807 <value name="SB6_CS_TEX" value="0x5"/> 808 <value name="SB6_VS_SHADER" value="0x8"/> 809 <value name="SB6_HS_SHADER" value="0x9"/> 810 <value name="SB6_DS_SHADER" value="0xa"/> 811 <value name="SB6_GS_SHADER" value="0xb"/> 812 <value name="SB6_FS_SHADER" value="0xc"/> 813 <value name="SB6_CS_SHADER" value="0xd"/> 814 <value name="SB6_UAV" value="0xe"/> 815 <value name="SB6_CS_UAV" value="0xf"/> 816 </enum> 817 <enum name="a6xx_state_type"> 818 <value name="ST6_SHADER" value="0"/> 819 <value name="ST6_CONSTANTS" value="1"/> 820 <value name="ST6_UBO" value="2"/> 821 <value name="ST6_UAV" value="3"/> 822 </enum> 823 <enum name="a6xx_state_src"> 824 <value name="SS6_DIRECT" value="0"/> 825 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? --> 826 <value name="SS6_INDIRECT" value="2"/> 827 <doc> 828 SS6_UBO used by the a6xx vulkan blob with tesselation constants 829 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset) 830 to load constants from a UBO loaded with DST_OFF = 14 and offset 0, 831 EXT_SRC_ADDR = 0xe0000 832 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k) 833 </doc> 834 <value name="SS6_UBO" value="3"/> 835 </enum> 836 <reg32 offset="0" name="0"> 837 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 838 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/> 839 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/> 840 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/> 841 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 842 </reg32> 843 <reg32 offset="1" name="1"> 844 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 845 </reg32> 846 <reg32 offset="2" name="2"> 847 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 848 </reg32> 849 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/> 850</domain> 851 852<bitset name="vgt_draw_initiator" inline="yes"> 853 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 854 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 855 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/> 856 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/> 857 <bitfield name="NOT_EOP" pos="12" type="boolean"/> 858 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/> 859 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/> 860 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/> 861</bitset> 862 863<!-- changed on a4xx: --> 864<enum name="a4xx_index_size"> 865 <value name="INDEX4_SIZE_8_BIT" value="0"/> 866 <value name="INDEX4_SIZE_16_BIT" value="1"/> 867 <value name="INDEX4_SIZE_32_BIT" value="2"/> 868</enum> 869 870<enum name="a6xx_patch_type"> 871 <value name="TESS_QUADS" value="0"/> 872 <value name="TESS_TRIANGLES" value="1"/> 873 <value name="TESS_ISOLINES" value="2"/> 874</enum> 875 876<bitset name="vgt_draw_initiator_a4xx" inline="yes"> 877 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 --> 878 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 879 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 880 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> 881 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> 882 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> 883 <bitfield name="GS_ENABLE" pos="16" type="boolean"/> 884 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> 885</bitset> 886 887<domain name="CP_DRAW_INDX" width="32"> 888 <reg32 offset="0" name="0"> 889 <bitfield name="VIZ_QUERY" low="0" high="31"/> 890 </reg32> 891 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 892 <reg32 offset="2" name="2"> 893 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 894 </reg32> 895 <reg32 offset="3" name="3"> 896 <bitfield name="INDX_BASE" low="0" high="31"/> 897 </reg32> 898 <reg32 offset="4" name="4"> 899 <bitfield name="INDX_SIZE" low="0" high="31"/> 900 </reg32> 901</domain> 902 903<domain name="CP_DRAW_INDX_2" width="32"> 904 <reg32 offset="0" name="0"> 905 <bitfield name="VIZ_QUERY" low="0" high="31"/> 906 </reg32> 907 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 908 <reg32 offset="2" name="2"> 909 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 910 </reg32> 911 <!-- followed by NUM_INDICES indices.. --> 912</domain> 913 914<domain name="CP_DRAW_INDX_OFFSET" width="32"> 915 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 916 <reg32 offset="1" name="1"> 917 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 918 </reg32> 919 <reg32 offset="2" name="2"> 920 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 921 </reg32> 922 <reg32 offset="3" name="3"> 923 <bitfield name="FIRST_INDX" low="0" high="31"/> 924 </reg32> 925 926 <stripe varset="chip" variants="A5XX-"> 927 <reg64 offset="4" name="INDX_BASE" type="address"/> 928 <reg32 offset="6" name="6"> 929 <!-- max # of elements in index buffer --> 930 <bitfield name="MAX_INDICES" low="0" high="31"/> 931 </reg32> 932 </stripe> 933 934 <reg32 offset="4" name="4"> 935 <bitfield name="INDX_BASE" low="0" high="31" type="address"/> 936 </reg32> 937 938 <reg32 offset="5" name="5"> 939 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 940 </reg32> 941</domain> 942 943<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 944 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 945 <stripe varset="chip" variants="A4XX"> 946 <reg32 offset="1" name="1"> 947 <bitfield name="INDIRECT" low="0" high="31"/> 948 </reg32> 949 </stripe> 950 <stripe varset="chip" variants="A5XX-"> 951 <reg32 offset="1" name="1"> 952 <bitfield name="INDIRECT_LO" low="0" high="31"/> 953 </reg32> 954 <reg32 offset="2" name="2"> 955 <bitfield name="INDIRECT_HI" low="0" high="31"/> 956 </reg32> 957 <reg64 offset="1" name="INDIRECT" type="address"/> 958 </stripe> 959</domain> 960 961<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 962 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 963 <stripe varset="chip" variants="A4XX"> 964 <reg32 offset="1" name="1"> 965 <bitfield name="INDX_BASE" low="0" high="31"/> 966 </reg32> 967 <reg32 offset="2" name="2"> 968 <!-- max # of bytes in index buffer --> 969 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 970 </reg32> 971 <reg32 offset="3" name="3"> 972 <bitfield name="INDIRECT" low="0" high="31"/> 973 </reg32> 974 </stripe> 975 <stripe varset="chip" variants="A5XX-"> 976 <reg32 offset="1" name="1"> 977 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 978 </reg32> 979 <reg32 offset="2" name="2"> 980 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 981 </reg32> 982 <reg64 offset="1" name="INDX_BASE" type="address"/> 983 <reg32 offset="3" name="3"> 984 <!-- max # of elements in index buffer --> 985 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/> 986 </reg32> 987 <reg32 offset="4" name="4"> 988 <bitfield name="INDIRECT_LO" low="0" high="31"/> 989 </reg32> 990 <reg32 offset="5" name="5"> 991 <bitfield name="INDIRECT_HI" low="0" high="31"/> 992 </reg32> 993 <reg64 offset="4" name="INDIRECT" type="address"/> 994 </stripe> 995</domain> 996 997<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-"> 998 <enum name="a6xx_draw_indirect_opcode"> 999 <value name="INDIRECT_OP_NORMAL" value="0x2"/> 1000 <value name="INDIRECT_OP_INDEXED" value="0x4"/> 1001 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/> 1002 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/> 1003 </enum> 1004 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 1005 <reg32 offset="1" name="1"> 1006 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/> 1007 <doc> 1008 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will 1009 be updated for each draw to {draw_id, first_vertex, first_instance, 0} 1010 value of 0 disables it 1011 </doc> 1012 <bitfield name="DST_OFF" low="8" high="21" type="hex"/> 1013 </reg32> 1014 <reg32 offset="2" name="DRAW_COUNT" type="uint"/> 1015 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL"> 1016 <reg64 offset="3" name="INDIRECT" type="address"/> 1017 <reg32 offset="5" name="STRIDE" type="uint"/> 1018 </stripe> 1019 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED"> 1020 <reg64 offset="3" name="INDEX" type="address"/> 1021 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 1022 <reg64 offset="6" name="INDIRECT" type="address"/> 1023 <reg32 offset="8" name="STRIDE" type="uint"/> 1024 </stripe> 1025 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT"> 1026 <reg64 offset="3" name="INDIRECT" type="address"/> 1027 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/> 1028 <reg32 offset="7" name="STRIDE" type="uint"/> 1029 </stripe> 1030 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED"> 1031 <reg64 offset="3" name="INDEX" type="address"/> 1032 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 1033 <reg64 offset="6" name="INDIRECT" type="address"/> 1034 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/> 1035 <reg32 offset="10" name="STRIDE" type="uint"/> 1036 </stripe> 1037</domain> 1038 1039<domain name="CP_DRAW_AUTO" width="32"> 1040 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 1041 <reg32 offset="1" name="1"> 1042 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 1043 </reg32> 1044 <reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/> 1045 <reg32 offset="4" name="4"> 1046 <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/> 1047 </reg32> 1048 <reg32 offset="5" name="5"> 1049 <bitfield name="STRIDE" low="0" high="31" type="uint"/> 1050 </reg32> 1051</domain> 1052 1053<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip"> 1054 <reg32 offset="0" name="0"> 1055 <bitfield name="ENABLE" pos="0" type="boolean"/> 1056 </reg32> 1057</domain> 1058 1059<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip"> 1060 <reg32 offset="0" name="0"> 1061 <bitfield name="ENABLE" pos="0" type="boolean"/> 1062 </reg32> 1063</domain> 1064 1065<domain name="CP_DRAW_PRED_SET" width="32" varset="chip"> 1066 <enum name="cp_draw_pred_src"> 1067 <!-- 1068 Sources 1-4 seem to be about combining reading 1069 SO/primitive queries and setting the predicate, which is 1070 a DX11-specific optimization (since in DX11 you can only 1071 predicate on the result of queries). 1072 --> 1073 <value name="PRED_SRC_MEM" value="5"> 1074 <doc> 1075 Read a 64-bit value at the given address and 1076 test if it equals/doesn't equal 0. 1077 </doc> 1078 </value> 1079 </enum> 1080 <enum name="cp_draw_pred_test"> 1081 <value name="NE_0_PASS" value="0"/> 1082 <value name="EQ_0_PASS" value="1"/> 1083 </enum> 1084 <reg32 offset="0" name="0"> 1085 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/> 1086 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/> 1087 </reg32> 1088 <reg64 offset="1" name="MEM_ADDR" type="address"/> 1089</domain> 1090 1091<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-"> 1092 <array offset="0" stride="3" length="100"> 1093 <reg32 offset="0" name="0"> 1094 <bitfield name="COUNT" low="0" high="15" type="uint"/> 1095 <bitfield name="DIRTY" pos="16" type="boolean"/> 1096 <bitfield name="DISABLE" pos="17" type="boolean"/> 1097 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> 1098 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> 1099 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 1100 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 1101 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 1102 <!-- high bit is 28 until a750: --> 1103 <bitfield name="GROUP_ID" low="24" high="29" type="uint"/> 1104 </reg32> 1105 <reg64 offset="1" name="ADDR" type="address"/> 1106 <reg32 offset="1" name="1"> 1107 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 1108 </reg32> 1109 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1110 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/> 1111 </reg32> 1112 </array> 1113</domain> 1114 1115<domain name="CP_SET_BIN" width="32"> 1116 <doc>value at offset 0 always seems to be 0x00000000..</doc> 1117 <reg32 offset="0" name="0"/> 1118 <reg32 offset="1" name="1"> 1119 <bitfield name="X1" low="0" high="15" type="uint"/> 1120 <bitfield name="Y1" low="16" high="31" type="uint"/> 1121 </reg32> 1122 <reg32 offset="2" name="2"> 1123 <bitfield name="X2" low="0" high="15" type="uint"/> 1124 <bitfield name="Y2" low="16" high="31" type="uint"/> 1125 </reg32> 1126</domain> 1127 1128<domain name="CP_SET_BIN_DATA" width="32"> 1129 <reg32 offset="0" name="0"> 1130 <!-- corresponds to VSC_PIPE[n].DATA_ADDR --> 1131 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/> 1132 </reg32> 1133 <reg32 offset="1" name="1"> 1134 <!-- seesm to correspond to VSC_SIZE_ADDRESS --> 1135 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/> 1136 </reg32> 1137</domain> 1138 1139<enum name="a7xx_abs_mask_mode"> 1140 <value name="ABS_MASK" value="0x1"/> 1141 <value name="NO_ABS_MASK" value="0x0"/> 1142</enum> 1143 1144<domain name="CP_SET_BIN_DATA5" width="32"> 1145 <reg32 offset="0" name="0"> 1146 <bitfield name="VSC_MASK" low="0" high="15" type="hex"> 1147 <doc> 1148 A mask of bins, starting at VSC_N, whose 1149 visibility is OR'd together. A value of 0 is 1150 interpreted as 1 (i.e. just use VSC_N for 1151 visbility) for backwards compatibility. Only 1152 exists on a7xx. 1153 </doc> 1154 </bitfield> 1155 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1156 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1157 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1158 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1159 <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"> 1160 <doc> 1161 If this field is 1, VSC_MASK and VSC_N are 1162 ignored and instead a new ordinal immediately 1163 after specifies the full 32-bit mask of bins 1164 to use. The mask is "absolute" instead of 1165 relative to VSC_N. 1166 </doc> 1167 </bitfield> 1168 </reg32> 1169 <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1170 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1171 <reg64 offset="1" name="BIN_DATA_ADDR" type="address"/> 1172 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1173 <reg64 offset="3" name="BIN_SIZE_ADDR" type="address"/> 1174 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1175 <reg64 offset="5" name="BIN_PRIM_STRM" type="address"/> 1176 <!-- 1177 a7xx adds a few more addresses to the end of the pkt 1178 --> 1179 <reg64 offset="7" name="7"/> 1180 <reg64 offset="9" name="9"/> 1181 </stripe> 1182 <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1183 <reg32 offset="1" name="ABS_MASK"/> 1184 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1185 <reg64 offset="2" name="BIN_DATA_ADDR" type="address"/> 1186 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1187 <reg64 offset="4" name="BIN_SIZE_ADDR" type="address"/> 1188 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1189 <reg64 offset="6" name="BIN_PRIM_STRM" type="address"/> 1190 <!-- 1191 a7xx adds a few more addresses to the end of the pkt 1192 --> 1193 <reg64 offset="8" name="8"/> 1194 <reg64 offset="10" name="10"/> 1195 </stripe> 1196</domain> 1197 1198<domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> 1199 <doc> 1200 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the 1201 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful 1202 for Vulkan where these values aren't known when the command 1203 stream is recorded. 1204 </doc> 1205 <reg32 offset="0" name="0"> 1206 <bitfield name="VSC_MASK" low="0" high="15" type="hex"/> 1207 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1208 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1209 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1210 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1211 <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"/> 1212 </reg32> 1213 <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1214 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1215 <reg32 offset="1" name="1"> 1216 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1217 </reg32> 1218 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1219 <reg32 offset="2" name="2"> 1220 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1221 </reg32> 1222 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1223 <reg32 offset="3" name="3"> 1224 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1225 </reg32> 1226 </stripe> 1227 <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1228 <reg32 offset="1" name="ABS_MASK"/> 1229 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1230 <reg32 offset="2" name="2"> 1231 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1232 </reg32> 1233 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1234 <reg32 offset="3" name="3"> 1235 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1236 </reg32> 1237 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1238 <reg32 offset="4" name="4"> 1239 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1240 </reg32> 1241 </stripe> 1242</domain> 1243 1244<domain name="CP_REG_RMW" width="32"> 1245 <doc> 1246 Modifies DST_REG using two sources that can either be registers 1247 or immediates. If SRC1_ADD is set, then do the following: 1248 1249 $dst = (($dst & $src0) rot $rotate) + $src1 1250 1251 Otherwise: 1252 1253 $dst = (($dst & $src0) rot $rotate) | $src1 1254 1255 Here "rot" means rotate left. 1256 </doc> 1257 <reg32 offset="0" name="0"> 1258 <bitfield name="DST_REG" low="0" high="17" type="hex"/> 1259 <bitfield name="DST_SCRATCH" pos="19" type="boolean" varset="chip" variants="A7XX-"/> 1260 <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> 1261 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" type="boolean" varset="chip" variants="A7XX-"/> 1262 <bitfield name="ROTATE" low="24" high="28" type="uint"/> 1263 <bitfield name="SRC1_ADD" pos="29" type="boolean"/> 1264 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> 1265 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/> 1266 </reg32> 1267 <reg32 offset="1" name="1"> 1268 <bitfield name="SRC0" low="0" high="31" type="uint"/> 1269 </reg32> 1270 <reg32 offset="2" name="2"> 1271 <bitfield name="SRC1" low="0" high="31" type="uint"/> 1272 </reg32> 1273</domain> 1274 1275<domain name="CP_REG_TO_MEM" width="32" prefix="chip"> 1276 <reg32 offset="0" name="0"> 1277 <bitfield name="REG" low="0" high="17" type="hex"/> 1278 <!-- number of registers/dwords copied is max(CNT, 1). --> 1279 <bitfield name="CNT" low="18" high="29" type="uint"/> 1280 <bitfield name="64B" pos="30" type="boolean"/> 1281 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1282 </reg32> 1283 <stripe varset="chip" variants="A2XX-A4XX"> 1284 <reg32 offset="1" name="DEST" type="address"/> 1285 </stripe> 1286 <stripe varset="chip" variants="A5XX-"> 1287 <reg64 offset="1" name="DEST" type="address"/> 1288 </stripe> 1289</domain> 1290 1291<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> 1292 <doc> 1293 Like CP_REG_TO_MEM, but the memory address to write to can be 1294 offsetted using either one or two registers or scratch 1295 registers. 1296 </doc> 1297 <reg32 offset="0" name="0"> 1298 <bitfield name="REG" low="0" high="17" type="hex"/> 1299 <!-- number of registers/dwords copied is max(CNT, 1). --> 1300 <bitfield name="CNT" low="18" high="29" type="uint"/> 1301 <bitfield name="64B" pos="30" type="boolean"/> 1302 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1303 </reg32> 1304 <reg64 offset="1" name="DEST" type="waddress"/> 1305 <reg32 offset="3" name="3"> 1306 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1307 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> 1308 </reg32> 1309 <!-- followed by an optional identical OFFSET1 dword --> 1310</domain> 1311 1312<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32"> 1313 <doc> 1314 Like CP_REG_TO_MEM, but the memory address to write to can be 1315 offsetted using a DWORD in memory. 1316 </doc> 1317 <reg32 offset="0" name="0"> 1318 <bitfield name="REG" low="0" high="17" type="hex"/> 1319 <!-- number of registers/dwords copied is max(CNT, 1). --> 1320 <bitfield name="CNT" low="18" high="29" type="uint"/> 1321 <bitfield name="64B" pos="30" type="boolean"/> 1322 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1323 </reg32> 1324 <reg64 offset="1" name="DEST" type="waddress"/> 1325 <reg64 offset="3" name="OFFSET" type="waddress"/> 1326</domain> 1327 1328<domain name="CP_MEM_TO_REG" width="32"> 1329 <reg32 offset="0" name="0"> 1330 <bitfield name="REG" low="0" high="17" type="hex"/> 1331 <!-- number of registers/dwords copied is max(CNT, 1). --> 1332 <bitfield name="CNT" low="19" high="29" type="uint"/> 1333 <!-- shift each DWORD left by 2 while copying --> 1334 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> 1335 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1336 <bitfield name="UNK31" pos="31" type="boolean"/> 1337 </reg32> 1338 <stripe varset="chip" variants="A2XX-A4XX"> 1339 <reg32 offset="1" name="SRC" type="address"/> 1340 </stripe> 1341 <stripe varset="chip" variants="A5XX-"> 1342 <reg64 offset="1" name="SRC" type="address"/> 1343 </stripe> 1344</domain> 1345 1346<domain name="CP_MEM_TO_MEM" width="32"> 1347 <reg32 offset="0" name="0"> 1348 <!-- 1349 not sure how many src operands we have, but the low 1350 bits negate the n'th src argument. 1351 --> 1352 <bitfield name="NEG_A" pos="0" type="boolean"/> 1353 <bitfield name="NEG_B" pos="1" type="boolean"/> 1354 <bitfield name="NEG_C" pos="2" type="boolean"/> 1355 1356 <!-- if set treat src/dst as 64bit values --> 1357 <bitfield name="DOUBLE" pos="29" type="boolean"/> 1358 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> 1359 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> 1360 <!-- some other kind of wait --> 1361 <bitfield name="UNK31" pos="31" type="boolean"/> 1362 </reg32> 1363 <reg64 offset="1" name="DST" type="waddress"/> 1364 <reg64 offset="3" name="SRC_A" type="address"/> 1365 <reg64 offset="5" name="SRC_B" type="address"/> 1366 <reg64 offset="7" name="SRC_C" type="address"/> 1367 <!-- 1368 followed by sequence of addresses.. the first is the 1369 destination and the rest are N src addresses which are 1370 summed (after being negated if NEG_x bit set) allowing 1371 to do things like 'result += end - start' (which turns 1372 out to be useful for queries and accumulating results 1373 across multiple tiles) 1374 --> 1375</domain> 1376 1377<domain name="CP_MEMCPY" width="32"> 1378 <reg32 offset="0" name="0"> 1379 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1380 </reg32> 1381 <reg32 offset="1" name="1"> 1382 <bitfield name="SRC_LO" low="0" high="31" type="hex"/> 1383 </reg32> 1384 <reg32 offset="2" name="2"> 1385 <bitfield name="SRC_HI" low="0" high="31" type="hex"/> 1386 </reg32> 1387 <reg32 offset="3" name="3"> 1388 <bitfield name="DST_LO" low="0" high="31" type="hex"/> 1389 </reg32> 1390 <reg32 offset="4" name="4"> 1391 <bitfield name="DST_HI" low="0" high="31" type="hex"/> 1392 </reg32> 1393</domain> 1394 1395<domain name="CP_REG_TO_SCRATCH" width="32"> 1396 <reg32 offset="0" name="0"> 1397 <bitfield name="REG" low="0" high="17" type="hex"/> 1398 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1399 <!-- number of registers/dwords copied is CNT + 1. --> 1400 <bitfield name="CNT" low="24" high="26" type="uint"/> 1401 <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> 1402 <bitfield name="SKIP_WAIT_FOR_ME" pos="27" type="boolean" varset="chip" variants="A7XX-"/> 1403 </reg32> 1404</domain> 1405 1406<domain name="CP_SCRATCH_TO_REG" width="32"> 1407 <reg32 offset="0" name="0"> 1408 <bitfield name="REG" low="0" high="17" type="hex"/> 1409 <!-- note: CP_MEM_TO_REG always sets this when writing to the register --> 1410 <bitfield name="UNK18" pos="18" type="boolean"/> 1411 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1412 <!-- number of registers/dwords copied is CNT + 1. --> 1413 <bitfield name="CNT" low="24" high="26" type="uint"/> 1414 </reg32> 1415</domain> 1416 1417<domain name="CP_SCRATCH_WRITE" width="32"> 1418 <reg32 offset="0" name="0"> 1419 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1420 </reg32> 1421 <!-- followed by one or more DWORDs to write to scratch registers --> 1422</domain> 1423 1424<domain name="CP_MEM_WRITE" width="32"> 1425 <stripe varset="chip" variants="A2XX-A4XX"> 1426 <reg32 offset="0" name="ADDR" type="address"/> 1427 </stripe> 1428 <stripe varset="chip" variants="A5XX-"> 1429 <reg64 offset="0" name="ADDR" type="address"/> 1430 </stripe> 1431 <!-- followed by the DWORDs to write --> 1432</domain> 1433 1434<enum name="cp_cond_function"> 1435 <value value="0" name="WRITE_ALWAYS"/> 1436 <value value="1" name="WRITE_LT"/> 1437 <value value="2" name="WRITE_LE"/> 1438 <value value="3" name="WRITE_EQ"/> 1439 <value value="4" name="WRITE_NE"/> 1440 <value value="5" name="WRITE_GE"/> 1441 <value value="6" name="WRITE_GT"/> 1442</enum> 1443 1444<domain name="CP_COND_WRITE" width="32"> 1445 <reg32 offset="0" name="0"> 1446 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1447 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1448 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1449 </reg32> 1450 <reg32 offset="1" name="1"> 1451 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/> 1452 </reg32> 1453 <reg32 offset="2" name="2"> 1454 <bitfield name="REF" low="0" high="31"/> 1455 </reg32> 1456 <reg32 offset="3" name="3"> 1457 <bitfield name="MASK" low="0" high="31"/> 1458 </reg32> 1459 <reg32 offset="4" name="4"> 1460 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/> 1461 </reg32> 1462 <reg32 offset="5" name="5"> 1463 <bitfield name="WRITE_DATA" low="0" high="31"/> 1464 </reg32> 1465</domain> 1466 1467<enum name="poll_memory_type"> 1468 <value value="0" name="POLL_REGISTER"/> 1469 <value value="1" name="POLL_MEMORY"/> 1470 <value value="2" name="POLL_SCRATCH"/> 1471 <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/> 1472</enum> 1473 1474<domain name="CP_COND_WRITE5" width="32"> 1475 <reg32 offset="0" name="0"> 1476 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1477 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1478 <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. --> 1479 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1480 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1481 </reg32> 1482 <reg64 offset="1" name="POLL_ADDR" type="address"/> 1483 <reg32 offset="3" name="3"> 1484 <bitfield name="REF" low="0" high="31"/> 1485 </reg32> 1486 <reg32 offset="4" name="4"> 1487 <bitfield name="MASK" low="0" high="31"/> 1488 </reg32> 1489 <reg64 offset="5" name="WRITE_ADDR" type="waddress"/> 1490 <reg32 offset="7" name="7"> 1491 <bitfield name="WRITE_DATA" low="0" high="31"/> 1492 </reg32> 1493</domain> 1494 1495<domain name="CP_WAIT_MEM_GTE" width="32"> 1496 <doc> 1497 Wait until a memory value is greater than or equal to the 1498 reference, using signed comparison. 1499 </doc> 1500 <reg32 offset="0" name="0"> 1501 <!-- Reserved for flags, presumably? Unused in FW --> 1502 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1503 </reg32> 1504 <reg64 offset="1" name="POLL_ADDR" type="address"/> 1505 <reg32 offset="3" name="3"> 1506 <bitfield name="REF" low="0" high="31"/> 1507 </reg32> 1508</domain> 1509 1510<domain name="CP_WAIT_REG_MEM" width="32"> 1511 <doc> 1512 This uses the same internal comparison as CP_COND_WRITE, 1513 but waits until the comparison is true instead. It busy-loops in 1514 the CP for the given number of cycles before trying again. 1515 </doc> 1516 <reg32 offset="0" name="0"> 1517 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1518 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1519 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1520 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1521 </reg32> 1522 <reg64 offset="1" name="POLL_ADDR" type="address"/> 1523 <reg32 offset="3" name="3"> 1524 <bitfield name="REF" low="0" high="31"/> 1525 </reg32> 1526 <reg32 offset="4" name="4"> 1527 <bitfield name="MASK" low="0" high="31"/> 1528 </reg32> 1529 <reg32 offset="5" name="5"> 1530 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/> 1531 </reg32> 1532</domain> 1533 1534<domain name="CP_WAIT_TWO_REGS" width="32"> 1535 <doc> 1536 Waits for REG0 to not be 0 or REG1 to not equal REF 1537 </doc> 1538 <reg32 offset="0" name="0"> 1539 <bitfield name="REG0" low="0" high="17" type="hex"/> 1540 </reg32> 1541 <reg32 offset="1" name="1"> 1542 <bitfield name="REG1" low="0" high="17" type="hex"/> 1543 </reg32> 1544 <reg32 offset="2" name="2"> 1545 <bitfield name="REF" low="0" high="31" type="uint"/> 1546 </reg32> 1547</domain> 1548 1549<domain name="CP_DISPATCH_COMPUTE" width="32"> 1550 <reg32 offset="0" name="0"/> 1551 <reg32 offset="1" name="1"> 1552 <bitfield name="X" low="0" high="31"/> 1553 </reg32> 1554 <reg32 offset="2" name="2"> 1555 <bitfield name="Y" low="0" high="31"/> 1556 </reg32> 1557 <reg32 offset="3" name="3"> 1558 <bitfield name="Z" low="0" high="31"/> 1559 </reg32> 1560</domain> 1561 1562<domain name="CP_SET_RENDER_MODE" width="32"> 1563 <enum name="render_mode_cmd"> 1564 <value value="1" name="BYPASS"/> 1565 <value value="2" name="BINNING"/> 1566 <value value="3" name="GMEM"/> 1567 <value value="5" name="BLIT2D"/> 1568 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? --> 1569 <value value="7" name="BLIT2DSCALE"/> 1570 <!-- 8 set before going back to BYPASS exiting 2D --> 1571 <value value="8" name="END2D"/> 1572 </enum> 1573 <reg32 offset="0" name="0"> 1574 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/> 1575 <!-- 1576 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in 1577 0x21xx range.. possibly (at least some) a5xx variants have a 1578 2d core? 1579 --> 1580 </reg32> 1581 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1582 <reg32 offset="1" name="1"> 1583 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1584 </reg32> 1585 <reg32 offset="2" name="2"> 1586 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1587 </reg32> 1588 <reg32 offset="3" name="3"> 1589 <!-- 1590 set when in GMEM.. maybe indicates GMEM contents need to be 1591 preserved on ctx switch? 1592 --> 1593 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/> 1594 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/> 1595 </reg32> 1596 <reg32 offset="4" name="4"/> 1597 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1598 <reg32 offset="5" name="5"> 1599 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1600 </reg32> 1601 <reg32 offset="6" name="6"> 1602 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1603 </reg32> 1604 <reg32 offset="7" name="7"> 1605 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1606 </reg32> 1607</domain> 1608 1609<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword --> 1610<domain name="CP_COMPUTE_CHECKPOINT" width="32"> 1611 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1612 <reg32 offset="0" name="0"> 1613 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1614 </reg32> 1615 <reg32 offset="1" name="1"> 1616 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1617 </reg32> 1618 <reg32 offset="2" name="2"> 1619 </reg32> 1620 <reg32 offset="3" name="3"/> 1621 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1622 <reg32 offset="4" name="4"> 1623 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1624 </reg32> 1625 <reg32 offset="5" name="5"> 1626 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1627 </reg32> 1628 <reg32 offset="6" name="6"> 1629 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1630 </reg32> 1631 <reg32 offset="7" name="7"/> 1632</domain> 1633 1634<domain name="CP_PERFCOUNTER_ACTION" width="32"> 1635 <reg32 offset="0" name="0"> 1636 </reg32> 1637 <reg32 offset="1" name="1"> 1638 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1639 </reg32> 1640 <reg32 offset="2" name="2"> 1641 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1642 </reg32> 1643</domain> 1644 1645<domain varset="chip" name="CP_EVENT_WRITE" width="32"> 1646 <reg32 offset="0" name="0"> 1647 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1648 <!-- when set, write back timestamp instead of value from packet: --> 1649 <bitfield name="TIMESTAMP" pos="30" type="boolean"/> 1650 <bitfield name="IRQ" pos="31" type="boolean"/> 1651 </reg32> 1652 <!-- 1653 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1654 context switch? 1655 --> 1656 <reg64 offset="1" name="ADDR" type="waddress"/> 1657 <reg32 offset="3" name="3"> 1658 <!-- ??? --> 1659 </reg32> 1660</domain> 1661 1662<domain varset="chip" name="CP_EVENT_WRITE7" width="32"> 1663 <enum name="event_write_src"> 1664 <!-- Write payload[0] --> 1665 <value value="0" name="EV_WRITE_USER_32B"/> 1666 <!-- Write payload[0] payload[1] --> 1667 <value value="1" name="EV_WRITE_USER_64B"/> 1668 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) --> 1669 <value value="2" name="EV_WRITE_TIMESTAMP_SUM"/> 1670 <value value="3" name="EV_WRITE_ALWAYSON"/> 1671 <!-- Write payload[1] regs starting at payload[0] offset --> 1672 <value value="4" name="EV_WRITE_REGS_CONTENT"/> 1673 </enum> 1674 1675 <enum name="event_write_dst"> 1676 <value value="0" name="EV_DST_RAM"/> 1677 <value value="1" name="EV_DST_ONCHIP"/> 1678 </enum> 1679 1680 <reg32 offset="0" name="0"> 1681 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1682 <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/> 1683 <!-- Write sample count at (iova + 16) --> 1684 <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/> 1685 <!-- *(iova + 8) += *(iova + 16) - *iova --> 1686 <bitfield name="WRITE_ACCUM_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> 1687 1688 <!-- Next 4 flags are valid to set only when concurrent binning is enabled --> 1689 <!-- Increment 16b BV counter. Valid only in BV pipe --> 1690 <bitfield name="INC_BV_COUNT" pos="16" type="boolean"/> 1691 <!-- Increment 16b BR counter. Valid only in BR pipe --> 1692 <bitfield name="INC_BR_COUNT" pos="17" type="boolean"/> 1693 <bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/> 1694 <bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/> 1695 1696 <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/> 1697 <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/> 1698 <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. --> 1699 <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/> 1700 <bitfield name="IRQ" pos="31" type="boolean"/> 1701 </reg32> 1702 1703 <stripe varset="event_write_dst" variants="EV_DST_RAM"> 1704 <reg64 offset="1" name="1" type="waddress"/> 1705 <reg32 offset="3" name="3"> 1706 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1707 </reg32> 1708 <reg32 offset="4" name="4"> 1709 <bitfield name="PAYLOAD_1" low="0" high="31"/> 1710 </reg32> 1711 </stripe> 1712 1713 <stripe varset="event_write_dst" variants="EV_DST_ONCHIP"> 1714 <reg32 offset="1" name="1"> 1715 <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/> 1716 </reg32> 1717 <reg32 offset="3" name="3"> 1718 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1719 </reg32> 1720 <reg32 offset="4" name="4"> 1721 <bitfield name="PAYLOAD_1" low="0" high="31"/> 1722 </reg32> 1723 </stripe> 1724</domain> 1725 1726<domain name="CP_BLIT" width="32"> 1727 <enum name="cp_blit_cmd"> 1728 <value value="0" name="BLIT_OP_FILL"/> 1729 <value value="1" name="BLIT_OP_COPY"/> 1730 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation --> 1731 </enum> 1732 <reg32 offset="0" name="0"> 1733 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/> 1734 </reg32> 1735 <reg32 offset="1" name="1"> 1736 <bitfield name="SRC_X1" low="0" high="13" type="uint"/> 1737 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/> 1738 </reg32> 1739 <reg32 offset="2" name="2"> 1740 <bitfield name="SRC_X2" low="0" high="13" type="uint"/> 1741 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/> 1742 </reg32> 1743 <reg32 offset="3" name="3"> 1744 <bitfield name="DST_X1" low="0" high="13" type="uint"/> 1745 <bitfield name="DST_Y1" low="16" high="29" type="uint"/> 1746 </reg32> 1747 <reg32 offset="4" name="4"> 1748 <bitfield name="DST_X2" low="0" high="13" type="uint"/> 1749 <bitfield name="DST_Y2" low="16" high="29" type="uint"/> 1750 </reg32> 1751</domain> 1752 1753<domain name="CP_EXEC_CS" width="32"> 1754 <reg32 offset="0" name="0"> 1755 </reg32> 1756 <reg32 offset="1" name="1"> 1757 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/> 1758 </reg32> 1759 <reg32 offset="2" name="2"> 1760 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/> 1761 </reg32> 1762 <reg32 offset="3" name="3"> 1763 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/> 1764 </reg32> 1765</domain> 1766 1767<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 1768 <reg32 offset="0" name="0"> 1769 </reg32> 1770 <stripe varset="chip" variants="A4XX"> 1771 <reg32 offset="1" name="ADDR" type="address"/> 1772 <reg32 offset="2" name="2"> 1773 <!-- localsize is value minus one: --> 1774 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1775 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1776 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1777 </reg32> 1778 </stripe> 1779 <stripe varset="chip" variants="A5XX-"> 1780 <reg64 offset="1" name="ADDR" type="address"/> 1781 <reg32 offset="3" name="3"> 1782 <!-- localsize is value minus one: --> 1783 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1784 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1785 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1786 </reg32> 1787 </stripe> 1788</domain> 1789 1790<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1791 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> 1792 <enum name="set_marker_mode"> 1793 <value value="0" name="SET_RENDER_MODE"/> 1794 <!-- IFPC - inter-frame power collapse --> 1795 <value value="1" name="SET_IFPC_MODE"/> 1796 </enum> 1797 <enum name="a6xx_ifpc_mode"> 1798 <value value="0" name="IFPC_ENABLE"/> 1799 <value value="1" name="IFPC_DISABLE"/> 1800 </enum> 1801 <enum name="a6xx_marker"> 1802 <value value="1" name="RM6_DIRECT_RENDER"/> 1803 <value value="2" name="RM6_BIN_VISIBILITY"/> 1804 <value value="3" name="RM6_BIN_DIRECT"/> 1805 <value value="4" name="RM6_BIN_RENDER_START"/> 1806 <value value="5" name="RM6_BIN_END_OF_DRAWS"/> 1807 <value value="6" name="RM6_BIN_RESOLVE"/> 1808 <value value="7" name="RM6_BIN_RENDER_END"/> 1809 <value value="8" name="RM6_COMPUTE"/> 1810 <value value="12" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1811 1812 <!-- 1813 These values come from a6xx_set_marker() in the 1814 downstream kernel, and they can only be set by the kernel 1815 --> 1816 <value value="13" name="RM6_IB1LIST_START"/> 1817 <value value="14" name="RM6_IB1LIST_END"/> 1818 <value value="15" name="RM7_BIN_VISIBILITY_END"/> 1819 1820 <!-- new in a8xx: --> 1821 <value value="32" name="RM8_DEPTH_PASS_START"/> 1822 <value value="33" name="RM8_DEPTH_PASS_END"/> 1823 <value value="34" name="RM8_SET_RENDER_TARGET"/> 1824 <value value="35" name="RM8_PGMEM_ON"/> 1825 <value value="36" name="RM8_PGMEM_OFF"/> 1826 </enum> 1827 <stripe varset="chip" variants="A6XX-A7XX"> 1828 <reg32 offset="0" name="0"> 1829 <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1830 <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1831 1832 1833 <bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1834 <!-- used by preemption to determine if GMEM needs to be saved or not --> 1835 <bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1836 1837 1838 <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1839 1840 1841 <!-- 1842 CP_SET_MARKER is used with these bits to create a 1843 critical section around a workaround for ray tracing. 1844 The workaround happens after BVH building, and appears 1845 to invalidate the RTU's BVH node cache. It makes sure 1846 that only one of BR/BV/LPAC is executing the 1847 workaround at a time, and no draws using RT on BV/LPAC 1848 are executing while the workaround is executed on BR (or 1849 vice versa, that no draws on BV/BR using RT are executed 1850 while the workaround executes on LPAC), by 1851 hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. 1852 The blob usage is: 1853 1854 1855 CP_SET_MARKER(RT_WA_START) 1856 ... workaround here ... 1857 CP_SET_MARKER(RT_WA_END) 1858 ... 1859 CP_SET_MARKER(SHADER_USES_RT) 1860 CP_DRAW_INDX(...) or CP_EXEC_CS(...) 1861 --> 1862 <bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/> 1863 <bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/> 1864 <bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/> 1865 </reg32> 1866 </stripe> 1867 <stripe varset="chip" variants="A8XX-"> 1868 <reg32 offset="0" name="0"> 1869 <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1870 <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1871 <bitfield name="MODE" low="0" high="6" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1872 <bitfield name="USES_GMEM" pos="7" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1873 <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1874 <!-- idk if the RT w/a fields apply to a8xx as well --> 1875 </reg32> 1876 </stripe> 1877</domain> 1878 1879<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1880 <doc>Set internal CP registers, used to indicate context save data addresses</doc> 1881 <enum name="pseudo_reg"> 1882 <value value="0" name="SMMU_INFO"/> 1883 <value value="1" name="NON_SECURE_SAVE_ADDR"/> 1884 <value value="2" name="SECURE_SAVE_ADDR"/> 1885 <value value="3" name="NON_PRIV_SAVE_ADDR"/> 1886 <value value="4" name="COUNTER"/> 1887 1888 <!-- 1889 On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them, 1890 but that doesn't work with concurrent binning because BR will be reading from 1891 a different set of streams than BV is writing, so on a7xx we have these 1892 pseudo-regs instead, which do the right thing. 1893 1894 The corresponding VSC registers exist, and they're written by BV when it 1895 encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG 1896 it will only write some private scratch registers which are read by 1897 CP_SET_BIN_DATA5_OFFSET. 1898 1899 If concurrent binning is disabled then BR also does binning so it will also 1900 write the "real" registers in BR. 1901 --> 1902 <value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/> 1903 <value value="9" name="VSC_SIZE_BASE"/> 1904 <value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/> 1905 <value value="11" name="UNK_STRM_ADDRESS"/> 1906 <value value="12" name="UNK_STRM_SIZE_ADDRESS"/> 1907 1908 <value value="16" name="BINDLESS_BASE_0_ADDR"/> 1909 <value value="17" name="BINDLESS_BASE_1_ADDR"/> 1910 <value value="18" name="BINDLESS_BASE_2_ADDR"/> 1911 <value value="19" name="BINDLESS_BASE_3_ADDR"/> 1912 <value value="20" name="BINDLESS_BASE_4_ADDR"/> 1913 <value value="21" name="BINDLESS_BASE_5_ADDR"/> 1914 <value value="22" name="BINDLESS_BASE_6_ADDR"/> 1915 </enum> 1916 <array offset="0" stride="3" length="100"> 1917 <reg32 offset="0" name="0"> 1918 <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/> 1919 </reg32> 1920 <reg32 offset="1" name="1"> 1921 <bitfield name="LO" low="0" high="31"/> 1922 </reg32> 1923 <reg32 offset="2" name="2"> 1924 <bitfield name="HI" low="0" high="31"/> 1925 </reg32> 1926 </array> 1927</domain> 1928 1929<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1930 <doc> 1931 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. 1932 So: 1933 1934 opcode: CP_REG_TEST (39) (2 dwords) 1935 { REG = 0xc10 | BIT = 0 } 1936 0000: 70b90001 00000c10 1937 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1938 0000: 70c70002 10000000 00000004 1939 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) 1940 1941 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at 1942 offset 0x0c10 is 1 1943 </doc> 1944 <enum name="source_type"> 1945 <value value="0" name="SOURCE_REG"/> 1946 <!-- Don't confuse with scratch registers, this is a separate memory 1947 written into by CP_MEM_TO_SCRATCH_MEM. --> 1948 <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/> 1949 </enum> 1950 <reg32 offset="0" name="0"> 1951 <!-- the register to test --> 1952 <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/> 1953 <bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/> 1954 <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/> 1955 <!-- the bit to test --> 1956 <bitfield name="BIT" low="20" high="24" type="uint"/> 1957 <!-- skip implied CP_WAIT_FOR_ME --> 1958 <bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/> 1959 <!-- the predicate bit to set (new in gen3+) --> 1960 <bitfield name="PRED_BIT" low="26" high="30" type="uint"/> 1961 <!-- update the predicate reg directly (new in gen3+) --> 1962 <bitfield name="PRED_UPDATE" pos="31" type="boolean"/> 1963 </reg32> 1964 1965 <!-- 1966 In PRED_UPDATE mode, the predicate reg is updated directly using two 1967 more dwords, ignoring other bits: 1968 1969 PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK); 1970 --> 1971 <reg32 offset="1" name="PRED_MASK" type="hex"/> 1972 <reg32 offset="2" name="PRED_VAL" type="hex"/> 1973</domain> 1974 1975<!-- I *think* this existed at least as far back as a4xx --> 1976<domain name="CP_COND_REG_EXEC" width="32"> 1977 <enum name="compare_mode"> 1978 <!-- use the predicate bit set by CP_REG_TEST --> 1979 <value value="1" name="PRED_TEST"/> 1980 <!-- compare two registers directly for equality --> 1981 <value value="2" name="REG_COMPARE"/> 1982 <!-- test if certain render modes are set via CP_SET_MARKER --> 1983 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/> 1984 <!-- compare REG0 for equality with immediate --> 1985 <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/> 1986 <!-- test which of BR/BV are enabled --> 1987 <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/> 1988 </enum> 1989 <reg32 offset="0" name="0" varset="compare_mode"> 1990 <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/> 1991 1992 <!-- the predicate bit to test (new in gen3+) --> 1993 <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/> 1994 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/> 1995 <!-- With REG_COMPARE instead of register read from ONCHIP memory --> 1996 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/> 1997 1998 <!-- 1999 Note: these bits have the same meaning, and use the same 2000 internal mechanism as the bits in CP_SET_DRAW_STATE. 2001 When RENDER_MODE is selected, they're used as 2002 a bitmask of which modes pass the test. 2003 --> 2004 2005 <!-- RM6_BIN_VISIBILITY --> 2006 <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/> 2007 <!-- all others --> 2008 <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/> 2009 <!-- RM6_DIRECT_RENDER --> 2010 <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/> 2011 2012 <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/> 2013 <bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/> 2014 <bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/> 2015 2016 <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/> 2017 </reg32> 2018 2019 <stripe varset="compare_mode" variants="PRED_TEST"> 2020 <reg32 offset="1" name="1"> 2021 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2022 </reg32> 2023 </stripe> 2024 2025 <stripe varset="compare_mode" variants="REG_COMPARE"> 2026 <reg32 offset="1" name="1"> 2027 <bitfield name="REG1" low="0" high="17" type="hex"/> 2028 <!-- Instead of register read from ONCHIP memory --> 2029 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/> 2030 </reg32> 2031 </stripe> 2032 2033 <stripe varset="compare_mode" variants="RENDER_MODE"> 2034 <reg32 offset="1" name="1"> 2035 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2036 </reg32> 2037 </stripe> 2038 2039 <stripe varset="compare_mode" variants="REG_COMPARE_IMM"> 2040 <reg32 offset="1" name="1"> 2041 <bitfield name="IMM" low="0" high="31"/> 2042 </reg32> 2043 </stripe> 2044 2045 <stripe varset="compare_mode" variants="THREAD_MODE"> 2046 <reg32 offset="1" name="1"> 2047 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2048 </reg32> 2049 </stripe> 2050 2051 <reg32 offset="2" name="2"> 2052 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2053 </reg32> 2054</domain> 2055 2056<domain name="CP_COND_EXEC" width="32"> 2057 <doc> 2058 Executes the following DWORDs of commands if the dword at ADDR0 2059 is not equal to 0 and the dword at ADDR1 is less than REF 2060 (signed comparison). 2061 </doc> 2062 <reg32 offset="0" name="0"> 2063 <bitfield name="ADDR0_LO" low="0" high="31"/> 2064 </reg32> 2065 <reg32 offset="1" name="1"> 2066 <bitfield name="ADDR0_HI" low="0" high="31"/> 2067 </reg32> 2068 <reg32 offset="2" name="2"> 2069 <bitfield name="ADDR1_LO" low="0" high="31"/> 2070 </reg32> 2071 <reg32 offset="3" name="3"> 2072 <bitfield name="ADDR1_HI" low="0" high="31"/> 2073 </reg32> 2074 <reg32 offset="4" name="4"> 2075 <bitfield name="REF" low="0" high="31"/> 2076 </reg32> 2077 <reg32 offset="5" name="5"> 2078 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 2079 </reg32> 2080</domain> 2081 2082<domain name="CP_SET_AMBLE" width="32"> 2083 <doc> 2084 Used by the userspace and kernel drivers to set various IB's 2085 which are executed during context save/restore for handling 2086 state that isn't restored by the context switch routine itself. 2087 </doc> 2088 <enum name="amble_type"> 2089 <value name="PREAMBLE_AMBLE_TYPE" value="0"> 2090 <doc>Executed unconditionally when switching back to the context.</doc> 2091 </value> 2092 <value name="BIN_PREAMBLE_AMBLE_TYPE" value="1"> 2093 <doc> 2094 Executed when switching back after switching 2095 away during execution of 2096 a CP_SET_MARKER packet with RM6_BIN_RENDER_END as the 2097 payload *and* skipsaverestore is set. This is 2098 expected to restore static register values not 2099 saved when skipsaverestore is set. 2100 2101 On BV, a skipsaverestore preemption is triggered 2102 and this preamble type is executed whenever a 2103 CP_THREAD_CONTROL that synchronizes threads 2104 happens. This can be explicitly via 2105 SYNC_THREADS, or implicitly when the value of 2106 CONCURRENT_BIN_DISABLE changes from the previous 2107 thread control. 2108 </doc> 2109 </value> 2110 <value name="POSTAMBLE_AMBLE_TYPE" value="2"> 2111 <doc> 2112 Executed when switching away from the context, 2113 except for context switches initiated via 2114 CP_YIELD. 2115 </doc> 2116 </value> 2117 <value name="KMD_AMBLE_TYPE" value="3"> 2118 <doc> 2119 This can only be set by the RB (i.e. the kernel) 2120 and executes with protected mode off, but 2121 is otherwise similar to POSTAMBLE_AMBLE_TYPE. 2122 </doc> 2123 </value> 2124 </enum> 2125 <reg64 offset="0" name="ADDR" type="address"/> 2126 <reg32 offset="2" name="2"> 2127 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 2128 <bitfield name="TYPE" low="20" high="21" type="amble_type"/> 2129 </reg32> 2130</domain> 2131 2132<domain name="CP_REG_WRITE" width="32"> 2133 <enum name="reg_tracker"> 2134 <doc> 2135 Keep shadow copies of these registers and only set them 2136 when drawing, avoiding redundant writes: 2137 - VPC_CNTL_0 2138 - HLSQ_CONTROL_1_REG 2139 - HLSQ_UNKNOWN_B980 2140 </doc> 2141 <value name="TRACK_CNTL_REG" value="0x1"/> 2142 <doc> 2143 Track RB_RENDER_CNTL, and insert a WFI in the following 2144 situation: 2145 - There is a write that disables binning 2146 - There was a draw with binning left enabled, but in 2147 BYPASS mode 2148 Presumably this is a hang workaround? 2149 </doc> 2150 <value name="TRACK_RENDER_CNTL" value="0x2"/> 2151 <doc> 2152 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of 2153 the data to write is 0. Used by the Vulkan blob with 2154 PC_MULTIVIEW_CNTL, but this isn't predicated on particular 2155 register(s) like the others. 2156 </doc> 2157 <value name="UNK_EVENT_WRITE" value="0x4"/> 2158 <doc> 2159 Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and 2160 GRAS_LRZ_VIEW_INFO with previous values, and if one of 2161 the following is true: 2162 - GRAS_LRZ_CNTL::GREATER has changed 2163 - GRAS_LRZ_CNTL::DIR has changed, the old value is not 2164 CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED 2165 - GRAS_LRZ_VIEW_INFO has changed 2166 then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE 2167 forced to 1. 2168 Only exists in a650_sqe.fw. 2169 </doc> 2170 <value name="TRACK_LRZ" value="0x8"/> 2171 </enum> 2172 <reg32 offset="0" name="0"> 2173 <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/> 2174 </reg32> 2175 <reg32 offset="1" name="1"/> 2176 <reg32 offset="2" name="2"/> 2177</domain> 2178 2179<domain name="CP_SMMU_TABLE_UPDATE" width="32"> 2180 <doc> 2181 Note that the SMMU's definition of TTBRn can take different forms 2182 depending on the pgtable format. But a5xx+ only uses aarch64 2183 format. 2184 </doc> 2185 <reg32 offset="0" name="0"> 2186 <bitfield name="TTBR0_LO" low="0" high="31"/> 2187 </reg32> 2188 <reg32 offset="1" name="1"> 2189 <bitfield name="TTBR0_HI" low="0" high="15"/> 2190 <bitfield name="ASID" low="16" high="31"/> 2191 </reg32> 2192 <reg32 offset="2" name="2"> 2193 <doc>Unused, does not apply to aarch64 pgtable format</doc> 2194 <bitfield name="CONTEXTIDR" low="0" high="31"/> 2195 </reg32> 2196 <reg32 offset="3" name="3"> 2197 <bitfield name="CONTEXTBANK" low="0" high="31"/> 2198 </reg32> 2199</domain> 2200 2201<domain name="CP_START_BIN" width="32"> 2202 <reg32 offset="0" name="BIN_COUNT" type="uint"/> 2203 <reg64 offset="1" name="PREFIX_ADDR" type="address"/> 2204 <reg32 offset="3" name="PREFIX_DWORDS"> 2205 <doc> 2206 Size of prefix for each bin. For each bin index i, the 2207 prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are 2208 executed in an IB2 before the IB1 commands following 2209 this packet. 2210 </doc> 2211 </reg32> 2212 <reg32 offset="4" name="BODY_DWORDS"> 2213 <doc>Number of dwords after this packet until CP_END_BIN</doc> 2214 </reg32> 2215</domain> 2216 2217<domain name="CP_WAIT_TIMESTAMP" width="32"> 2218 <enum name="ts_wait_value_src"> 2219 <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) --> 2220 <value value="0" name="TS_WAIT_GE_32B"/> 2221 <!-- Wait for value at memory address to be >= SRC_0 (unsigned) --> 2222 <value value="1" name="TS_WAIT_GE_64B"/> 2223 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) --> 2224 <value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/> 2225 </enum> 2226 2227 <enum name="ts_wait_type"> 2228 <value value="0" name="TS_WAIT_RAM"/> 2229 <value value="1" name="TS_WAIT_ONCHIP"/> 2230 </enum> 2231 2232 <reg32 offset="0" name="0"> 2233 <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/> 2234 <bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/> 2235 </reg32> 2236 2237 <stripe varset="ts_wait_type" variants="TS_WAIT_RAM"> 2238 <reg64 offset="1" name="ADDR" type="address"/> 2239 </stripe> 2240 2241 <stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP"> 2242 <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/> 2243 </stripe> 2244 2245 <reg32 offset="3" name="SRC_0"/> 2246 <reg32 offset="4" name="SRC_1"/> 2247</domain> 2248 2249<domain name="CP_BV_BR_COUNT_OPS" width="32"> 2250 <enum name="pipe_count_op"> 2251 <value name="PIPE_CLEAR_BV_BR" value="0x1"/> 2252 <value name="PIPE_SET_BR_OFFSET" value="0x2"/> 2253 <!-- Wait until for BV_counter > BR_counter --> 2254 <value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/> 2255 <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter --> 2256 <value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/> 2257 </enum> 2258 <reg32 offset="0" name="0"> 2259 <bitfield name="OP" low="0" high="3" type="pipe_count_op"/> 2260 </reg32> 2261 <reg32 offset="1" name="1"> 2262 <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/> 2263 </reg32> 2264</domain> 2265 2266<domain name="CP_MODIFY_TIMESTAMP" width="32"> 2267 <enum name="timestamp_op"> 2268 <value name="MODIFY_TIMESTAMP_CLEAR" value="0"/> 2269 <value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/> 2270 <value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/> 2271 </enum> 2272 <reg32 offset="0" name="0"> 2273 <bitfield name="ADD" low="0" high="7" type="uint"/> 2274 <bitfield name="OP" low="28" high="31" type="timestamp_op"/> 2275 </reg32> 2276</domain> 2277 2278<domain name="CP_MEM_TO_SCRATCH_MEM" width="32"> 2279 <doc> 2280 Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers 2281 and keep them in a local scratch memory instead of fetching every time 2282 when skipping IBs. 2283 </doc> 2284 <reg32 offset="0" name="0"> 2285 <bitfield name="CNT" low="0" high="5" type="uint"/> 2286 </reg32> 2287 <reg32 offset="1" name="1"> 2288 <doc>Scratch memory size is 48 dwords`</doc> 2289 <bitfield name="OFFSET" low="0" high="5" type="uint"/> 2290 </reg32> 2291 <reg32 offset="2" name="2"> 2292 <bitfield name="SRC" low="0" high="31"/> 2293 </reg32> 2294 <reg32 offset="3" name="3"> 2295 <bitfield name="SRC_HI" low="0" high="31"/> 2296 </reg32> 2297</domain> 2298 2299<domain name="CP_THREAD_CONTROL" width="32"> 2300 <enum name="cp_thread"> 2301 <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render --> 2302 <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility --> 2303 <value name="CP_SET_THREAD_BOTH" value="3"/> 2304 </enum> 2305 <reg32 offset="0" name="0"> 2306 <bitfield low="0" high="1" name="THREAD" type="cp_thread"/> 2307 <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/> 2308 <bitfield pos="31" name="SYNC_THREADS" type="boolean"/> 2309 </reg32> 2310</domain> 2311 2312<domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32"> 2313 <reg64 offset="0" name="IB_BASE"/> 2314 <reg32 offset="2" name="2"> 2315 <!-- STRIDE * COUNT --> 2316 <bitfield name="IB_SIZE" low="0" high="11"/> 2317 <bitfield name="STRIDE" low="20" high="31"/> 2318 </reg32> 2319 <reg32 offset="3" name="3"> 2320 <bitfield name="COUNT" low="0" high="31"/> 2321 </reg32> 2322</domain> 2323 2324<domain name="CP_RESET_CONTEXT_STATE" width="32"> 2325 <reg32 offset="0" name="0"> 2326 <bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/> 2327 <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/> 2328 <bitfield name="CLEAR_BV_BR_COUNTER" pos="2" type="boolean"/> 2329 <bitfield name="RESET_GLOBAL_LOCAL_TS" pos="3" type="boolean"/> 2330 </reg32> 2331</domain> 2332 2333<domain name="CP_SCOPE_CNTL" width="32"> 2334 <enum name="cp_scope"> 2335 <value value="0" name="INTERRUPTS"/> 2336 </enum> 2337 <reg32 offset="0" name="0"> 2338 <bitfield name="DISABLE_PREEMPTION" pos="0" type="boolean"/> 2339 <bitfield low="28" high="31" name="SCOPE" type="cp_scope"/> 2340 </reg32> 2341</domain> 2342 2343<domain name="CP_INDIRECT_BUFFER" width="32" varset="chip" prefix="chip" variants="A5XX-"> 2344 <reg64 offset="0" name="IB_BASE" type="address"/> 2345 <reg32 offset="2" name="2"> 2346 <bitfield name="IB_SIZE" low="0" high="19"/> 2347 </reg32> 2348</domain> 2349 2350<domain name="CP_RESOURCE_LIST" width="32"> 2351 <doc> 2352 A7xx introduces the "resource table" which is managed by 2353 CP_RESOURCE_LIST. It is used to synchronize BR and BV access 2354 to resources such as LRZ buffers. 2355 2356 The resource table consists of resources that are in-use by BR. 2357 Each "resource" has a base address, which is 2358 usually a pointer but is treated by the HW as an opaque handle, 2359 a read/write bit, and a timestamp when it was last used. 2360 Resources are removed from the table upon event completion when 2361 a special CP_EVENT_WRITE::CLEAR_RENDER_RESOURCE bit is set, which 2362 will remove all resources with a timestamp up to the current 2363 timestamp. 2364 2365 CP_RESOURCE_LIST first specifies a list of BV resources. For 2366 each BV resource, the HW will check if there is a corresponding 2367 BR resource in the table, and if at least one of the BV and BR 2368 resources is marked WRITE then it will stall until the BR 2369 resource is removed. 2370 2371 It then specifies a list of BR resources. These will be added to 2372 the resource table, unless there is an overflow in which case 2373 the designated overflow register will have bit 0 set. Overflow 2374 should cause the next binning pass to stall until BR is done, 2375 effectively disabling concurrent binning. 2376 2377 CP_RESOURCE_LIST must be executed by BV. BR resources are added 2378 by BV and removed by BR. 2379 2380 There is a separate table for "LRZ resources." These behave a 2381 bit differently: specifying an LRZ resource via BV_RES_LRZ 2382 stalls on any matching resource existing and then adds it to the 2383 table, making it both a BV and BR resource in one. There is a 2384 separate CLEAR_LRZ_RESOURCE bit for removing resources from the 2385 LRZ table, and it only removes one resource given by a base 2386 address passed to CP_EVENT_WRITE. Therefore timestamps are 2387 unnecessary. 2388 </doc> 2389 <reg32 offset="0" name="BV_COUNT" type="uint"/> 2390 <doc> 2391 What follows is a list of CP_BV_RESOURCE and then CP_RESOURCE_LIST_BR. 2392 </doc> 2393</domain> 2394 2395<domain name="CP_BV_RESOURCE" width="32"> 2396 <doc> 2397 BV resources don't go in the table. Instead CP waits until any 2398 corresponding BR resources with the same base pointer are 2399 finished before the packet completes. 2400 </doc> 2401 <enum name="cp_bv_resource_encoding"> 2402 <value value="0" name="BV_RES_DIRECT"/> 2403 <doc> 2404 INDIRECT resources are encoded as a 32b offset + 3b 2405 bindless base selector. The offset is added to the given 2406 BINDLESS_BASE pseudoregister and then the 64b value 2407 fetched there is used as the pointer. 2408 </doc> 2409 <value value="1" name="BV_RES_INDIRECT_READ"/> 2410 <value value="2" name="BV_RES_LRZ"/> 2411 <value value="3" name="BV_RES_INDIRECT_WRITE"/> 2412 </enum> 2413 <reg64 offset="0" name="0"> 2414 <bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/> 2415 <bitfield name="WRITE" pos="0" type="boolean"/> 2416 <bitfield name="ENCODING" low="62" high="63" type="cp_bv_resource_encoding"/> 2417 </reg64> 2418</domain> 2419 2420<domain name="CP_RESOURCE_LIST_BR" width="32"> 2421 <reg32 offset="0" name="0"> 2422 <bitfield name="BR_COUNT" low="0" high="23" type="uint"/> 2423 <bitfield name="OVERFLOW_ONCHIP_ADDR" low="24" high="26"/> 2424 <bitfield name="OVERFLOW" pos="31" type="boolean"/> 2425 </reg32> 2426 <doc> 2427 What follows is a list of CP_BR_RESOURCE. 2428 </doc> 2429</domain> 2430 2431<domain name="CP_BR_RESOURCE" width="32"> 2432 <enum name="cp_br_resource_encoding"> 2433 <value value="0" name="BR_RES_DIRECT"/> 2434 <value value="2" name="BR_RES_INDIRECT_READ"/> 2435 <value value="3" name="BR_RES_INDIRECT_WRITE"/> <!-- set WRITE bit --> 2436 </enum> 2437 <reg64 offset="0" name="0"> 2438 <bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/> 2439 <bitfield name="WRITE" pos="0" type="boolean"/> 2440 <bitfield name="ENCODING" low="62" high="63" type="cp_br_resource_encoding"/> 2441 </reg64> 2442</domain> 2443 2444</database> 2445
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