FILE
a6xx_gmu.xml
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linux-6.19.14/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7 8<domain name="A6XX" width="32" prefix="variant" varset="chip"> 9 10 <bitset name="A6XX_GMU_GPU_IDLE_STATUS"> 11 <bitfield name="BUSY_IGN_AHB" pos="23"/> 12 <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/> 13 </bitset> 14 15 <bitset name="A6XX_GMU_OOB"> 16 <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/> 17 <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/> 18 <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/> 19 <bitfield name="DCVS_SET_MASK" pos="23"/> 20 <bitfield name="DCVS_CHECK_MASK" pos="31"/> 21 <bitfield name="DCVS_CLEAR_MASK" pos="31"/> 22 <bitfield name="GPU_SET_MASK" pos="18"/> 23 <bitfield name="GPU_CHECK_MASK" pos="26"/> 24 <bitfield name="GPU_CLEAR_MASK" pos="26"/> 25 <bitfield name="PERFCNTR_SET_MASK" pos="17"/> 26 <bitfield name="PERFCNTR_CHECK_MASK" pos="25"/> 27 <bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/> 28 </bitset> 29 30 <bitset name="A6XX_HFI_IRQ"> 31 <bitfield name="MSGQ_MASK" pos="0" /> 32 <bitfield name="DSGQ_MASK" pos="1"/> 33 <bitfield name="BLOCKED_MSG_MASK" pos="2"/> 34 <bitfield name="CM3_FAULT_MASK" pos="23"/> 35 <bitfield name="GMU_ERR_MASK" low="16" high="22"/> 36 <bitfield name="OOB_MASK" low="24" high="31"/> 37 </bitset> 38 39 <bitset name="A6XX_HFI_H2F"> 40 <bitfield name="IRQ_MASK_BIT" pos="0" /> 41 </bitset> 42 43 <reg32 offset="0x1a880" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/> 44 <reg32 offset="0x1a881" name="GMU_GX_SPTPRAC_POWER_CONTROL"/> 45 <reg32 offset="0x1b400" name="GMU_CM3_ITCM_START"/> 46 <reg32 offset="0x1c400" name="GMU_CM3_DTCM_START"/> 47 <reg32 offset="0x1cbf0" name="GMU_NMI_CONTROL_STATUS"/> 48 <reg32 offset="0x1cbf8" name="GMU_BOOT_SLUMBER_OPTION"/> 49 <reg32 offset="0x1cbf9" name="GMU_GX_VOTE_IDX"/> 50 <reg32 offset="0x1cbfa" name="GMU_MX_VOTE_IDX"/> 51 <reg32 offset="0x1cbfc" name="GMU_DCVS_ACK_OPTION"/> 52 <reg32 offset="0x1cbfd" name="GMU_DCVS_PERF_SETTING"/> 53 <reg32 offset="0x1cbfe" name="GMU_DCVS_BW_SETTING"/> 54 <reg32 offset="0x1cbff" name="GMU_DCVS_RETURN"/> 55 <reg32 offset="0x1d3f8" name="GMU_CORE_FW_VERSION"> 56 <bitfield name="MAJOR" low="28" high="31"/> 57 <bitfield name="MINOR" low="16" high="27"/> 58 <bitfield name="STEP" low="0" high="15"/> 59 </reg32> 60 <reg32 offset="0x1f400" name="GMU_ICACHE_CONFIG"/> 61 <reg32 offset="0x1f401" name="GMU_DCACHE_CONFIG"/> 62 <reg32 offset="0x1f40f" name="GMU_SYS_BUS_CONFIG"/> 63 <reg32 offset="0x1f50b" name="GMU_MRC_GBIF_QOS_CTRL"/> 64 <reg32 offset="0x1f800" name="GMU_CM3_SYSRESET"/> 65 <reg32 offset="0x1f801" name="GMU_CM3_BOOT_CONFIG"/> 66 <reg32 offset="0x1f81a" name="GMU_CM3_FW_BUSY"/> 67 <reg32 offset="0x1f81c" name="GMU_CM3_FW_INIT_RESULT"/> 68 <reg32 offset="0x1f82d" name="GMU_CM3_CFG"/> 69 <reg32 offset="0x1f840" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/> 70 <reg32 offset="0x1fc10" name="GMU_CX_GMU_POWER_COUNTER_ENABLE" variants="A8XX"/> 71 <reg32 offset="0x1f841" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/> 72 <reg32 offset="0x1f842" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/> 73 <reg32 offset="0x1fc40" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0" variants="A8XX-"/> 74 <reg32 offset="0x1fc41" name="GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1" variants="A8XX-"/> 75 <reg32 offset="0x1f844" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/> 76 <reg32 offset="0x1fca0" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L" variants="A8XX-"/> 77 <reg32 offset="0x1f845" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/> 78 <reg32 offset="0x1fca1" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H" variants="A8XX-"/> 79 <reg32 offset="0x1f846" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/> 80 <reg32 offset="0x1f847" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/> 81 <reg32 offset="0x1f848" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/> 82 <reg32 offset="0x1f849" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/> 83 <reg32 offset="0x1f84a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/> 84 <reg32 offset="0x1f84b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/> 85 <reg32 offset="0x1f84c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/> 86 <reg32 offset="0x1f84d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/> 87 <reg32 offset="0x1f84e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/> 88 <reg32 offset="0x1f84f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/> 89 <reg32 offset="0x1f8c0" name="GMU_PWR_COL_INTER_FRAME_CTRL"> 90 <bitfield name="IFPC_ENABLE" pos="0" type="boolean"/> 91 <bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/> 92 <bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/> 93 <bitfield name="NUM_PASS_SKIPS" low="10" high="13"/> 94 <bitfield name="MIN_PASS_LENGTH" low="14" high="31"/> 95 </reg32> 96 <reg32 offset="0x1f8c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/> 97 <reg32 offset="0x1f8c2" name="GMU_PWR_COL_SPTPRAC_HYST"/> 98 <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A6XX"> 99 <bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/> 100 <bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/> 101 <bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/> 102 <bitfield name="SPTPRAC_GDSC_POWER_ON" pos="3" type="boolean"/> 103 <bitfield name="SP_CLOCK_OFF" pos="4" type="boolean"/> 104 <bitfield name="GMU_UP_POWER_STATE" pos="5" type="boolean"/> 105 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/> 106 <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/> 107 </reg32> 108 <reg32 offset="0x1f8d0" name="GMU_SPTPRAC_PWR_CLK_STATUS" variants="A7XX"> 109 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/> 110 <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/> 111 </reg32> 112 <reg32 offset="0x1f7e8" name="GMU_PWR_CLK_STATUS" variants="A8XX-"> 113 <bitfield name="GX_HM_GDSC_POWER_OFF" pos="0" type="boolean"/> 114 <bitfield name="GX_HM_CLK_OFF" pos="1" type="boolean"/> 115 </reg32> 116 <reg32 offset="0x1f8e4" name="GMU_GPU_NAP_CTRL"> 117 <bitfield name="HW_NAP_ENABLE" pos="0"/> 118 <bitfield name="SID" low="4" high="8"/> 119 </reg32> 120 <reg32 offset="0x1f8e8" name="GMU_RPMH_CTRL"> 121 <bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/> 122 <bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/> 123 <bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/> 124 <bitfield name="MX_VOTE_ENABLE" pos="9" type="boolean"/> 125 <bitfield name="CX_VOTE_ENABLE" pos="10" type="boolean"/> 126 <bitfield name="GFX_VOTE_ENABLE" pos="11" type="boolean"/> 127 <bitfield name="DDR_MIN_VOTE_ENABLE" pos="12" type="boolean"/> 128 <bitfield name="MX_MIN_VOTE_ENABLE" pos="13" type="boolean"/> 129 <bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/> 130 <bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/> 131 </reg32> 132 <reg32 offset="0x1f8e9" name="GMU_RPMH_HYST_CTRL"/> 133 <reg32 offset="0x1f8ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A6XX"/> 134 <reg32 offset="0x1f7e9" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE" variants="A8XX-"/> 135 <reg32 offset="0x1f8f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A6XX"/> 136 <reg32 offset="0x1f7ec" name="GPU_GMU_CX_GMU_CX_FAL_INTF" variants="A8XX-"/> 137 <reg32 offset="0x1f8f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A6XX"/> 138 <reg32 offset="0x1f7ed" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF" variants="A8XX-"/> 139 <reg32 offset="0x1f900" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/> 140 <reg32 offset="0x1f901" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/> 141 <reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/> 142 <reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/> 143 <reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/> 144 <reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L"/> 145 <reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H"/> 146 <reg32 offset="0x1f8c3" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A6XX-A7XX"/> 147 <reg32 offset="0x1f7e4" name="GMU_GMU_PWR_COL_KEEPALIVE" variants="A8XX-"/> 148 <reg32 offset="0x1f8c4" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A6XX-A7XX"/> 149 <reg32 offset="0x1f7e5" name="GMU_PWR_COL_PREEMPT_KEEPALIVE" variants="A8XX-"/> 150 <reg32 offset="0x1f980" name="GMU_HFI_CTRL_STATUS"/> 151 <reg32 offset="0x1f981" name="GMU_HFI_VERSION_INFO"/> 152 <reg32 offset="0x1f982" name="GMU_HFI_SFR_ADDR"/> 153 <reg32 offset="0x1f983" name="GMU_HFI_MMAP_ADDR"/> 154 <reg32 offset="0x1f984" name="GMU_HFI_QTBL_INFO"/> 155 <reg32 offset="0x1f985" name="GMU_HFI_QTBL_ADDR"/> 156 <reg32 offset="0x1f986" name="GMU_HFI_CTRL_INIT"/> 157 <reg32 offset="0x1f990" name="GMU_GMU2HOST_INTR_SET"/> 158 <reg32 offset="0x1f991" name="GMU_GMU2HOST_INTR_CLR"/> 159 <reg32 offset="0x1f992" name="GMU_GMU2HOST_INTR_INFO"> 160 <bitfield name="MSGQ" pos="0" type="boolean"/> 161 <bitfield name="CM3_FAULT" pos="23" type="boolean"/> 162 </reg32> 163 <reg32 offset="0x1f993" name="GMU_GMU2HOST_INTR_MASK"/> 164 <reg32 offset="0x1f994" name="GMU_HOST2GMU_INTR_SET"/> 165 <reg32 offset="0x1f995" name="GMU_HOST2GMU_INTR_CLR"/> 166 <reg32 offset="0x1f996" name="GMU_HOST2GMU_INTR_RAW_INFO"/> 167 <reg32 offset="0x1f997" name="GMU_HOST2GMU_INTR_EN_0"/> 168 <reg32 offset="0x1f998" name="GMU_HOST2GMU_INTR_EN_1"/> 169 <reg32 offset="0x1f999" name="GMU_HOST2GMU_INTR_EN_2"/> 170 <reg32 offset="0x1f99a" name="GMU_HOST2GMU_INTR_EN_3"/> 171 <reg32 offset="0x1f99b" name="GMU_HOST2GMU_INTR_INFO_0"/> 172 <reg32 offset="0x1f99c" name="GMU_HOST2GMU_INTR_INFO_1"/> 173 <reg32 offset="0x1f99d" name="GMU_HOST2GMU_INTR_INFO_2"/> 174 <reg32 offset="0x1f99e" name="GMU_HOST2GMU_INTR_INFO_3"/> 175 <reg32 offset="0x1f9c5" name="GMU_GENERAL_0"/> 176 <reg32 offset="0x1f9c6" name="GMU_GENERAL_1"/> 177 <reg32 offset="0x1f9cb" name="GMU_GENERAL_6"/> 178 <reg32 offset="0x1f9cc" name="GMU_GENERAL_7"/> 179 <reg32 offset="0x1f9cd" name="GMU_GENERAL_8" variants="A7XX"/> 180 <reg32 offset="0x1f9ce" name="GMU_GENERAL_9" variants="A7XX"/> 181 <reg32 offset="0x1f9cf" name="GMU_GENERAL_10" variants="A7XX"/> 182 <reg32 offset="0x1f9c0" name="GMU_GENERAL_0" variants="A8XX"/> 183 <reg32 offset="0x1f9c1" name="GMU_GENERAL_1" variants="A8XX"/> 184 <reg32 offset="0x1f9c6" name="GMU_GENERAL_6" variants="A8XX"/> 185 <reg32 offset="0x1f9c7" name="GMU_GENERAL_7" variants="A8XX"/> 186 <reg32 offset="0x1f9c8" name="GMU_GENERAL_8" variants="A8XX"/> 187 <reg32 offset="0x1f9c9" name="GMU_GENERAL_9" variants="A8XX"/> 188 <reg32 offset="0x1f9ca" name="GMU_GENERAL_10" variants="A8XX"/> 189 <reg32 offset="0x1f9cb" name="GMU_GENERAL_11" variants="A8XX"/> 190 <reg32 offset="0x1f95d" name="GMU_ISENSE_CTRL"/> 191 <reg32 offset="0x23120" name="GPU_CS_ENABLE_REG"/> 192 <reg32 offset="0x1f95d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/> 193 <reg32 offset="0x22d78" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/> 194 <reg32 offset="0x22d58" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/> 195 <reg32 offset="0x22d80" name="GPU_CS_A_SENSOR_CTRL_0"/> 196 <reg32 offset="0x422da" name="GPU_CS_A_SENSOR_CTRL_2"/> 197 <reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/> 198 <reg32 offset="0x23157" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/> 199 <reg32 offset="0x2301a" name="GPU_CS_SENSOR_GENERAL_STATUS"/> 200 <reg32 offset="0x2301d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/> 201 <reg32 offset="0x2301f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/> 202 <reg32 offset="0x23021" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/> 203 <reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/> 204 <reg32 offset="0x2316d" name="GPU_CS_AMP_PERIOD_CTRL"/> 205 <reg32 offset="0x23165" name="GPU_CS_AMP_CALIBRATION_DONE"/> 206 <reg32 offset="0x1f94d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/> 207 <reg32 offset="0x23b03" name="GMU_AO_INTERRUPT_EN"/> 208 <reg32 offset="0x23b04" name="GMU_AO_HOST_INTERRUPT_CLR"/> 209 <reg32 offset="0x23b05" name="GMU_AO_HOST_INTERRUPT_STATUS"> 210 <bitfield name="WDOG_BITE" pos="0" type="boolean"/> 211 <bitfield name="RSCC_COMP" pos="1" type="boolean"/> 212 <bitfield name="VDROOP" pos="2" type="boolean"/> 213 <bitfield name="FENCE_ERR" pos="3" type="boolean"/> 214 <bitfield name="DBD_WAKEUP" pos="4" type="boolean"/> 215 <bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/> 216 </reg32> 217 <reg32 offset="0x23b06" name="GMU_AO_HOST_INTERRUPT_MASK"/> 218 <reg32 offset="0x23b09" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/> 219 <reg32 offset="0x23b0a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/> 220 <reg32 offset="0x23b0b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/> 221 <reg32 offset="0x23b0c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS"> 222 <bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/> 223 </reg32> 224 <reg32 offset="0x23b0d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/> 225 <reg32 offset="0x23b0e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/> 226 <reg32 offset="0x23b10" name="GMU_AO_AHB_FENCE_CTRL"/> 227 <reg32 offset="0x23b13" name="GMU_AHB_FENCE_STATUS"/> 228 <reg32 offset="0x23b14" name="GMU_AHB_FENCE_STATUS_CLR"/> 229 <reg32 offset="0x23b15" name="GMU_RBBM_INT_UNMASKED_STATUS"/> 230 <reg32 offset="0x23b16" name="GMU_AO_SPARE_CNTL"/> 231 <reg32 offset="0x23b07" name="GMU_RSCC_CONTROL_REQ"/> 232 <reg32 offset="0x23b08" name="GMU_RSCC_CONTROL_ACK"/> 233 <reg32 offset="0x23b11" name="GMU_AHB_FENCE_RANGE_0"/> 234 <reg32 offset="0x23b12" name="GMU_AHB_FENCE_RANGE_1"/> 235 <reg32 offset="0x24403" name="GPU_CC_GX_GDSCR"/> 236 <reg32 offset="0x24542" name="GPU_CC_GX_DOMAIN_MISC"/> 237 <reg32 offset="0x26801" name="GPU_CPR_FSM_CTL"/> 238 239 <!-- starts at offset 0x8c00 on most gpus --> 240 <reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/> 241 <reg32 offset="0x0008" name="RSCC_PDC_SEQ_START_ADDR"/> 242 <reg32 offset="0x0009" name="RSCC_PDC_MATCH_VALUE_LO"/> 243 <reg32 offset="0x000a" name="RSCC_PDC_MATCH_VALUE_HI"/> 244 <reg32 offset="0x000b" name="RSCC_PDC_SLAVE_ID_DRV0"/> 245 <reg32 offset="0x000d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/> 246 <reg32 offset="0x000e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/> 247 <reg32 offset="0x0082" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/> 248 <reg32 offset="0x0083" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/> 249 <reg32 offset="0x0089" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/> 250 <reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/> 251 <reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/> 252 <reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/> 253 <reg32 offset="0x0154" name="RSCC_SEQ_MEM_0_DRV0_A740" variants="A7XX"/> 254 <reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/> 255 <reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/> 256 <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/> 257 <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/> 258 <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/> 259 <reg32 offset="0x05e6" name="RSCC_TCS4_DRV0_STATUS" variants="A7XX-"/> 260 <reg32 offset="0x068e" name="RSCC_TCS5_DRV0_STATUS" variants="A7XX-"/> 261 <reg32 offset="0x0736" name="RSCC_TCS6_DRV0_STATUS" variants="A7XX-"/> 262 <reg32 offset="0x07de" name="RSCC_TCS7_DRV0_STATUS" variants="A7XX-"/> 263 <reg32 offset="0x0886" name="RSCC_TCS8_DRV0_STATUS" variants="A7XX-"/> 264 <reg32 offset="0x092e" name="RSCC_TCS9_DRV0_STATUS" variants="A7XX-"/> 265</domain> 266 267</database>
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