msm_gpu.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2013 Red Hat
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 */
   6
   7#include "drm/drm_drv.h"
   8
   9#include "msm_gpu.h"
  10#include "msm_gem.h"
  11#include "msm_mmu.h"
  12#include "msm_fence.h"
  13#include "msm_gpu_trace.h"
  14//#include "adreno/adreno_gpu.h"
  15
  16#include <generated/utsrelease.h>
  17#include <linux/string_helpers.h>
  18#include <linux/devcoredump.h>
  19#include <linux/sched/task.h>
  20
  21/*
  22 * Power Management:
  23 */
  24
  25static int enable_pwrrail(struct msm_gpu *gpu)
  26{
  27	struct drm_device *dev = gpu->dev;
  28	int ret = 0;
  29
  30	if (gpu->gpu_reg) {
  31		ret = regulator_enable(gpu->gpu_reg);
  32		if (ret) {
  33			DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
  34			return ret;
  35		}
  36	}
  37
  38	if (gpu->gpu_cx) {
  39		ret = regulator_enable(gpu->gpu_cx);
  40		if (ret) {
  41			DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
  42			return ret;
  43		}
  44	}
  45
  46	return 0;
  47}
  48
  49static int disable_pwrrail(struct msm_gpu *gpu)
  50{
  51	if (gpu->gpu_cx)
  52		regulator_disable(gpu->gpu_cx);
  53	if (gpu->gpu_reg)
  54		regulator_disable(gpu->gpu_reg);
  55	return 0;
  56}
  57
  58static int enable_clk(struct msm_gpu *gpu)
  59{
  60	if (gpu->core_clk && gpu->fast_rate)
  61		dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate);
  62
  63	/* Set the RBBM timer rate to 19.2Mhz */
  64	if (gpu->rbbmtimer_clk)
  65		clk_set_rate(gpu->rbbmtimer_clk, 19200000);
  66
  67	return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
  68}
  69
  70static int disable_clk(struct msm_gpu *gpu)
  71{
  72	clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
  73
  74	/*
  75	 * Set the clock to a deliberately low rate. On older targets the clock
  76	 * speed had to be non zero to avoid problems. On newer targets this
  77	 * will be rounded down to zero anyway so it all works out.
  78	 */
  79	if (gpu->core_clk)
  80		dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000);
  81
  82	if (gpu->rbbmtimer_clk)
  83		clk_set_rate(gpu->rbbmtimer_clk, 0);
  84
  85	return 0;
  86}
  87
  88static int enable_axi(struct msm_gpu *gpu)
  89{
  90	return clk_prepare_enable(gpu->ebi1_clk);
  91}
  92
  93static int disable_axi(struct msm_gpu *gpu)
  94{
  95	clk_disable_unprepare(gpu->ebi1_clk);
  96	return 0;
  97}
  98
  99int msm_gpu_pm_resume(struct msm_gpu *gpu)
 100{
 101	int ret;
 102
 103	DBG("%s", gpu->name);
 104	trace_msm_gpu_resume(0);
 105
 106	ret = enable_pwrrail(gpu);
 107	if (ret)
 108		return ret;
 109
 110	ret = enable_clk(gpu);
 111	if (ret)
 112		return ret;
 113
 114	ret = enable_axi(gpu);
 115	if (ret)
 116		return ret;
 117
 118	msm_devfreq_resume(gpu);
 119
 120	gpu->needs_hw_init = true;
 121
 122	return 0;
 123}
 124
 125int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 126{
 127	int ret;
 128
 129	DBG("%s", gpu->name);
 130	trace_msm_gpu_suspend(0);
 131
 132	msm_devfreq_suspend(gpu);
 133
 134	ret = disable_axi(gpu);
 135	if (ret)
 136		return ret;
 137
 138	ret = disable_clk(gpu);
 139	if (ret)
 140		return ret;
 141
 142	ret = disable_pwrrail(gpu);
 143	if (ret)
 144		return ret;
 145
 146	gpu->suspend_count++;
 147
 148	return 0;
 149}
 150
 151void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx,
 152			 struct drm_printer *p)
 153{
 154	drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
 155	drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
 156	drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
 157}
 158
 159int msm_gpu_hw_init(struct msm_gpu *gpu)
 160{
 161	int ret;
 162
 163	WARN_ON(!mutex_is_locked(&gpu->lock));
 164
 165	if (!gpu->needs_hw_init)
 166		return 0;
 167
 168	disable_irq(gpu->irq);
 169	ret = gpu->funcs->hw_init(gpu);
 170	if (!ret)
 171		gpu->needs_hw_init = false;
 172	enable_irq(gpu->irq);
 173
 174	return ret;
 175}
 176
 177#ifdef CONFIG_DEV_COREDUMP
 178static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 179		size_t count, void *data, size_t datalen)
 180{
 181	struct msm_gpu *gpu = data;
 182	struct drm_print_iterator iter;
 183	struct drm_printer p;
 184	struct msm_gpu_state *state;
 185
 186	state = msm_gpu_crashstate_get(gpu);
 187	if (!state)
 188		return 0;
 189
 190	iter.data = buffer;
 191	iter.offset = 0;
 192	iter.start = offset;
 193	iter.remain = count;
 194
 195	p = drm_coredump_printer(&iter);
 196
 197	drm_printf(&p, "---\n");
 198	drm_printf(&p, "kernel: " UTS_RELEASE "\n");
 199	drm_printf(&p, "module: " KBUILD_MODNAME "\n");
 200	drm_printf(&p, "time: %ptSp\n", &state->time);
 201	if (state->comm)
 202		drm_printf(&p, "comm: %s\n", state->comm);
 203	if (state->cmd)
 204		drm_printf(&p, "cmdline: %s\n", state->cmd);
 205
 206	gpu->funcs->show(gpu, state, &p);
 207
 208	msm_gpu_crashstate_put(gpu);
 209
 210	return count - iter.remain;
 211}
 212
 213static void msm_gpu_devcoredump_free(void *data)
 214{
 215	struct msm_gpu *gpu = data;
 216
 217	msm_gpu_crashstate_put(gpu);
 218}
 219
 220static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 221				      struct drm_gem_object *obj, u64 iova,
 222				      bool full, size_t offset, size_t size)
 223{
 224	struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 225	struct msm_gem_object *msm_obj = to_msm_bo(obj);
 226
 227	/* Don't record write only objects */
 228	state_bo->size = size;
 229	state_bo->flags = msm_obj->flags;
 230	state_bo->iova = iova;
 231
 232	BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(msm_obj->name));
 233
 234	memcpy(state_bo->name, msm_obj->name, sizeof(state_bo->name));
 235
 236	if (full) {
 237		void *ptr;
 238
 239		state_bo->data = kvmalloc(size, GFP_KERNEL);
 240		if (!state_bo->data)
 241			goto out;
 242
 243		ptr = msm_gem_get_vaddr_active(obj);
 244		if (IS_ERR(ptr)) {
 245			kvfree(state_bo->data);
 246			state_bo->data = NULL;
 247			goto out;
 248		}
 249
 250		memcpy(state_bo->data, ptr + offset, size);
 251		msm_gem_put_vaddr_locked(obj);
 252	}
 253out:
 254	state->nr_bos++;
 255}
 256
 257static void crashstate_get_bos(struct msm_gpu_state *state, struct msm_gem_submit *submit)
 258{
 259	extern bool rd_full;
 260
 261	if (msm_context_is_vmbind(submit->queue->ctx)) {
 262		struct drm_exec exec;
 263		struct drm_gpuva *vma;
 264		unsigned cnt = 0;
 265
 266		drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
 267		drm_exec_until_all_locked(&exec) {
 268			cnt = 0;
 269
 270			drm_exec_lock_obj(&exec, drm_gpuvm_resv_obj(submit->vm));
 271			drm_exec_retry_on_contention(&exec);
 272
 273			drm_gpuvm_for_each_va (vma, submit->vm) {
 274				if (!vma->gem.obj)
 275					continue;
 276
 277				cnt++;
 278				drm_exec_lock_obj(&exec, vma->gem.obj);
 279				drm_exec_retry_on_contention(&exec);
 280			}
 281
 282		}
 283
 284		drm_gpuvm_for_each_va (vma, submit->vm)
 285			cnt++;
 286
 287		state->bos = kcalloc(cnt, sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 288
 289		if (state->bos)
 290			drm_gpuvm_for_each_va(vma, submit->vm) {
 291				bool dump = rd_full || (vma->flags & MSM_VMA_DUMP);
 292
 293				/* Skip MAP_NULL/PRR VMAs: */
 294				if (!vma->gem.obj)
 295					continue;
 296
 297				msm_gpu_crashstate_get_bo(state, vma->gem.obj, vma->va.addr,
 298							  dump, vma->gem.offset, vma->va.range);
 299			}
 300
 301		drm_exec_fini(&exec);
 302	} else {
 303		state->bos = kcalloc(submit->nr_bos,
 304			sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 305
 306		for (int i = 0; state->bos && i < submit->nr_bos; i++) {
 307			struct drm_gem_object *obj = submit->bos[i].obj;
 308			bool dump = rd_full || (submit->bos[i].flags & MSM_SUBMIT_BO_DUMP);
 309
 310			msm_gem_lock(obj);
 311			msm_gpu_crashstate_get_bo(state, obj, submit->bos[i].iova,
 312						  dump, 0, obj->size);
 313			msm_gem_unlock(obj);
 314		}
 315	}
 316}
 317
 318static void crashstate_get_vm_logs(struct msm_gpu_state *state, struct msm_gem_vm *vm)
 319{
 320	uint32_t vm_log_len = (1 << vm->log_shift);
 321	uint32_t vm_log_mask = vm_log_len - 1;
 322	int first;
 323
 324	/* Bail if no log, or empty log: */
 325	if (!vm->log || !vm->log[0].op)
 326		return;
 327
 328	mutex_lock(&vm->mmu_lock);
 329
 330	/*
 331	 * log_idx is the next entry to overwrite, meaning it is the oldest, or
 332	 * first, entry (other than the special case handled below where the
 333	 * log hasn't wrapped around yet)
 334	 */
 335	first = vm->log_idx;
 336
 337	if (!vm->log[first].op) {
 338		/*
 339		 * If the next log entry has not been written yet, then only
 340		 * entries 0 to idx-1 are valid (ie. we haven't wrapped around
 341		 * yet)
 342		 */
 343		state->nr_vm_logs = MAX(0, first - 1);
 344		first = 0;
 345	} else {
 346		state->nr_vm_logs = vm_log_len;
 347	}
 348
 349	state->vm_logs = kmalloc_array(
 350		state->nr_vm_logs, sizeof(vm->log[0]), GFP_KERNEL);
 351	if (!state->vm_logs) {
 352		state->nr_vm_logs = 0;
 353	}
 354
 355	for (int i = 0; i < state->nr_vm_logs; i++) {
 356		int idx = (i + first) & vm_log_mask;
 357
 358		state->vm_logs[i] = vm->log[idx];
 359	}
 360
 361	mutex_unlock(&vm->mmu_lock);
 362}
 363
 364static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 365		struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
 366		char *comm, char *cmd)
 367{
 368	struct msm_gpu_state *state;
 369
 370	/* Check if the target supports capturing crash state */
 371	if (!gpu->funcs->gpu_state_get)
 372		return;
 373
 374	/* Only save one crash state at a time */
 375	if (gpu->crashstate)
 376		return;
 377
 378	state = gpu->funcs->gpu_state_get(gpu);
 379	if (IS_ERR_OR_NULL(state))
 380		return;
 381
 382	/* Fill in the additional crash state information */
 383	state->comm = kstrdup(comm, GFP_KERNEL);
 384	state->cmd = kstrdup(cmd, GFP_KERNEL);
 385	if (fault_info)
 386		state->fault_info = *fault_info;
 387
 388	if (submit && state->fault_info.ttbr0) {
 389		struct msm_gpu_fault_info *info = &state->fault_info;
 390		struct msm_mmu *mmu = to_msm_vm(submit->vm)->mmu;
 391
 392		msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0,
 393					   &info->asid);
 394		msm_iommu_pagetable_walk(mmu, info->iova, info->ptes);
 395	}
 396
 397	if (submit) {
 398		crashstate_get_vm_logs(state, to_msm_vm(submit->vm));
 399		crashstate_get_bos(state, submit);
 400	}
 401
 402	/* Set the active crash state to be dumped on failure */
 403	gpu->crashstate = state;
 404
 405	dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
 406		msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
 407}
 408#else
 409static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 410		struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
 411		char *comm, char *cmd)
 412{
 413}
 414#endif
 415
 416/*
 417 * Hangcheck detection for locked gpu:
 418 */
 419
 420static struct msm_gem_submit *
 421find_submit(struct msm_ringbuffer *ring, uint32_t fence)
 422{
 423	struct msm_gem_submit *submit;
 424	unsigned long flags;
 425
 426	spin_lock_irqsave(&ring->submit_lock, flags);
 427	list_for_each_entry(submit, &ring->submits, node) {
 428		if (submit->seqno == fence) {
 429			spin_unlock_irqrestore(&ring->submit_lock, flags);
 430			return submit;
 431		}
 432	}
 433	spin_unlock_irqrestore(&ring->submit_lock, flags);
 434
 435	return NULL;
 436}
 437
 438static void retire_submits(struct msm_gpu *gpu);
 439
 440static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
 441{
 442	struct msm_context *ctx = submit->queue->ctx;
 443	struct task_struct *task;
 444
 445	WARN_ON(!mutex_is_locked(&submit->gpu->lock));
 446
 447	/* Note that kstrdup will return NULL if argument is NULL: */
 448	*comm = kstrdup(ctx->comm, GFP_KERNEL);
 449	*cmd  = kstrdup(ctx->cmdline, GFP_KERNEL);
 450
 451	task = get_pid_task(submit->pid, PIDTYPE_PID);
 452	if (!task)
 453		return;
 454
 455	if (!*comm)
 456		*comm = kstrdup(task->comm, GFP_KERNEL);
 457
 458	if (!*cmd)
 459		*cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
 460
 461	put_task_struct(task);
 462}
 463
 464static void recover_worker(struct kthread_work *work)
 465{
 466	struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
 467	struct drm_device *dev = gpu->dev;
 468	struct msm_drm_private *priv = dev->dev_private;
 469	struct msm_gem_submit *submit;
 470	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 471	char *comm = NULL, *cmd = NULL;
 472	struct task_struct *task;
 473	int i;
 474
 475	mutex_lock(&gpu->lock);
 476
 477	DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 478
 479	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 480
 481	/*
 482	 * If the submit retired while we were waiting for the worker to run,
 483	 * or waiting to acquire the gpu lock, then nothing more to do.
 484	 */
 485	if (!submit)
 486		goto out_unlock;
 487
 488	/* Increment the fault counts */
 489	submit->queue->faults++;
 490
 491	task = get_pid_task(submit->pid, PIDTYPE_PID);
 492	if (!task)
 493		gpu->global_faults++;
 494	else {
 495		struct msm_gem_vm *vm = to_msm_vm(submit->vm);
 496
 497		vm->faults++;
 498
 499		/*
 500		 * If userspace has opted-in to VM_BIND (and therefore userspace
 501		 * management of the VM), faults mark the VM as unusable. This
 502		 * matches vulkan expectations (vulkan is the main target for
 503		 * VM_BIND).
 504		 */
 505		if (!vm->managed)
 506			msm_gem_vm_unusable(submit->vm);
 507	}
 508
 509	get_comm_cmdline(submit, &comm, &cmd);
 510
 511	if (comm && cmd) {
 512		DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
 513			      gpu->name, comm, cmd);
 514
 515		msm_rd_dump_submit(priv->hangrd, submit,
 516				   "offending task: %s (%s)", comm, cmd);
 517	} else {
 518		DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name);
 519
 520		msm_rd_dump_submit(priv->hangrd, submit, NULL);
 521	}
 522
 523	/* Record the crash state */
 524	pm_runtime_get_sync(&gpu->pdev->dev);
 525	msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd);
 526
 527	kfree(cmd);
 528	kfree(comm);
 529
 530	/*
 531	 * Update all the rings with the latest and greatest fence.. this
 532	 * needs to happen after msm_rd_dump_submit() to ensure that the
 533	 * bo's referenced by the offending submit are still around.
 534	 */
 535	for (i = 0; i < gpu->nr_rings; i++) {
 536		struct msm_ringbuffer *ring = gpu->rb[i];
 537
 538		uint32_t fence = ring->memptrs->fence;
 539
 540		/*
 541		 * For the current (faulting?) ring/submit advance the fence by
 542		 * one more to clear the faulting submit
 543		 */
 544		if (ring == cur_ring)
 545			ring->memptrs->fence = ++fence;
 546
 547		msm_update_fence(ring->fctx, fence);
 548	}
 549
 550	if (msm_gpu_active(gpu)) {
 551		/* retire completed submits, plus the one that hung: */
 552		retire_submits(gpu);
 553
 554		gpu->funcs->recover(gpu);
 555
 556		/*
 557		 * Replay all remaining submits starting with highest priority
 558		 * ring
 559		 */
 560		for (i = 0; i < gpu->nr_rings; i++) {
 561			struct msm_ringbuffer *ring = gpu->rb[i];
 562			unsigned long flags;
 563
 564			spin_lock_irqsave(&ring->submit_lock, flags);
 565			list_for_each_entry(submit, &ring->submits, node) {
 566				/*
 567				 * If the submit uses an unusable vm make sure
 568				 * we don't actually run it
 569				 */
 570				if (to_msm_vm(submit->vm)->unusable)
 571					submit->nr_cmds = 0;
 572				gpu->funcs->submit(gpu, submit);
 573			}
 574			spin_unlock_irqrestore(&ring->submit_lock, flags);
 575		}
 576	}
 577
 578	pm_runtime_put(&gpu->pdev->dev);
 579
 580out_unlock:
 581	mutex_unlock(&gpu->lock);
 582
 583	msm_gpu_retire(gpu);
 584}
 585
 586void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info)
 587{
 588	struct msm_gem_submit *submit;
 589	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 590	char *comm = NULL, *cmd = NULL;
 591
 592	mutex_lock(&gpu->lock);
 593
 594	submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 595	if (submit && submit->fault_dumped)
 596		goto resume_smmu;
 597
 598	if (submit) {
 599		get_comm_cmdline(submit, &comm, &cmd);
 600
 601		/*
 602		 * When we get GPU iova faults, we can get 1000s of them,
 603		 * but we really only want to log the first one.
 604		 */
 605		submit->fault_dumped = true;
 606	}
 607
 608	/* Record the crash state */
 609	pm_runtime_get_sync(&gpu->pdev->dev);
 610	msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd);
 611	pm_runtime_put_sync(&gpu->pdev->dev);
 612
 613	kfree(cmd);
 614	kfree(comm);
 615
 616resume_smmu:
 617	mutex_unlock(&gpu->lock);
 618}
 619
 620static void hangcheck_timer_reset(struct msm_gpu *gpu)
 621{
 622	struct msm_drm_private *priv = gpu->dev->dev_private;
 623	mod_timer(&gpu->hangcheck_timer,
 624			round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
 625}
 626
 627static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 628{
 629	if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES)
 630		return false;
 631
 632	if (!gpu->funcs->progress)
 633		return false;
 634
 635	if (!gpu->funcs->progress(gpu, ring))
 636		return false;
 637
 638	ring->hangcheck_progress_retries++;
 639	return true;
 640}
 641
 642static void hangcheck_handler(struct timer_list *t)
 643{
 644	struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer);
 645	struct drm_device *dev = gpu->dev;
 646	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
 647	uint32_t fence = ring->memptrs->fence;
 648
 649	if (fence != ring->hangcheck_fence) {
 650		/* some progress has been made.. ya! */
 651		ring->hangcheck_fence = fence;
 652		ring->hangcheck_progress_retries = 0;
 653	} else if (fence_before(fence, ring->fctx->last_fence) &&
 654			!made_progress(gpu, ring)) {
 655		/* no progress and not done.. hung! */
 656		ring->hangcheck_fence = fence;
 657		ring->hangcheck_progress_retries = 0;
 658		DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
 659				gpu->name, ring->id);
 660		DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
 661				gpu->name, fence);
 662		DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
 663				gpu->name, ring->fctx->last_fence);
 664
 665		kthread_queue_work(gpu->worker, &gpu->recover_work);
 666	}
 667
 668	/* if still more pending work, reset the hangcheck timer: */
 669	if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
 670		hangcheck_timer_reset(gpu);
 671
 672	/* workaround for missing irq: */
 673	msm_gpu_retire(gpu);
 674}
 675
 676/*
 677 * Performance Counters:
 678 */
 679
 680/* called under perf_lock */
 681static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
 682{
 683	uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
 684	int i, n = min(ncntrs, gpu->num_perfcntrs);
 685
 686	/* read current values: */
 687	for (i = 0; i < gpu->num_perfcntrs; i++)
 688		current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
 689
 690	/* update cntrs: */
 691	for (i = 0; i < n; i++)
 692		cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
 693
 694	/* save current values: */
 695	for (i = 0; i < gpu->num_perfcntrs; i++)
 696		gpu->last_cntrs[i] = current_cntrs[i];
 697
 698	return n;
 699}
 700
 701static void update_sw_cntrs(struct msm_gpu *gpu)
 702{
 703	ktime_t time;
 704	uint32_t elapsed;
 705	unsigned long flags;
 706
 707	spin_lock_irqsave(&gpu->perf_lock, flags);
 708	if (!gpu->perfcntr_active)
 709		goto out;
 710
 711	time = ktime_get();
 712	elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
 713
 714	gpu->totaltime += elapsed;
 715	if (gpu->last_sample.active)
 716		gpu->activetime += elapsed;
 717
 718	gpu->last_sample.active = msm_gpu_active(gpu);
 719	gpu->last_sample.time = time;
 720
 721out:
 722	spin_unlock_irqrestore(&gpu->perf_lock, flags);
 723}
 724
 725void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
 726{
 727	unsigned long flags;
 728
 729	pm_runtime_get_sync(&gpu->pdev->dev);
 730
 731	spin_lock_irqsave(&gpu->perf_lock, flags);
 732	/* we could dynamically enable/disable perfcntr registers too.. */
 733	gpu->last_sample.active = msm_gpu_active(gpu);
 734	gpu->last_sample.time = ktime_get();
 735	gpu->activetime = gpu->totaltime = 0;
 736	gpu->perfcntr_active = true;
 737	update_hw_cntrs(gpu, 0, NULL);
 738	spin_unlock_irqrestore(&gpu->perf_lock, flags);
 739}
 740
 741void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
 742{
 743	gpu->perfcntr_active = false;
 744	pm_runtime_put_sync(&gpu->pdev->dev);
 745}
 746
 747/* returns -errno or # of cntrs sampled */
 748int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 749		uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
 750{
 751	unsigned long flags;
 752	int ret;
 753
 754	spin_lock_irqsave(&gpu->perf_lock, flags);
 755
 756	if (!gpu->perfcntr_active) {
 757		ret = -EINVAL;
 758		goto out;
 759	}
 760
 761	*activetime = gpu->activetime;
 762	*totaltime = gpu->totaltime;
 763
 764	gpu->activetime = gpu->totaltime = 0;
 765
 766	ret = update_hw_cntrs(gpu, ncntrs, cntrs);
 767
 768out:
 769	spin_unlock_irqrestore(&gpu->perf_lock, flags);
 770
 771	return ret;
 772}
 773
 774/*
 775 * Cmdstream submission/retirement:
 776 */
 777
 778static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 779		struct msm_gem_submit *submit)
 780{
 781	int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 782	volatile struct msm_gpu_submit_stats *stats;
 783	u64 elapsed, clock = 0, cycles;
 784	unsigned long flags;
 785
 786	stats = &ring->memptrs->stats[index];
 787	/* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
 788	elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 789	do_div(elapsed, 192);
 790
 791	cycles = stats->cpcycles_end - stats->cpcycles_start;
 792
 793	/* Calculate the clock frequency from the number of CP cycles */
 794	if (elapsed) {
 795		clock = cycles * 1000;
 796		do_div(clock, elapsed);
 797	}
 798
 799	submit->queue->ctx->elapsed_ns += elapsed;
 800	submit->queue->ctx->cycles     += cycles;
 801
 802	trace_msm_gpu_submit_retired(submit, elapsed, clock,
 803		stats->alwayson_start, stats->alwayson_end);
 804
 805	msm_submit_retire(submit);
 806
 807	pm_runtime_mark_last_busy(&gpu->pdev->dev);
 808
 809	spin_lock_irqsave(&ring->submit_lock, flags);
 810	list_del(&submit->node);
 811	spin_unlock_irqrestore(&ring->submit_lock, flags);
 812
 813	/* Update devfreq on transition from active->idle: */
 814	mutex_lock(&gpu->active_lock);
 815	gpu->active_submits--;
 816	WARN_ON(gpu->active_submits < 0);
 817	if (!gpu->active_submits) {
 818		msm_devfreq_idle(gpu);
 819		pm_runtime_put_autosuspend(&gpu->pdev->dev);
 820	}
 821
 822	mutex_unlock(&gpu->active_lock);
 823
 824	msm_gem_submit_put(submit);
 825}
 826
 827static void retire_submits(struct msm_gpu *gpu)
 828{
 829	int i;
 830
 831	/* Retire the commits starting with highest priority */
 832	for (i = 0; i < gpu->nr_rings; i++) {
 833		struct msm_ringbuffer *ring = gpu->rb[i];
 834
 835		while (true) {
 836			struct msm_gem_submit *submit = NULL;
 837			unsigned long flags;
 838
 839			spin_lock_irqsave(&ring->submit_lock, flags);
 840			submit = list_first_entry_or_null(&ring->submits,
 841					struct msm_gem_submit, node);
 842			spin_unlock_irqrestore(&ring->submit_lock, flags);
 843
 844			/*
 845			 * If no submit, we are done.  If submit->fence hasn't
 846			 * been signalled, then later submits are not signalled
 847			 * either, so we are also done.
 848			 */
 849			if (submit && dma_fence_is_signaled(submit->hw_fence)) {
 850				retire_submit(gpu, ring, submit);
 851			} else {
 852				break;
 853			}
 854		}
 855	}
 856
 857	wake_up_all(&gpu->retire_event);
 858}
 859
 860static void retire_worker(struct kthread_work *work)
 861{
 862	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 863
 864	retire_submits(gpu);
 865}
 866
 867/* call from irq handler to schedule work to retire bo's */
 868void msm_gpu_retire(struct msm_gpu *gpu)
 869{
 870	int i;
 871
 872	for (i = 0; i < gpu->nr_rings; i++)
 873		msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
 874
 875	kthread_queue_work(gpu->worker, &gpu->retire_work);
 876	update_sw_cntrs(gpu);
 877}
 878
 879/* add bo's to gpu's ring, and kick gpu: */
 880void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 881{
 882	struct msm_ringbuffer *ring = submit->ring;
 883	unsigned long flags;
 884
 885	WARN_ON(!mutex_is_locked(&gpu->lock));
 886
 887	pm_runtime_get_sync(&gpu->pdev->dev);
 888
 889	msm_gpu_hw_init(gpu);
 890
 891	submit->seqno = submit->hw_fence->seqno;
 892
 893	update_sw_cntrs(gpu);
 894
 895	/*
 896	 * ring->submits holds a ref to the submit, to deal with the case
 897	 * that a submit completes before msm_ioctl_gem_submit() returns.
 898	 */
 899	msm_gem_submit_get(submit);
 900
 901	spin_lock_irqsave(&ring->submit_lock, flags);
 902	list_add_tail(&submit->node, &ring->submits);
 903	spin_unlock_irqrestore(&ring->submit_lock, flags);
 904
 905	/* Update devfreq on transition from idle->active: */
 906	mutex_lock(&gpu->active_lock);
 907	if (!gpu->active_submits) {
 908		pm_runtime_get(&gpu->pdev->dev);
 909		msm_devfreq_active(gpu);
 910	}
 911	gpu->active_submits++;
 912	mutex_unlock(&gpu->active_lock);
 913
 914	gpu->funcs->submit(gpu, submit);
 915	submit->ring->cur_ctx_seqno = submit->queue->ctx->seqno;
 916
 917	pm_runtime_put(&gpu->pdev->dev);
 918	hangcheck_timer_reset(gpu);
 919}
 920
 921/*
 922 * Init/Cleanup:
 923 */
 924
 925static irqreturn_t irq_handler(int irq, void *data)
 926{
 927	struct msm_gpu *gpu = data;
 928	return gpu->funcs->irq(gpu);
 929}
 930
 931static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 932{
 933	int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
 934
 935	if (ret < 1) {
 936		gpu->nr_clocks = 0;
 937		return ret;
 938	}
 939
 940	gpu->nr_clocks = ret;
 941
 942	gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 943		gpu->nr_clocks, "core");
 944
 945	gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 946		gpu->nr_clocks, "rbbmtimer");
 947
 948	return 0;
 949}
 950
 951/* Return a new address space for a msm_drm_private instance */
 952struct drm_gpuvm *
 953msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task,
 954			  bool kernel_managed)
 955{
 956	struct drm_gpuvm *vm = NULL;
 957
 958	if (!gpu)
 959		return NULL;
 960
 961	/*
 962	 * If the target doesn't support private address spaces then return
 963	 * the global one
 964	 */
 965	if (gpu->funcs->create_private_vm) {
 966		vm = gpu->funcs->create_private_vm(gpu, kernel_managed);
 967		if (!IS_ERR(vm))
 968			to_msm_vm(vm)->pid = get_pid(task_pid(task));
 969	}
 970
 971	if (IS_ERR_OR_NULL(vm))
 972		vm = drm_gpuvm_get(gpu->vm);
 973
 974	return vm;
 975}
 976
 977int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 978		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 979		const char *name, struct msm_gpu_config *config)
 980{
 981	struct msm_drm_private *priv = drm->dev_private;
 982	int i, ret, nr_rings = config->nr_rings;
 983	void *memptrs;
 984	uint64_t memptrs_iova;
 985
 986	if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
 987		gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
 988
 989	gpu->dev = drm;
 990	gpu->funcs = funcs;
 991	gpu->name = name;
 992
 993	gpu->worker = kthread_run_worker(0, "gpu-worker");
 994	if (IS_ERR(gpu->worker)) {
 995		ret = PTR_ERR(gpu->worker);
 996		gpu->worker = NULL;
 997		goto fail;
 998	}
 999
1000	sched_set_fifo_low(gpu->worker->task);
1001
1002	mutex_init(&gpu->active_lock);
1003	mutex_init(&gpu->lock);
1004	init_waitqueue_head(&gpu->retire_event);
1005	kthread_init_work(&gpu->retire_work, retire_worker);
1006	kthread_init_work(&gpu->recover_work, recover_worker);
1007
1008	priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
1009
1010	/*
1011	 * If progress detection is supported, halve the hangcheck timer
1012	 * duration, as it takes two iterations of the hangcheck handler
1013	 * to detect a hang.
1014	 */
1015	if (funcs->progress)
1016		priv->hangcheck_period /= 2;
1017
1018	timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
1019
1020	spin_lock_init(&gpu->perf_lock);
1021
1022
1023	/* Map registers: */
1024	gpu->mmio = msm_ioremap(pdev, config->ioname);
1025	if (IS_ERR(gpu->mmio)) {
1026		ret = PTR_ERR(gpu->mmio);
1027		goto fail;
1028	}
1029
1030	/* Get Interrupt: */
1031	gpu->irq = platform_get_irq(pdev, 0);
1032	if (gpu->irq < 0) {
1033		ret = gpu->irq;
1034		goto fail;
1035	}
1036
1037	ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
1038			IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
1039	if (ret) {
1040		DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
1041		goto fail;
1042	}
1043
1044	ret = get_clocks(pdev, gpu);
1045	if (ret)
1046		goto fail;
1047
1048	gpu->ebi1_clk = msm_clk_get(pdev, "bus");
1049	DBG("ebi1_clk: %p", gpu->ebi1_clk);
1050	if (IS_ERR(gpu->ebi1_clk))
1051		gpu->ebi1_clk = NULL;
1052
1053	/* Acquire regulators: */
1054	gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
1055	DBG("gpu_reg: %p", gpu->gpu_reg);
1056	if (IS_ERR(gpu->gpu_reg))
1057		gpu->gpu_reg = NULL;
1058
1059	gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
1060	DBG("gpu_cx: %p", gpu->gpu_cx);
1061	if (IS_ERR(gpu->gpu_cx))
1062		gpu->gpu_cx = NULL;
1063
1064	platform_set_drvdata(pdev, &gpu->adreno_smmu);
1065
1066	msm_devfreq_init(gpu);
1067
1068	gpu->vm = gpu->funcs->create_vm(gpu, pdev);
1069	if (IS_ERR(gpu->vm)) {
1070		ret = PTR_ERR(gpu->vm);
1071		goto fail;
1072	}
1073
1074	memptrs = msm_gem_kernel_new(drm,
1075		sizeof(struct msm_rbmemptrs) * nr_rings,
1076		check_apriv(gpu, MSM_BO_WC), gpu->vm, &gpu->memptrs_bo,
1077		&memptrs_iova);
1078
1079	if (IS_ERR(memptrs)) {
1080		ret = PTR_ERR(memptrs);
1081		DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
1082		goto fail;
1083	}
1084
1085	msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
1086
1087	if (nr_rings > ARRAY_SIZE(gpu->rb)) {
1088		DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
1089			ARRAY_SIZE(gpu->rb));
1090		nr_rings = ARRAY_SIZE(gpu->rb);
1091	}
1092
1093	/* Create ringbuffer(s): */
1094	for (i = 0; i < nr_rings; i++) {
1095		gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
1096
1097		if (IS_ERR(gpu->rb[i])) {
1098			ret = PTR_ERR(gpu->rb[i]);
1099			DRM_DEV_ERROR(drm->dev,
1100				"could not create ringbuffer %d: %d\n", i, ret);
1101			goto fail;
1102		}
1103
1104		memptrs += sizeof(struct msm_rbmemptrs);
1105		memptrs_iova += sizeof(struct msm_rbmemptrs);
1106	}
1107
1108	gpu->nr_rings = nr_rings;
1109
1110	refcount_set(&gpu->sysprof_active, 1);
1111
1112	return 0;
1113
1114fail:
1115	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
1116		msm_ringbuffer_destroy(gpu->rb[i]);
1117		gpu->rb[i] = NULL;
1118	}
1119
1120	msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
1121
1122	platform_set_drvdata(pdev, NULL);
1123	return ret;
1124}
1125
1126void msm_gpu_cleanup(struct msm_gpu *gpu)
1127{
1128	int i;
1129
1130	DBG("%s", gpu->name);
1131
1132	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1133		msm_ringbuffer_destroy(gpu->rb[i]);
1134		gpu->rb[i] = NULL;
1135	}
1136
1137	msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
1138
1139	if (!IS_ERR_OR_NULL(gpu->vm)) {
1140		struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
1141		mmu->funcs->detach(mmu);
1142		drm_gpuvm_put(gpu->vm);
1143	}
1144
1145	if (gpu->worker) {
1146		kthread_destroy_worker(gpu->worker);
1147	}
1148
1149	msm_devfreq_cleanup(gpu);
1150
1151	platform_set_drvdata(gpu->pdev, NULL);
1152}