hdmi_i2c.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2013 Red Hat
  4 * Author: Rob Clark <robdclark@gmail.com>
  5 */
  6
  7#include "hdmi.h"
  8
  9struct hdmi_i2c_adapter {
 10	struct i2c_adapter base;
 11	struct hdmi *hdmi;
 12	bool sw_done;
 13	wait_queue_head_t ddc_event;
 14};
 15#define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base)
 16
 17static void init_ddc(struct hdmi_i2c_adapter *hdmi_i2c)
 18{
 19	struct hdmi *hdmi = hdmi_i2c->hdmi;
 20
 21	hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
 22			HDMI_DDC_CTRL_SW_STATUS_RESET);
 23	hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
 24			HDMI_DDC_CTRL_SOFT_RESET);
 25
 26	hdmi_write(hdmi, REG_HDMI_DDC_SPEED,
 27			HDMI_DDC_SPEED_THRESHOLD(2) |
 28			HDMI_DDC_SPEED_PRESCALE(10));
 29
 30	hdmi_write(hdmi, REG_HDMI_DDC_SETUP,
 31			HDMI_DDC_SETUP_TIMEOUT(0xff));
 32
 33	/* enable reference timer for 27us */
 34	hdmi_write(hdmi, REG_HDMI_DDC_REF,
 35			HDMI_DDC_REF_REFTIMER_ENABLE |
 36			HDMI_DDC_REF_REFTIMER(27));
 37}
 38
 39static int ddc_clear_irq(struct hdmi_i2c_adapter *hdmi_i2c)
 40{
 41	struct hdmi *hdmi = hdmi_i2c->hdmi;
 42	struct drm_device *dev = hdmi->dev;
 43	uint32_t retry = 0xffff;
 44	uint32_t ddc_int_ctrl;
 45
 46	do {
 47		--retry;
 48
 49		hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
 50				HDMI_DDC_INT_CTRL_SW_DONE_ACK |
 51				HDMI_DDC_INT_CTRL_SW_DONE_MASK);
 52
 53		ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
 54
 55	} while ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT) && retry);
 56
 57	if (!retry) {
 58		DRM_DEV_ERROR(dev->dev, "timeout waiting for DDC\n");
 59		return -ETIMEDOUT;
 60	}
 61
 62	hdmi_i2c->sw_done = false;
 63
 64	return 0;
 65}
 66
 67#define MAX_TRANSACTIONS 4
 68
 69static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c)
 70{
 71	struct hdmi *hdmi = hdmi_i2c->hdmi;
 72
 73	if (!hdmi_i2c->sw_done) {
 74		uint32_t ddc_int_ctrl;
 75
 76		ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
 77
 78		if ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_MASK) &&
 79				(ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT)) {
 80			hdmi_i2c->sw_done = true;
 81			hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
 82					HDMI_DDC_INT_CTRL_SW_DONE_ACK);
 83		}
 84	}
 85
 86	return hdmi_i2c->sw_done;
 87}
 88
 89static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
 90		struct i2c_msg *msgs, int num)
 91{
 92	struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
 93	struct hdmi *hdmi = hdmi_i2c->hdmi;
 94	struct drm_device *dev = hdmi->dev;
 95	static const uint32_t nack[] = {
 96			HDMI_DDC_SW_STATUS_NACK0, HDMI_DDC_SW_STATUS_NACK1,
 97			HDMI_DDC_SW_STATUS_NACK2, HDMI_DDC_SW_STATUS_NACK3,
 98	};
 99	int indices[MAX_TRANSACTIONS];
100	int ret, i, j, index = 0;
101	uint32_t ddc_status, ddc_data, i2c_trans;
102
103	num = min(num, MAX_TRANSACTIONS);
104
105	WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE));
106
107	if (num == 0)
108		return num;
109
110	ret = pm_runtime_resume_and_get(&hdmi->pdev->dev);
111	if (ret)
112		return ret;
113
114	init_ddc(hdmi_i2c);
115
116	ret = ddc_clear_irq(hdmi_i2c);
117	if (ret)
118		goto fail;
119
120	for (i = 0; i < num; i++) {
121		struct i2c_msg *p = &msgs[i];
122		uint32_t raw_addr = p->addr << 1;
123
124		if (p->flags & I2C_M_RD)
125			raw_addr |= 1;
126
127		ddc_data = HDMI_DDC_DATA_DATA(raw_addr) |
128				HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
129
130		if (i == 0) {
131			ddc_data |= HDMI_DDC_DATA_INDEX(0) |
132					HDMI_DDC_DATA_INDEX_WRITE;
133		}
134
135		hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
136		index++;
137
138		indices[i] = index;
139
140		if (p->flags & I2C_M_RD) {
141			index += p->len;
142		} else {
143			for (j = 0; j < p->len; j++) {
144				ddc_data = HDMI_DDC_DATA_DATA(p->buf[j]) |
145						HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
146				hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
147				index++;
148			}
149		}
150
151		i2c_trans = HDMI_I2C_TRANSACTION_REG_CNT(p->len) |
152				HDMI_I2C_TRANSACTION_REG_RW(
153						(p->flags & I2C_M_RD) ? DDC_READ : DDC_WRITE) |
154				HDMI_I2C_TRANSACTION_REG_START;
155
156		if (i == (num - 1))
157			i2c_trans |= HDMI_I2C_TRANSACTION_REG_STOP;
158
159		hdmi_write(hdmi, REG_HDMI_I2C_TRANSACTION(i), i2c_trans);
160	}
161
162	/* trigger the transfer: */
163	hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
164			HDMI_DDC_CTRL_TRANSACTION_CNT(num - 1) |
165			HDMI_DDC_CTRL_GO);
166
167	ret = wait_event_timeout(hdmi_i2c->ddc_event, sw_done(hdmi_i2c), HZ/4);
168	if (ret <= 0) {
169		if (ret == 0)
170			ret = -ETIMEDOUT;
171		dev_warn(dev->dev, "DDC timeout: %d\n", ret);
172		DBG("sw_status=%08x, hw_status=%08x, int_ctrl=%08x",
173				hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS),
174				hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS),
175				hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL));
176		goto fail;
177	}
178
179	ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS);
180
181	/* read back results of any read transactions: */
182	for (i = 0; i < num; i++) {
183		struct i2c_msg *p = &msgs[i];
184
185		if (!(p->flags & I2C_M_RD))
186			continue;
187
188		/* check for NACK: */
189		if (ddc_status & nack[i]) {
190			DBG("ddc_status=%08x", ddc_status);
191			break;
192		}
193
194		ddc_data = HDMI_DDC_DATA_DATA_RW(DDC_READ) |
195				HDMI_DDC_DATA_INDEX(indices[i]) |
196				HDMI_DDC_DATA_INDEX_WRITE;
197
198		hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
199
200		/* discard first byte: */
201		hdmi_read(hdmi, REG_HDMI_DDC_DATA);
202
203		for (j = 0; j < p->len; j++) {
204			ddc_data = hdmi_read(hdmi, REG_HDMI_DDC_DATA);
205			p->buf[j] = FIELD(ddc_data, HDMI_DDC_DATA_DATA);
206		}
207	}
208
209	pm_runtime_put(&hdmi->pdev->dev);
210
211	return i;
212
213fail:
214	pm_runtime_put(&hdmi->pdev->dev);
215	return ret;
216}
217
218static u32 msm_hdmi_i2c_func(struct i2c_adapter *adapter)
219{
220	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
221}
222
223static const struct i2c_algorithm msm_hdmi_i2c_algorithm = {
224	.master_xfer	= msm_hdmi_i2c_xfer,
225	.functionality	= msm_hdmi_i2c_func,
226};
227
228void msm_hdmi_i2c_irq(struct i2c_adapter *i2c)
229{
230	struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
231
232	if (sw_done(hdmi_i2c))
233		wake_up_all(&hdmi_i2c->ddc_event);
234}
235
236void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c)
237{
238	struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
239	i2c_del_adapter(i2c);
240	kfree(hdmi_i2c);
241}
242
243struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi)
244{
245	struct hdmi_i2c_adapter *hdmi_i2c;
246	struct i2c_adapter *i2c = NULL;
247	int ret;
248
249	hdmi_i2c = kzalloc(sizeof(*hdmi_i2c), GFP_KERNEL);
250	if (!hdmi_i2c) {
251		ret = -ENOMEM;
252		goto fail;
253	}
254
255	i2c = &hdmi_i2c->base;
256
257	hdmi_i2c->hdmi = hdmi;
258	init_waitqueue_head(&hdmi_i2c->ddc_event);
259
260
261	i2c->owner = THIS_MODULE;
262	snprintf(i2c->name, sizeof(i2c->name), "msm hdmi i2c");
263	i2c->dev.parent = &hdmi->pdev->dev;
264	i2c->algo = &msm_hdmi_i2c_algorithm;
265
266	ret = i2c_add_adapter(i2c);
267	if (ret)
268		goto fail;
269
270	return i2c;
271
272fail:
273	if (i2c)
274		msm_hdmi_i2c_destroy(i2c);
275	return ERR_PTR(ret);
276}