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dsi_phy_14nm.c
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linux-6.19.14/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/delay.h> 10 11#include "dsi_phy.h" 12#include "dsi.xml.h" 13#include "dsi_phy_14nm.xml.h" 14 15#define PHY_14NM_CKLN_IDX 4 16 17/* 18 * DSI PLL 14nm - clock diagram (eg: DSI0): 19 * 20 * dsi0n1_postdiv_clk 21 * | 22 * | 23 * +----+ | +----+ 24 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte 25 * +----+ | +----+ 26 * | dsi0n1_postdivby2_clk 27 * | +----+ | 28 * o---| /2 |--o--|\ 29 * | +----+ | \ +----+ 30 * | | |--| n2 |-- dsi0pll 31 * o--------------| / +----+ 32 * |/ 33 */ 34 35#define POLL_MAX_READS 15 36#define POLL_TIMEOUT_US 1000 37 38#define VCO_REF_CLK_RATE 19200000 39#define VCO_MIN_RATE 1300000000UL 40#define VCO_MAX_RATE 2600000000UL 41 42struct dsi_pll_config { 43 u64 vco_current_rate; 44 45 u32 ssc_en; /* SSC enable/disable */ 46 47 /* fixed params */ 48 u32 plllock_cnt; 49 u32 ssc_center; 50 u32 ssc_adj_period; 51 u32 ssc_spread; 52 u32 ssc_freq; 53 54 /* calculated */ 55 u32 dec_start; 56 u32 div_frac_start; 57 u32 ssc_period; 58 u32 ssc_step_size; 59 u32 plllock_cmp; 60 u32 pll_vco_div_ref; 61 u32 pll_vco_count; 62 u32 pll_kvco_div_ref; 63 u32 pll_kvco_count; 64}; 65 66struct pll_14nm_cached_state { 67 unsigned long vco_rate; 68 u8 n2postdiv; 69 u8 n1postdiv; 70}; 71 72struct dsi_pll_14nm { 73 struct clk_hw clk_hw; 74 75 struct msm_dsi_phy *phy; 76 77 /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ 78 spinlock_t postdiv_lock; 79 80 struct pll_14nm_cached_state cached_state; 81 82 struct dsi_pll_14nm *slave; 83}; 84 85#define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw) 86 87/* 88 * Private struct for N1/N2 post-divider clocks. These clocks are similar to 89 * the generic clk_divider class of clocks. The only difference is that it 90 * also sets the slave DSI PLL's post-dividers if in bonded DSI mode 91 */ 92struct dsi_pll_14nm_postdiv { 93 struct clk_hw hw; 94 95 /* divider params */ 96 u8 shift; 97 u8 width; 98 u8 flags; /* same flags as used by clk_divider struct */ 99 100 struct dsi_pll_14nm *pll; 101}; 102 103#define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw) 104 105/* 106 * Global list of private DSI PLL struct pointers. We need this for bonded DSI 107 * mode, where the master PLL's clk_ops needs access the slave's private data 108 */ 109static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; 110 111static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, 112 u32 nb_tries, u32 timeout_us) 113{ 114 bool pll_locked = false, pll_ready = false; 115 void __iomem *base = pll_14nm->phy->pll_base; 116 u32 tries, val; 117 118 tries = nb_tries; 119 while (tries--) { 120 val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); 121 pll_locked = !!(val & BIT(5)); 122 123 if (pll_locked) 124 break; 125 126 udelay(timeout_us); 127 } 128 129 if (!pll_locked) 130 goto out; 131 132 tries = nb_tries; 133 while (tries--) { 134 val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); 135 pll_ready = !!(val & BIT(0)); 136 137 if (pll_ready) 138 break; 139 140 udelay(timeout_us); 141 } 142 143out: 144 DBG("DSI PLL is %slocked, %sready", pll_locked ? "" : "*not* ", pll_ready ? "" : "*not* "); 145 146 return pll_locked && pll_ready; 147} 148 149static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf) 150{ 151 /* fixed input */ 152 pconf->plllock_cnt = 1; 153 154 /* 155 * SSC is enabled by default. We might need DT props for configuring 156 * some SSC params like PPM and center/down spread etc. 157 */ 158 pconf->ssc_en = 1; 159 pconf->ssc_center = 0; /* down spread by default */ 160 pconf->ssc_spread = 5; /* PPM / 1000 */ 161 pconf->ssc_freq = 31500; /* default recommended */ 162 pconf->ssc_adj_period = 37; 163} 164 165#define CEIL(x, y) (((x) + ((y) - 1)) / (y)) 166 167static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 168{ 169 u32 period, ssc_period; 170 u32 ref, rem; 171 u64 step_size; 172 173 DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); 174 175 ssc_period = pconf->ssc_freq / 500; 176 period = (u32)VCO_REF_CLK_RATE / 1000; 177 ssc_period = CEIL(period, ssc_period); 178 ssc_period -= 1; 179 pconf->ssc_period = ssc_period; 180 181 DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq, 182 pconf->ssc_spread, pconf->ssc_period); 183 184 step_size = (u32)pconf->vco_current_rate; 185 ref = VCO_REF_CLK_RATE; 186 ref /= 1000; 187 step_size = div_u64(step_size, ref); 188 step_size <<= 20; 189 step_size = div_u64(step_size, 1000); 190 step_size *= pconf->ssc_spread; 191 step_size = div_u64(step_size, 1000); 192 step_size *= (pconf->ssc_adj_period + 1); 193 194 rem = 0; 195 step_size = div_u64_rem(step_size, ssc_period + 1, &rem); 196 if (rem) 197 step_size++; 198 199 DBG("step_size=%lld", step_size); 200 201 step_size &= 0x0ffff; /* take lower 16 bits */ 202 203 pconf->ssc_step_size = step_size; 204} 205 206static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 207{ 208 u64 multiplier = BIT(20); 209 u64 dec_start_multiple, dec_start, pll_comp_val; 210 u32 duration, div_frac_start; 211 u64 vco_clk_rate = pconf->vco_current_rate; 212 u64 fref = VCO_REF_CLK_RATE; 213 214 DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); 215 216 dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); 217 dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); 218 219 pconf->dec_start = (u32)dec_start; 220 pconf->div_frac_start = div_frac_start; 221 222 if (pconf->plllock_cnt == 0) 223 duration = 1024; 224 else if (pconf->plllock_cnt == 1) 225 duration = 256; 226 else if (pconf->plllock_cnt == 2) 227 duration = 128; 228 else 229 duration = 32; 230 231 pll_comp_val = duration * dec_start_multiple; 232 pll_comp_val = div_u64(pll_comp_val, multiplier); 233 do_div(pll_comp_val, 10); 234 235 pconf->plllock_cmp = (u32)pll_comp_val; 236} 237 238static u32 pll_14nm_kvco_slop(u32 vrate) 239{ 240 u32 slop = 0; 241 242 if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL) 243 slop = 600; 244 else if (vrate > 1800000000UL && vrate < 2300000000UL) 245 slop = 400; 246 else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE) 247 slop = 280; 248 249 return slop; 250} 251 252static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 253{ 254 u64 vco_clk_rate = pconf->vco_current_rate; 255 u64 fref = VCO_REF_CLK_RATE; 256 u32 vco_measure_time = 5; 257 u32 kvco_measure_time = 5; 258 u64 data; 259 u32 cnt; 260 261 data = fref * vco_measure_time; 262 do_div(data, 1000000); 263 data &= 0x03ff; /* 10 bits */ 264 data -= 2; 265 pconf->pll_vco_div_ref = data; 266 267 data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */ 268 data *= vco_measure_time; 269 do_div(data, 10); 270 pconf->pll_vco_count = data; 271 272 data = fref * kvco_measure_time; 273 do_div(data, 1000000); 274 data &= 0x03ff; /* 10 bits */ 275 data -= 1; 276 pconf->pll_kvco_div_ref = data; 277 278 cnt = pll_14nm_kvco_slop(vco_clk_rate); 279 cnt *= 2; 280 cnt /= 100; 281 cnt *= kvco_measure_time; 282 pconf->pll_kvco_count = cnt; 283} 284 285static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 286{ 287 void __iomem *base = pll->phy->pll_base; 288 u8 data; 289 290 data = pconf->ssc_adj_period; 291 data &= 0x0ff; 292 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1); 293 data = (pconf->ssc_adj_period >> 8); 294 data &= 0x03; 295 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2); 296 297 data = pconf->ssc_period; 298 data &= 0x0ff; 299 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1); 300 data = (pconf->ssc_period >> 8); 301 data &= 0x0ff; 302 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2); 303 304 data = pconf->ssc_step_size; 305 data &= 0x0ff; 306 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1); 307 data = (pconf->ssc_step_size >> 8); 308 data &= 0x0ff; 309 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2); 310 311 data = (pconf->ssc_center & 0x01); 312 data <<= 1; 313 data |= 0x01; /* enable */ 314 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER); 315 316 wmb(); /* make sure register committed */ 317} 318 319static void pll_db_commit_common(struct dsi_pll_14nm *pll, 320 struct dsi_pll_config *pconf) 321{ 322 void __iomem *base = pll->phy->pll_base; 323 u8 data; 324 325 /* confgiure the non frequency dependent pll registers */ 326 data = 0; 327 writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET); 328 329 writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN); 330 331 writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL); 332 /* bandgap_timer */ 333 writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2); 334 /* pll_wakeup_timer */ 335 writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5); 336 337 data = pconf->pll_vco_div_ref & 0xff; 338 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1); 339 data = (pconf->pll_vco_div_ref >> 8) & 0x3; 340 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2); 341 342 data = pconf->pll_kvco_div_ref & 0xff; 343 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1); 344 data = (pconf->pll_kvco_div_ref >> 8) & 0x3; 345 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2); 346 347 writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1); 348 349 writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM); 350 351 writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM); 352 353 writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR); 354 355 writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET); 356 357 writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET); 358 359 writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET); 360 361 writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1); 362 363 writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM); 364 365 writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL); 366} 367 368static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) 369{ 370 void __iomem *cmn_base = pll_14nm->phy->base; 371 372 /* de assert pll start and apply pll sw reset */ 373 374 /* stop pll */ 375 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 376 377 /* pll sw reset */ 378 writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); 379 udelay(10); 380 wmb(); /* make sure register committed */ 381 382 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); 383 wmb(); /* make sure register committed */ 384} 385 386static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, 387 struct dsi_pll_config *pconf) 388{ 389 void __iomem *base = pll->phy->pll_base; 390 void __iomem *cmn_base = pll->phy->base; 391 u8 data; 392 393 DBG("DSI%d PLL", pll->phy->id); 394 395 writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL); 396 397 pll_db_commit_common(pll, pconf); 398 399 pll_14nm_software_reset(pll); 400 401 /* Use the /2 path in Mux */ 402 writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1); 403 404 data = 0xff; /* data, clk, pll normal operation */ 405 writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0); 406 407 /* configure the frequency dependent pll registers */ 408 data = pconf->dec_start; 409 writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START); 410 411 data = pconf->div_frac_start & 0xff; 412 writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1); 413 data = (pconf->div_frac_start >> 8) & 0xff; 414 writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2); 415 data = (pconf->div_frac_start >> 16) & 0xf; 416 writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3); 417 418 data = pconf->plllock_cmp & 0xff; 419 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1); 420 421 data = (pconf->plllock_cmp >> 8) & 0xff; 422 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2); 423 424 data = (pconf->plllock_cmp >> 16) & 0x3; 425 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3); 426 427 data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */ 428 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN); 429 430 data = pconf->pll_vco_count & 0xff; 431 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1); 432 data = (pconf->pll_vco_count >> 8) & 0xff; 433 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2); 434 435 data = pconf->pll_kvco_count & 0xff; 436 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1); 437 data = (pconf->pll_kvco_count >> 8) & 0x3; 438 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2); 439 440 /* 441 * High nibble configures the post divider internal to the VCO. It's 442 * fixed to divide by 1 for now. 443 * 444 * 0: divided by 1 445 * 1: divided by 2 446 * 2: divided by 4 447 * 3: divided by 8 448 */ 449 writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV); 450 451 if (pconf->ssc_en) 452 pll_db_commit_ssc(pll, pconf); 453 454 wmb(); /* make sure register committed */ 455} 456 457/* 458 * VCO clock Callbacks 459 */ 460static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, 461 unsigned long parent_rate) 462{ 463 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 464 struct dsi_pll_config conf; 465 466 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate, 467 parent_rate); 468 469 dsi_pll_14nm_config_init(&conf); 470 conf.vco_current_rate = rate; 471 472 pll_14nm_dec_frac_calc(pll_14nm, &conf); 473 474 if (conf.ssc_en) 475 pll_14nm_ssc_calc(pll_14nm, &conf); 476 477 pll_14nm_calc_vco_count(pll_14nm, &conf); 478 479 /* commit the slave DSI PLL registers if we're master. Note that we 480 * don't lock the slave PLL. We just ensure that the PLL/PHY registers 481 * of the master and slave are identical 482 */ 483 if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { 484 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 485 486 pll_db_commit_14nm(pll_14nm_slave, &conf); 487 } 488 489 pll_db_commit_14nm(pll_14nm, &conf); 490 491 return 0; 492} 493 494static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, 495 unsigned long parent_rate) 496{ 497 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 498 void __iomem *base = pll_14nm->phy->pll_base; 499 u64 vco_rate, multiplier = BIT(20); 500 u32 div_frac_start; 501 u32 dec_start; 502 u64 ref_clk = parent_rate; 503 504 dec_start = readl(base + REG_DSI_14nm_PHY_PLL_DEC_START); 505 dec_start &= 0x0ff; 506 507 DBG("dec_start = %x", dec_start); 508 509 div_frac_start = (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) 510 & 0xf) << 16; 511 div_frac_start |= (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) 512 & 0xff) << 8; 513 div_frac_start |= readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) 514 & 0xff; 515 516 DBG("div_frac_start = %x", div_frac_start); 517 518 vco_rate = ref_clk * dec_start; 519 520 vco_rate += ((ref_clk * div_frac_start) / multiplier); 521 522 /* 523 * Recalculating the rate from dec_start and frac_start doesn't end up 524 * the rate we originally set. Convert the freq to KHz, round it up and 525 * convert it back to MHz. 526 */ 527 vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000; 528 529 DBG("returning vco rate = %lu", (unsigned long)vco_rate); 530 531 return (unsigned long)vco_rate; 532} 533 534static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) 535{ 536 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 537 void __iomem *base = pll_14nm->phy->pll_base; 538 void __iomem *cmn_base = pll_14nm->phy->base; 539 bool locked; 540 541 DBG(""); 542 543 if (unlikely(pll_14nm->phy->pll_on)) 544 return 0; 545 546 if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) 547 dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); 548 549 writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1); 550 writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 551 552 locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, 553 POLL_TIMEOUT_US); 554 555 if (unlikely(!locked)) { 556 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n"); 557 return -EINVAL; 558 } 559 560 DBG("DSI PLL lock success"); 561 pll_14nm->phy->pll_on = true; 562 563 return 0; 564} 565 566static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) 567{ 568 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 569 void __iomem *cmn_base = pll_14nm->phy->base; 570 571 DBG(""); 572 573 if (unlikely(!pll_14nm->phy->pll_on)) 574 return; 575 576 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 577 578 pll_14nm->phy->pll_on = false; 579} 580 581static int dsi_pll_14nm_clk_determine_rate(struct clk_hw *hw, 582 struct clk_rate_request *req) 583{ 584 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 585 586 req->rate = clamp_t(unsigned long, req->rate, 587 pll_14nm->phy->cfg->min_pll_rate, pll_14nm->phy->cfg->max_pll_rate); 588 589 return 0; 590} 591 592static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { 593 .determine_rate = dsi_pll_14nm_clk_determine_rate, 594 .set_rate = dsi_pll_14nm_vco_set_rate, 595 .recalc_rate = dsi_pll_14nm_vco_recalc_rate, 596 .prepare = dsi_pll_14nm_vco_prepare, 597 .unprepare = dsi_pll_14nm_vco_unprepare, 598}; 599 600/* 601 * N1 and N2 post-divider clock callbacks 602 */ 603#define div_mask(width) ((1 << (width)) - 1) 604static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, 605 unsigned long parent_rate) 606{ 607 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 608 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 609 void __iomem *base = pll_14nm->phy->base; 610 u8 shift = postdiv->shift; 611 u8 width = postdiv->width; 612 u32 val; 613 614 DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate); 615 616 val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; 617 val &= div_mask(width); 618 619 return divider_recalc_rate(hw, parent_rate, val, NULL, 620 postdiv->flags, width); 621} 622 623static int dsi_pll_14nm_postdiv_determine_rate(struct clk_hw *hw, 624 struct clk_rate_request *req) 625{ 626 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 627 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 628 629 DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, req->rate); 630 631 return divider_determine_rate(hw, req, NULL, postdiv->width, postdiv->flags); 632} 633 634static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 635 unsigned long parent_rate) 636{ 637 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 638 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 639 void __iomem *base = pll_14nm->phy->base; 640 spinlock_t *lock = &pll_14nm->postdiv_lock; 641 u8 shift = postdiv->shift; 642 u8 width = postdiv->width; 643 unsigned int value; 644 unsigned long flags = 0; 645 u32 val; 646 647 DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate, 648 parent_rate); 649 650 value = divider_get_val(rate, parent_rate, NULL, postdiv->width, 651 postdiv->flags); 652 653 spin_lock_irqsave(lock, flags); 654 655 val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 656 val &= ~(div_mask(width) << shift); 657 658 val |= value << shift; 659 writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 660 661 /* If we're master in bonded DSI mode, then the slave PLL's post-dividers 662 * follow the master's post dividers 663 */ 664 if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { 665 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 666 void __iomem *slave_base = pll_14nm_slave->phy->base; 667 668 writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 669 } 670 671 spin_unlock_irqrestore(lock, flags); 672 673 return 0; 674} 675 676static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { 677 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, 678 .determine_rate = dsi_pll_14nm_postdiv_determine_rate, 679 .set_rate = dsi_pll_14nm_postdiv_set_rate, 680}; 681 682/* 683 * PLL Callbacks 684 */ 685 686static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy) 687{ 688 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 689 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; 690 void __iomem *cmn_base = pll_14nm->phy->base; 691 u32 data; 692 693 data = readl(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 694 695 cached_state->n1postdiv = data & 0xf; 696 cached_state->n2postdiv = (data >> 4) & 0xf; 697 698 DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id, 699 cached_state->n1postdiv, cached_state->n2postdiv); 700 701 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); 702} 703 704static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) 705{ 706 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 707 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; 708 void __iomem *cmn_base = pll_14nm->phy->base; 709 u32 data; 710 int ret; 711 712 ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw, 713 cached_state->vco_rate, 0); 714 if (ret) { 715 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, 716 "restore vco rate failed. ret=%d\n", ret); 717 return ret; 718 } 719 720 data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); 721 722 DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id, 723 cached_state->n1postdiv, cached_state->n2postdiv); 724 725 writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 726 727 /* also restore post-dividers for slave DSI PLL */ 728 if (phy->usecase == MSM_DSI_PHY_MASTER) { 729 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 730 void __iomem *slave_base = pll_14nm_slave->phy->base; 731 732 writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 733 } 734 735 return 0; 736} 737 738static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) 739{ 740 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 741 void __iomem *base = phy->pll_base; 742 u32 clkbuflr_en, bandgap = 0; 743 744 switch (phy->usecase) { 745 case MSM_DSI_PHY_STANDALONE: 746 clkbuflr_en = 0x1; 747 break; 748 case MSM_DSI_PHY_MASTER: 749 clkbuflr_en = 0x3; 750 pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX]; 751 break; 752 case MSM_DSI_PHY_SLAVE: 753 clkbuflr_en = 0x0; 754 bandgap = 0x3; 755 break; 756 default: 757 return -EINVAL; 758 } 759 760 writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN); 761 if (bandgap) 762 writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP); 763 764 return 0; 765} 766 767static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, 768 const char *name, 769 const struct clk_hw *parent_hw, 770 unsigned long flags, 771 u8 shift) 772{ 773 struct dsi_pll_14nm_postdiv *pll_postdiv; 774 struct device *dev = &pll_14nm->phy->pdev->dev; 775 struct clk_init_data postdiv_init = { 776 .parent_hws = (const struct clk_hw *[]) { parent_hw }, 777 .num_parents = 1, 778 .name = name, 779 .flags = flags, 780 .ops = &clk_ops_dsi_pll_14nm_postdiv, 781 }; 782 int ret; 783 784 pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL); 785 if (!pll_postdiv) 786 return ERR_PTR(-ENOMEM); 787 788 pll_postdiv->pll = pll_14nm; 789 pll_postdiv->shift = shift; 790 /* both N1 and N2 postdividers are 4 bits wide */ 791 pll_postdiv->width = 4; 792 /* range of each divider is from 1 to 15 */ 793 pll_postdiv->flags = CLK_DIVIDER_ONE_BASED; 794 pll_postdiv->hw.init = &postdiv_init; 795 796 ret = devm_clk_hw_register(dev, &pll_postdiv->hw); 797 if (ret) 798 return ERR_PTR(ret); 799 800 return &pll_postdiv->hw; 801} 802 803static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks) 804{ 805 char clk_name[32]; 806 struct clk_init_data vco_init = { 807 .parent_data = &(const struct clk_parent_data) { 808 .fw_name = "ref", 809 }, 810 .num_parents = 1, 811 .name = clk_name, 812 .flags = CLK_IGNORE_UNUSED, 813 .ops = &clk_ops_dsi_pll_14nm_vco, 814 }; 815 struct device *dev = &pll_14nm->phy->pdev->dev; 816 struct clk_hw *hw, *n1_postdiv, *n1_postdivby2; 817 int ret; 818 819 DBG("DSI%d", pll_14nm->phy->id); 820 821 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id); 822 pll_14nm->clk_hw.init = &vco_init; 823 824 ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw); 825 if (ret) 826 return ret; 827 828 snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", pll_14nm->phy->id); 829 830 /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ 831 n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name, 832 &pll_14nm->clk_hw, CLK_SET_RATE_PARENT, 0); 833 if (IS_ERR(n1_postdiv)) 834 return PTR_ERR(n1_postdiv); 835 836 snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id); 837 838 /* DSI Byte clock = VCO_CLK / N1 / 8 */ 839 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, 840 n1_postdiv, CLK_SET_RATE_PARENT, 1, 8); 841 if (IS_ERR(hw)) 842 return PTR_ERR(hw); 843 844 provided_clocks[DSI_BYTE_PLL_CLK] = hw; 845 846 snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); 847 848 /* 849 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider 850 * on the way. Don't let it set parent. 851 */ 852 n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev, 853 clk_name, n1_postdiv, 0, 1, 2); 854 if (IS_ERR(n1_postdivby2)) 855 return PTR_ERR(n1_postdivby2); 856 857 snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id); 858 859 /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 860 * This is the output of N2 post-divider, bits 4-7 in 861 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent. 862 */ 863 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, n1_postdivby2, 864 0, 4); 865 if (IS_ERR(hw)) 866 return PTR_ERR(hw); 867 868 provided_clocks[DSI_PIXEL_PLL_CLK] = hw; 869 870 return 0; 871} 872 873static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) 874{ 875 struct platform_device *pdev = phy->pdev; 876 struct dsi_pll_14nm *pll_14nm; 877 int ret; 878 879 if (!pdev) 880 return -ENODEV; 881 882 pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); 883 if (!pll_14nm) 884 return -ENOMEM; 885 886 DBG("PLL%d", phy->id); 887 888 pll_14nm_list[phy->id] = pll_14nm; 889 890 spin_lock_init(&pll_14nm->postdiv_lock); 891 892 pll_14nm->phy = phy; 893 894 ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); 895 if (ret) { 896 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); 897 return ret; 898 } 899 900 phy->vco_hw = &pll_14nm->clk_hw; 901 902 return 0; 903} 904 905static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, 906 struct msm_dsi_dphy_timing *timing, 907 int lane_idx) 908{ 909 void __iomem *base = phy->lane_base; 910 bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX); 911 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; 912 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; 913 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; 914 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; 915 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; 916 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : 917 timing->hs_halfbyte_en; 918 919 writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), 920 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx)); 921 writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero), 922 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx)); 923 writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare), 924 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx)); 925 writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail), 926 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx)); 927 writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst), 928 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx)); 929 writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly), 930 base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx)); 931 writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0, 932 base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx)); 933 writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | 934 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure), 935 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx)); 936 writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get), 937 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx)); 938 writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0), 939 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx)); 940} 941 942static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, 943 struct msm_dsi_phy_clk_request *clk_req) 944{ 945 struct msm_dsi_dphy_timing *timing = &phy->timing; 946 u32 data; 947 int i; 948 int ret; 949 void __iomem *base = phy->base; 950 void __iomem *lane_base = phy->lane_base; 951 u32 glbl_test_ctrl; 952 953 if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { 954 DRM_DEV_ERROR(&phy->pdev->dev, 955 "%s: D-PHY timing calculation failed\n", 956 __func__); 957 return -EINVAL; 958 } 959 960 data = 0x1c; 961 if (phy->usecase != MSM_DSI_PHY_STANDALONE) 962 data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32); 963 writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL); 964 965 writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 966 967 /* 4 data lanes + 1 clk lane configuration */ 968 for (i = 0; i < 5; i++) { 969 writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i)); 970 971 writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i)); 972 writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06, 973 lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i)); 974 975 writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f, 976 lane_base + REG_DSI_14nm_PHY_LN_CFG3(i)); 977 writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i)); 978 writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i)); 979 writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i)); 980 981 dsi_14nm_dphy_set_timing(phy, timing, i); 982 } 983 984 /* Make sure PLL is not start */ 985 writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 986 987 wmb(); /* make sure everything is written before reset and enable */ 988 989 /* reset digital block */ 990 writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1); 991 wmb(); /* ensure reset is asserted */ 992 udelay(100); 993 writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1); 994 995 glbl_test_ctrl = readl(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 996 if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE) 997 glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; 998 else 999 glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; 1000 writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 1001 ret = dsi_14nm_set_usecase(phy); 1002 if (ret) { 1003 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", 1004 __func__, ret); 1005 return ret; 1006 } 1007 1008 /* Remove power down from PLL and all lanes */ 1009 writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0); 1010 1011 return 0; 1012} 1013 1014static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) 1015{ 1016 writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 1017 writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0); 1018 1019 /* ensure that the phy is completely disabled */ 1020 wmb(); 1021} 1022 1023static const struct regulator_bulk_data dsi_phy_14nm_17mA_regulators[] = { 1024 { .supply = "vcca", .init_load_uA = 17000 }, 1025}; 1026 1027static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = { 1028 { .supply = "vcca", .init_load_uA = 73400 }, 1029}; 1030 1031static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = { 1032 { .supply = "vdda", .init_load_uA = 36000 }, 1033}; 1034 1035const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 1036 .has_phy_lane = true, 1037 .regulator_data = dsi_phy_14nm_17mA_regulators, 1038 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), 1039 .ops = { 1040 .enable = dsi_14nm_phy_enable, 1041 .disable = dsi_14nm_phy_disable, 1042 .pll_init = dsi_pll_14nm_init, 1043 .save_pll_state = dsi_14nm_pll_save_state, 1044 .restore_pll_state = dsi_14nm_pll_restore_state, 1045 }, 1046 .min_pll_rate = VCO_MIN_RATE, 1047 .max_pll_rate = VCO_MAX_RATE, 1048 .io_start = { 0x994400, 0x996400 }, 1049 .num_dsi_phy = 2, 1050}; 1051 1052const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { 1053 .has_phy_lane = true, 1054 .regulator_data = dsi_phy_14nm_73p4mA_regulators, 1055 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_73p4mA_regulators), 1056 .ops = { 1057 .enable = dsi_14nm_phy_enable, 1058 .disable = dsi_14nm_phy_disable, 1059 .pll_init = dsi_pll_14nm_init, 1060 .save_pll_state = dsi_14nm_pll_save_state, 1061 .restore_pll_state = dsi_14nm_pll_restore_state, 1062 }, 1063 .min_pll_rate = VCO_MIN_RATE, 1064 .max_pll_rate = VCO_MAX_RATE, 1065 .io_start = { 0xc994400, 0xc996400 }, 1066 .num_dsi_phy = 2, 1067}; 1068 1069const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { 1070 .has_phy_lane = true, 1071 .regulator_data = dsi_phy_14nm_17mA_regulators, 1072 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), 1073 .ops = { 1074 .enable = dsi_14nm_phy_enable, 1075 .disable = dsi_14nm_phy_disable, 1076 .pll_init = dsi_pll_14nm_init, 1077 .save_pll_state = dsi_14nm_pll_save_state, 1078 .restore_pll_state = dsi_14nm_pll_restore_state, 1079 }, 1080 .min_pll_rate = VCO_MIN_RATE, 1081 .max_pll_rate = VCO_MAX_RATE, 1082 .io_start = { 0x1a94400, 0x1a96400 }, 1083 .num_dsi_phy = 2, 1084}; 1085 1086const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { 1087 .has_phy_lane = true, 1088 .ops = { 1089 .enable = dsi_14nm_phy_enable, 1090 .disable = dsi_14nm_phy_disable, 1091 .pll_init = dsi_pll_14nm_init, 1092 .save_pll_state = dsi_14nm_pll_save_state, 1093 .restore_pll_state = dsi_14nm_pll_restore_state, 1094 }, 1095 .min_pll_rate = VCO_MIN_RATE, 1096 .max_pll_rate = VCO_MAX_RATE, 1097 .io_start = { 0x5e94400 }, 1098 .num_dsi_phy = 1, 1099}; 1100 1101const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs = { 1102 .has_phy_lane = true, 1103 .regulator_data = dsi_phy_14nm_36mA_regulators, 1104 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators), 1105 .ops = { 1106 .enable = dsi_14nm_phy_enable, 1107 .disable = dsi_14nm_phy_disable, 1108 .pll_init = dsi_pll_14nm_init, 1109 .save_pll_state = dsi_14nm_pll_save_state, 1110 .restore_pll_state = dsi_14nm_pll_restore_state, 1111 }, 1112 .min_pll_rate = VCO_MIN_RATE, 1113 .max_pll_rate = VCO_MAX_RATE, 1114 .io_start = { 0xae94400 }, 1115 .num_dsi_phy = 1, 1116};
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