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dsi_host.c
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linux-6.19.14/drivers/gpu/drm/msm/dsi/dsi_host.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/dma-mapping.h> 9#include <linux/err.h> 10#include <linux/interrupt.h> 11#include <linux/mfd/syscon.h> 12#include <linux/of.h> 13#include <linux/of_graph.h> 14#include <linux/of_irq.h> 15#include <linux/pinctrl/consumer.h> 16#include <linux/pm_opp.h> 17#include <linux/regmap.h> 18#include <linux/regulator/consumer.h> 19#include <linux/spinlock.h> 20 21#include <video/mipi_display.h> 22 23#include <drm/display/drm_dsc_helper.h> 24#include <drm/drm_of.h> 25 26#include "dsi.h" 27#include "dsi.xml.h" 28#include "sfpb.xml.h" 29#include "dsi_cfg.h" 30#include "msm_dsc_helper.h" 31#include "msm_kms.h" 32#include "msm_gem.h" 33#include "phy/dsi_phy.h" 34 35#define DSI_RESET_TOGGLE_DELAY_MS 20 36 37static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40{ 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86} 87 88#define DSI_ERR_STATE_ACK 0x0000 89#define DSI_ERR_STATE_TIMEOUT 0x0001 90#define DSI_ERR_STATE_DLN0_PHY 0x0002 91#define DSI_ERR_STATE_FIFO 0x0004 92#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96#define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_intf_clk; 121 122 /* 123 * Clocks which needs to be properly parented between DISPCC and DSI PHY 124 * PLL: 125 */ 126 struct clk *byte_src_clk; 127 struct clk *pixel_src_clk; 128 struct clk *dsi_pll_byte_clk; 129 struct clk *dsi_pll_pixel_clk; 130 131 unsigned long byte_clk_rate; 132 unsigned long byte_intf_clk_rate; 133 unsigned long pixel_clk_rate; 134 unsigned long esc_clk_rate; 135 136 /* DSI v2 specific clocks */ 137 struct clk *src_clk; 138 139 unsigned long src_clk_rate; 140 141 const struct msm_dsi_cfg_handler *cfg_hnd; 142 143 struct completion dma_comp; 144 struct completion video_comp; 145 struct mutex dev_mutex; 146 struct mutex cmd_mutex; 147 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 148 149 u32 err_work_state; 150 struct work_struct err_work; 151 struct workqueue_struct *workqueue; 152 153 /* DSI 6G TX buffer*/ 154 struct drm_gem_object *tx_gem_obj; 155 struct drm_gpuvm *vm; 156 157 /* DSI v2 TX buffer */ 158 void *tx_buf; 159 dma_addr_t tx_buf_paddr; 160 161 int tx_size; 162 163 u8 *rx_buf; 164 165 struct regmap *sfpb; 166 167 struct drm_display_mode *mode; 168 struct drm_dsc_config *dsc; 169 170 /* connected device info */ 171 unsigned int channel; 172 unsigned int lanes; 173 enum mipi_dsi_pixel_format format; 174 unsigned long mode_flags; 175 176 /* lane data parsed via DT */ 177 int dlane_swap; 178 int num_data_lanes; 179 180 /* from phy DT */ 181 bool cphy_mode; 182 183 u32 dma_cmd_ctrl_restore; 184 185 bool registered; 186 bool power_on; 187 bool enabled; 188 int irq; 189}; 190 191static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 192{ 193 return readl(msm_host->ctrl_base + reg); 194} 195 196static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 197{ 198 writel(data, msm_host->ctrl_base + reg); 199} 200 201static const struct msm_dsi_cfg_handler * 202dsi_get_config(struct msm_dsi_host *msm_host) 203{ 204 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 205 struct device *dev = &msm_host->pdev->dev; 206 struct clk *ahb_clk; 207 int ret; 208 u32 major = 0, minor = 0; 209 210 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 211 if (IS_ERR(ahb_clk)) { 212 dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", 213 __func__); 214 goto exit; 215 } 216 217 pm_runtime_get_sync(dev); 218 219 ret = clk_prepare_enable(ahb_clk); 220 if (ret) { 221 dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); 222 goto runtime_put; 223 } 224 225 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 226 if (ret) { 227 dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); 228 goto disable_clks; 229 } 230 231 cfg_hnd = msm_dsi_cfg_get(major, minor); 232 233 DBG("%s: Version %x:%x\n", __func__, major, minor); 234 235disable_clks: 236 clk_disable_unprepare(ahb_clk); 237runtime_put: 238 pm_runtime_put_sync(dev); 239exit: 240 return cfg_hnd; 241} 242 243static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 244{ 245 return container_of(host, struct msm_dsi_host, base); 246} 247 248int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 249{ 250 struct platform_device *pdev = msm_host->pdev; 251 int ret = 0; 252 253 msm_host->src_clk = msm_clk_get(pdev, "src"); 254 255 if (IS_ERR(msm_host->src_clk)) { 256 ret = PTR_ERR(msm_host->src_clk); 257 pr_err("%s: can't find src clock. ret=%d\n", 258 __func__, ret); 259 msm_host->src_clk = NULL; 260 return ret; 261 } 262 263 return ret; 264} 265 266int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 267{ 268 struct platform_device *pdev = msm_host->pdev; 269 int ret = 0; 270 271 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 272 if (IS_ERR(msm_host->byte_intf_clk)) { 273 ret = PTR_ERR(msm_host->byte_intf_clk); 274 pr_err("%s: can't find byte_intf clock. ret=%d\n", 275 __func__, ret); 276 } 277 278 return ret; 279} 280 281int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) 282{ 283 struct device *dev = &msm_host->pdev->dev; 284 int ret; 285 286 ret = dsi_clk_init_6g_v2(msm_host); 287 if (ret) 288 return ret; 289 290 msm_host->byte_src_clk = devm_clk_get(dev, "byte_src"); 291 if (IS_ERR(msm_host->byte_src_clk)) 292 return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), 293 "can't get byte_src clock\n"); 294 295 msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte"); 296 if (IS_ERR(msm_host->dsi_pll_byte_clk)) 297 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), 298 "can't get dsi_pll_byte clock\n"); 299 300 msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src"); 301 if (IS_ERR(msm_host->pixel_src_clk)) 302 return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), 303 "can't get pixel_src clock\n"); 304 305 msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel"); 306 if (IS_ERR(msm_host->dsi_pll_pixel_clk)) 307 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), 308 "can't get dsi_pll_pixel clock\n"); 309 310 return 0; 311} 312 313static int dsi_clk_init(struct msm_dsi_host *msm_host) 314{ 315 struct platform_device *pdev = msm_host->pdev; 316 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 317 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 318 int i, ret = 0; 319 320 /* get bus clocks */ 321 for (i = 0; i < cfg->num_bus_clks; i++) 322 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 323 msm_host->num_bus_clks = cfg->num_bus_clks; 324 325 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 326 if (ret < 0) 327 return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); 328 329 /* get link and source clocks */ 330 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 331 if (IS_ERR(msm_host->byte_clk)) 332 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), 333 "%s: can't find dsi_byte clock\n", 334 __func__); 335 336 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 337 if (IS_ERR(msm_host->pixel_clk)) 338 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), 339 "%s: can't find dsi_pixel clock\n", 340 __func__); 341 342 msm_host->esc_clk = msm_clk_get(pdev, "core"); 343 if (IS_ERR(msm_host->esc_clk)) 344 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), 345 "%s: can't find dsi_esc clock\n", 346 __func__); 347 348 if (cfg_hnd->ops->clk_init_ver) 349 ret = cfg_hnd->ops->clk_init_ver(msm_host); 350 351 return ret; 352} 353 354int msm_dsi_runtime_suspend(struct device *dev) 355{ 356 struct platform_device *pdev = to_platform_device(dev); 357 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 358 struct mipi_dsi_host *host = msm_dsi->host; 359 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 360 361 if (!msm_host->cfg_hnd) 362 return 0; 363 364 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 365 366 return 0; 367} 368 369int msm_dsi_runtime_resume(struct device *dev) 370{ 371 struct platform_device *pdev = to_platform_device(dev); 372 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 373 struct mipi_dsi_host *host = msm_dsi->host; 374 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 375 376 if (!msm_host->cfg_hnd) 377 return 0; 378 379 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 380} 381 382int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 383{ 384 int ret; 385 386 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 387 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 388 389 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 390 msm_host->byte_clk_rate); 391 if (ret) { 392 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 393 return ret; 394 } 395 396 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 397 if (ret) { 398 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 399 return ret; 400 } 401 402 if (msm_host->byte_intf_clk) { 403 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 404 if (ret) { 405 pr_err("%s: Failed to set rate byte intf clk, %d\n", 406 __func__, ret); 407 return ret; 408 } 409 } 410 411 return 0; 412} 413 414int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) 415{ 416 struct device *dev = &msm_host->pdev->dev; 417 int ret; 418 419 /* 420 * DSI PHY PLLs have to be enabled to allow reparenting to them, so 421 * cannot use assigned-clock-parents. 422 */ 423 ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk); 424 if (ret) 425 dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); 426 427 ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk); 428 if (ret) 429 dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); 430 431 return dsi_link_clk_set_rate_6g(msm_host); 432} 433 434int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 435{ 436 int ret; 437 438 ret = clk_prepare_enable(msm_host->esc_clk); 439 if (ret) { 440 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 441 goto error; 442 } 443 444 ret = clk_prepare_enable(msm_host->byte_clk); 445 if (ret) { 446 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 447 goto byte_clk_err; 448 } 449 450 ret = clk_prepare_enable(msm_host->pixel_clk); 451 if (ret) { 452 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 453 goto pixel_clk_err; 454 } 455 456 ret = clk_prepare_enable(msm_host->byte_intf_clk); 457 if (ret) { 458 pr_err("%s: Failed to enable byte intf clk\n", 459 __func__); 460 goto byte_intf_clk_err; 461 } 462 463 return 0; 464 465byte_intf_clk_err: 466 clk_disable_unprepare(msm_host->pixel_clk); 467pixel_clk_err: 468 clk_disable_unprepare(msm_host->byte_clk); 469byte_clk_err: 470 clk_disable_unprepare(msm_host->esc_clk); 471error: 472 return ret; 473} 474 475int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 476{ 477 int ret; 478 479 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 480 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 481 msm_host->esc_clk_rate, msm_host->src_clk_rate); 482 483 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 484 if (ret) { 485 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 486 return ret; 487 } 488 489 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 490 if (ret) { 491 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 492 return ret; 493 } 494 495 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 496 if (ret) { 497 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 498 return ret; 499 } 500 501 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 502 if (ret) { 503 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 504 return ret; 505 } 506 507 return 0; 508} 509 510int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 511{ 512 int ret; 513 514 ret = clk_prepare_enable(msm_host->byte_clk); 515 if (ret) { 516 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 517 goto error; 518 } 519 520 ret = clk_prepare_enable(msm_host->esc_clk); 521 if (ret) { 522 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 523 goto esc_clk_err; 524 } 525 526 ret = clk_prepare_enable(msm_host->src_clk); 527 if (ret) { 528 pr_err("%s: Failed to enable dsi src clk\n", __func__); 529 goto src_clk_err; 530 } 531 532 ret = clk_prepare_enable(msm_host->pixel_clk); 533 if (ret) { 534 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 535 goto pixel_clk_err; 536 } 537 538 return 0; 539 540pixel_clk_err: 541 clk_disable_unprepare(msm_host->src_clk); 542src_clk_err: 543 clk_disable_unprepare(msm_host->esc_clk); 544esc_clk_err: 545 clk_disable_unprepare(msm_host->byte_clk); 546error: 547 return ret; 548} 549 550void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 551{ 552 /* Drop the performance state vote */ 553 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 554 clk_disable_unprepare(msm_host->esc_clk); 555 clk_disable_unprepare(msm_host->pixel_clk); 556 clk_disable_unprepare(msm_host->byte_intf_clk); 557 clk_disable_unprepare(msm_host->byte_clk); 558} 559 560void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 561{ 562 clk_disable_unprepare(msm_host->pixel_clk); 563 clk_disable_unprepare(msm_host->src_clk); 564 clk_disable_unprepare(msm_host->esc_clk); 565 clk_disable_unprepare(msm_host->byte_clk); 566} 567 568/** 569 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 570 * @mode: The selected mode for the DSI output 571 * @dsc: DRM DSC configuration for this DSI output 572 * 573 * Adjust the pclk rate by calculating a new hdisplay proportional to 574 * the compression ratio such that: 575 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 576 * 577 * Porches do not need to be adjusted: 578 * - For VIDEO mode they are not compressed by DSC and are passed as is. 579 * - For CMD mode there are no actual porches. Instead these fields 580 * currently represent the overhead to the image data transfer. As such, they 581 * are calculated for the final mode parameters (after the compression) and 582 * are not to be adjusted too. 583 * 584 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 585 * transfer time and data overhead as a starting point of the calculations. 586 */ 587static unsigned long 588dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 589 const struct drm_dsc_config *dsc, 590 bool is_bonded_dsi) 591{ 592 int hdisplay, new_hdisplay, new_htotal; 593 594 /* 595 * For bonded DSI, split hdisplay across two links and round up each 596 * half separately, passing the full hdisplay would only round up once. 597 * This also aligns with the hdisplay we program later in 598 * dsi_timing_setup() 599 */ 600 hdisplay = mode->hdisplay; 601 if (is_bonded_dsi) 602 hdisplay /= 2; 603 604 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), 605 dsc->bits_per_component * 3); 606 607 if (is_bonded_dsi) 608 new_hdisplay *= 2; 609 610 new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 611 612 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); 613} 614 615static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 616 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 617{ 618 unsigned long pclk_rate; 619 620 pclk_rate = mode->clock * 1000u; 621 622 if (dsc) 623 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); 624 625 /* 626 * For bonded DSI mode, the current DRM mode has the complete width of the 627 * panel. Since, the complete panel is driven by two DSI controllers, 628 * the clock rates have to be split between the two dsi controllers. 629 * Adjust the byte and pixel clock rates for each dsi host accordingly. 630 */ 631 if (is_bonded_dsi) 632 pclk_rate /= 2; 633 634 return pclk_rate; 635} 636 637unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 638 const struct drm_display_mode *mode) 639{ 640 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 641 u8 lanes = msm_host->lanes; 642 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 643 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 644 unsigned long pclk_bpp; 645 646 if (lanes == 0) { 647 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 648 lanes = 1; 649 } 650 651 /* CPHY "byte_clk" is in units of 16 bits */ 652 if (msm_host->cphy_mode) 653 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 654 else 655 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 656 657 return pclk_bpp; 658} 659 660static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 661{ 662 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 663 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 664 msm_host->mode); 665 666 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 667 msm_host->byte_clk_rate); 668} 669 670int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 671{ 672 if (!msm_host->mode) { 673 pr_err("%s: mode not set\n", __func__); 674 return -EINVAL; 675 } 676 677 dsi_calc_pclk(msm_host, is_bonded_dsi); 678 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 679 return 0; 680} 681 682int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 683{ 684 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 685 unsigned int esc_mhz, esc_div; 686 unsigned long byte_mhz; 687 688 dsi_calc_pclk(msm_host, is_bonded_dsi); 689 690 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 691 692 /* 693 * esc clock is byte clock followed by a 4 bit divider, 694 * we need to find an escape clock frequency within the 695 * mipi DSI spec range within the maximum divider limit 696 * We iterate here between an escape clock frequencey 697 * between 20 Mhz to 5 Mhz and pick up the first one 698 * that can be supported by our divider 699 */ 700 701 byte_mhz = msm_host->byte_clk_rate / 1000000; 702 703 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 704 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 705 706 /* 707 * TODO: Ideally, we shouldn't know what sort of divider 708 * is available in mmss_cc, we're just assuming that 709 * it'll always be a 4 bit divider. Need to come up with 710 * a better way here. 711 */ 712 if (esc_div >= 1 && esc_div <= 16) 713 break; 714 } 715 716 if (esc_mhz < 5) 717 return -EINVAL; 718 719 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 720 721 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 722 msm_host->src_clk_rate); 723 724 return 0; 725} 726 727static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 728{ 729 u32 intr; 730 unsigned long flags; 731 732 spin_lock_irqsave(&msm_host->intr_lock, flags); 733 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 734 735 if (enable) 736 intr |= mask; 737 else 738 intr &= ~mask; 739 740 DBG("intr=%x enable=%d", intr, enable); 741 742 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 743 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 744} 745 746static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 747{ 748 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 749 return BURST_MODE; 750 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 751 return NON_BURST_SYNCH_PULSE; 752 753 return NON_BURST_SYNCH_EVENT; 754} 755 756static inline enum dsi_vid_dst_format 757dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 758{ 759 switch (mipi_fmt) { 760 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 761 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 762 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 763 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 764 default: return VID_DST_FORMAT_RGB888; 765 } 766} 767 768static inline enum dsi_cmd_dst_format 769dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 770{ 771 switch (mipi_fmt) { 772 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 773 case MIPI_DSI_FMT_RGB666_PACKED: 774 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 775 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 776 default: return CMD_DST_FORMAT_RGB888; 777 } 778} 779 780static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 781{ 782 dsi_write(msm_host, REG_DSI_CTRL, 0); 783} 784 785bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 786{ 787 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 788 789 return msm_host->dsc && 790 (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && 791 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); 792} 793 794static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 795 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 796{ 797 u32 flags = msm_host->mode_flags; 798 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 799 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 800 u32 data = 0, lane_ctrl = 0; 801 802 if (flags & MIPI_DSI_MODE_VIDEO) { 803 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 804 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 805 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 806 data |= DSI_VID_CFG0_HFP_POWER_STOP; 807 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 808 data |= DSI_VID_CFG0_HBP_POWER_STOP; 809 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 810 data |= DSI_VID_CFG0_HSA_POWER_STOP; 811 /* Always set low power stop mode for BLLP 812 * to let command engine send packets 813 */ 814 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 815 DSI_VID_CFG0_BLLP_POWER_STOP; 816 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 817 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 818 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 819 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 820 data |= DSI_VID_CFG0_DATABUS_WIDEN; 821 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 822 823 /* Do not swap RGB colors */ 824 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 825 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 826 } else { 827 /* Do not swap RGB colors */ 828 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 829 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 830 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 831 832 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 833 DSI_CMD_CFG1_WR_MEM_CONTINUE( 834 MIPI_DCS_WRITE_MEMORY_CONTINUE); 835 /* Always insert DCS command */ 836 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 837 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 838 839 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 840 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 841 842 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 843 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 844 845 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 846 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 847 848 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 849 } 850 } 851 852 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 853 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 854 DSI_CMD_DMA_CTRL_LOW_POWER); 855 856 data = 0; 857 /* Always assume dedicated TE pin */ 858 data |= DSI_TRIG_CTRL_TE; 859 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 860 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 861 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 862 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 863 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 864 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 865 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 866 867 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 868 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 869 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 870 871 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 872 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 873 phy_shared_timings->clk_pre_inc_by_2) 874 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 875 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 876 877 data = 0; 878 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 879 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 880 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 881 882 /* allow only ack-err-status to generate interrupt */ 883 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 884 885 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 886 887 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 888 889 data = DSI_CTRL_CLK_EN; 890 891 DBG("lane number=%d", msm_host->lanes); 892 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 893 894 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 895 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 896 897 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 898 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 899 900 if (msm_dsi_phy_set_continuous_clock(phy, true)) 901 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 902 903 dsi_write(msm_host, REG_DSI_LANE_CTRL, 904 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 905 } 906 907 data |= DSI_CTRL_ENABLE; 908 909 dsi_write(msm_host, REG_DSI_CTRL, data); 910 911 if (msm_host->cphy_mode) 912 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 913} 914 915static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) 916{ 917 struct drm_dsc_config *dsc = msm_host->dsc; 918 u32 reg, reg_ctrl, reg_ctrl2; 919 u32 slice_per_intf, total_bytes_per_intf; 920 u32 pkt_per_line; 921 u32 eol_byte_num; 922 u32 bytes_per_pkt; 923 924 /* first calculate dsc parameters and then program 925 * compress mode registers 926 */ 927 slice_per_intf = dsc->slice_count; 928 929 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 930 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ 931 932 eol_byte_num = total_bytes_per_intf % 3; 933 934 /* 935 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. 936 * 937 * Since the current driver only supports slice_per_pkt = 1, 938 * pkt_per_line will be equal to slice per intf for now. 939 */ 940 pkt_per_line = slice_per_intf; 941 942 if (is_cmd_mode) /* packet data type */ 943 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 944 else 945 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 946 947 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 948 * registers have similar offsets, so for below common code use 949 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 950 * 951 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 952 */ 953 if (pkt_per_line > 4) 954 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 955 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 956 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 957 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 958 959 if (is_cmd_mode) { 960 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 961 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 962 963 reg_ctrl &= ~0xffff; 964 reg_ctrl |= reg; 965 966 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 967 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 968 969 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 970 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 971 } else { 972 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 973 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 974 } 975} 976 977static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 978{ 979 struct drm_display_mode *mode = msm_host->mode; 980 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 981 u32 h_total = mode->htotal; 982 u32 v_total = mode->vtotal; 983 u32 hs_end = mode->hsync_end - mode->hsync_start; 984 u32 vs_end = mode->vsync_end - mode->vsync_start; 985 u32 ha_start = h_total - mode->hsync_start; 986 u32 ha_end = ha_start + mode->hdisplay; 987 u32 va_start = v_total - mode->vsync_start; 988 u32 va_end = va_start + mode->vdisplay; 989 u32 hdisplay = mode->hdisplay; 990 u32 wc; 991 int ret; 992 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 993 994 DBG(""); 995 996 /* 997 * For bonded DSI mode, the current DRM mode has 998 * the complete width of the panel. Since, the complete 999 * panel is driven by two DSI controllers, the horizontal 1000 * timings have to be split between the two dsi controllers. 1001 * Adjust the DSI host timing values accordingly. 1002 */ 1003 if (is_bonded_dsi) { 1004 h_total /= 2; 1005 hs_end /= 2; 1006 ha_start /= 2; 1007 ha_end /= 2; 1008 hdisplay /= 2; 1009 } 1010 1011 if (msm_host->dsc) { 1012 struct drm_dsc_config *dsc = msm_host->dsc; 1013 u32 bits_per_pclk; 1014 1015 /* update dsc params with timing params */ 1016 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 1017 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 1018 mode->hdisplay, mode->vdisplay); 1019 return; 1020 } 1021 1022 dsc->pic_width = mode->hdisplay; 1023 dsc->pic_height = mode->vdisplay; 1024 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 1025 1026 /* we do the calculations for dsc parameters here so that 1027 * panel can use these parameters 1028 */ 1029 ret = dsi_populate_dsc_params(msm_host, dsc); 1030 if (ret) 1031 return; 1032 1033 /* 1034 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 1035 * enabled, MDP always sends out 48-bit compressed data per 1036 * pclk and on average, DSI consumes an amount of compressed 1037 * data equivalent to the uncompressed pixel depth per pclk. 1038 * 1039 * Calculate the number of pclks needed to transmit one line of 1040 * the compressed data. 1041 1042 * The back/font porch and pulse width are kept intact. For 1043 * VIDEO mode they represent timing parameters rather than 1044 * actual data transfer, see the documentation for 1045 * dsi_adjust_pclk_for_compression(). For CMD mode they are 1046 * unused anyway. 1047 */ 1048 h_total -= hdisplay; 1049 if (wide_bus_enabled) 1050 bits_per_pclk = mipi_dsi_pixel_format_to_bpp(msm_host->format); 1051 else 1052 bits_per_pclk = 24; 1053 1054 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc) * 8, bits_per_pclk); 1055 1056 h_total += hdisplay; 1057 ha_end = ha_start + hdisplay; 1058 } 1059 1060 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 1061 if (msm_host->dsc) 1062 dsi_update_dsc_timing(msm_host, false); 1063 1064 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1065 DSI_ACTIVE_H_START(ha_start) | 1066 DSI_ACTIVE_H_END(ha_end)); 1067 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1068 DSI_ACTIVE_V_START(va_start) | 1069 DSI_ACTIVE_V_END(va_end)); 1070 dsi_write(msm_host, REG_DSI_TOTAL, 1071 DSI_TOTAL_H_TOTAL(h_total - 1) | 1072 DSI_TOTAL_V_TOTAL(v_total - 1)); 1073 1074 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1075 DSI_ACTIVE_HSYNC_START(hs_start) | 1076 DSI_ACTIVE_HSYNC_END(hs_end)); 1077 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1078 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1079 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1080 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1081 } else { /* command mode */ 1082 if (msm_host->dsc) 1083 dsi_update_dsc_timing(msm_host, true); 1084 1085 /* image data and 1 byte write_memory_start cmd */ 1086 if (!msm_host->dsc) 1087 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1088 else 1089 /* 1090 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1091 * Currently, the driver only supports default value of slice_per_pkt = 1 1092 * 1093 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info 1094 * and adjust DSC math to account for slice_per_pkt. 1095 */ 1096 wc = msm_host->dsc->slice_chunk_size + 1; 1097 1098 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1099 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1100 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1101 msm_host->channel) | 1102 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1103 MIPI_DSI_DCS_LONG_WRITE)); 1104 1105 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1106 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1107 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1108 } 1109} 1110 1111static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1112{ 1113 u32 ctrl; 1114 1115 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1116 1117 if (ctrl & DSI_CTRL_ENABLE) { 1118 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1119 /* 1120 * dsi controller need to be disabled before 1121 * clocks turned on 1122 */ 1123 wmb(); 1124 } 1125 1126 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1127 wmb(); /* clocks need to be enabled before reset */ 1128 1129 /* dsi controller can only be reset while clocks are running */ 1130 dsi_write(msm_host, REG_DSI_RESET, 1); 1131 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1132 dsi_write(msm_host, REG_DSI_RESET, 0); 1133 wmb(); /* controller out of reset */ 1134 1135 if (ctrl & DSI_CTRL_ENABLE) { 1136 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1137 wmb(); /* make sure dsi controller enabled again */ 1138 } 1139} 1140 1141static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1142 bool video_mode, bool enable) 1143{ 1144 u32 dsi_ctrl; 1145 1146 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1147 1148 if (!enable) { 1149 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1150 DSI_CTRL_CMD_MODE_EN); 1151 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1152 DSI_IRQ_MASK_VIDEO_DONE, 0); 1153 } else { 1154 if (video_mode) { 1155 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1156 } else { /* command mode */ 1157 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1158 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1159 } 1160 dsi_ctrl |= DSI_CTRL_ENABLE; 1161 } 1162 1163 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1164} 1165 1166static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1167{ 1168 u32 data; 1169 1170 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1171 1172 if (mode == 0) 1173 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1174 else 1175 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1176 1177 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1178} 1179 1180static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1181{ 1182 u32 ret = 0; 1183 struct device *dev = &msm_host->pdev->dev; 1184 1185 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1186 1187 reinit_completion(&msm_host->video_comp); 1188 1189 ret = wait_for_completion_timeout(&msm_host->video_comp, 1190 msecs_to_jiffies(70)); 1191 1192 if (ret == 0) 1193 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1194 1195 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1196} 1197 1198static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1199{ 1200 u32 data; 1201 1202 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1203 return; 1204 1205 data = dsi_read(msm_host, REG_DSI_STATUS0); 1206 1207 /* if video mode engine is not busy, its because 1208 * either timing engine was not turned on or the 1209 * DSI controller has finished transmitting the video 1210 * data already, so no need to wait in those cases 1211 */ 1212 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1213 return; 1214 1215 if (msm_host->power_on && msm_host->enabled) { 1216 dsi_wait4video_done(msm_host); 1217 /* delay 4 ms to skip BLLP */ 1218 usleep_range(2000, 4000); 1219 } 1220} 1221 1222int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1223{ 1224 struct drm_device *dev = msm_host->dev; 1225 struct msm_drm_private *priv = dev->dev_private; 1226 uint64_t iova; 1227 u8 *data; 1228 1229 msm_host->vm = drm_gpuvm_get(priv->kms->vm); 1230 1231 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1232 msm_host->vm, 1233 &msm_host->tx_gem_obj, &iova); 1234 1235 if (IS_ERR(data)) { 1236 msm_host->tx_gem_obj = NULL; 1237 return PTR_ERR(data); 1238 } 1239 1240 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1241 1242 msm_host->tx_size = msm_host->tx_gem_obj->size; 1243 1244 return 0; 1245} 1246 1247int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1248{ 1249 struct drm_device *dev = msm_host->dev; 1250 1251 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1252 &msm_host->tx_buf_paddr, GFP_KERNEL); 1253 if (!msm_host->tx_buf) 1254 return -ENOMEM; 1255 1256 msm_host->tx_size = size; 1257 1258 return 0; 1259} 1260 1261void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1262{ 1263 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1264 struct drm_device *dev = msm_host->dev; 1265 1266 /* 1267 * This is possible if we're tearing down before we've had a chance to 1268 * fully initialize. A very real possibility if our probe is deferred, 1269 * in which case we'll hit msm_dsi_host_destroy() without having run 1270 * through the dsi_tx_buf_alloc(). 1271 */ 1272 if (!dev) 1273 return; 1274 1275 if (msm_host->tx_gem_obj) { 1276 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm); 1277 drm_gpuvm_put(msm_host->vm); 1278 msm_host->tx_gem_obj = NULL; 1279 msm_host->vm = NULL; 1280 } 1281 1282 if (msm_host->tx_buf) 1283 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1284 msm_host->tx_buf_paddr); 1285} 1286 1287void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1288{ 1289 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1290} 1291 1292void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1293{ 1294 return msm_host->tx_buf; 1295} 1296 1297void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1298{ 1299 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1300} 1301 1302/* 1303 * prepare cmd buffer to be txed 1304 */ 1305static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1306 const struct mipi_dsi_msg *msg) 1307{ 1308 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1309 struct mipi_dsi_packet packet; 1310 int len; 1311 int ret; 1312 u8 *data; 1313 1314 ret = mipi_dsi_create_packet(&packet, msg); 1315 if (ret) { 1316 pr_err("%s: create packet failed, %d\n", __func__, ret); 1317 return ret; 1318 } 1319 len = (packet.size + 3) & (~0x3); 1320 1321 if (len > msm_host->tx_size) { 1322 pr_err("%s: packet size is too big\n", __func__); 1323 return -EINVAL; 1324 } 1325 1326 data = cfg_hnd->ops->tx_buf_get(msm_host); 1327 if (IS_ERR(data)) { 1328 ret = PTR_ERR(data); 1329 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1330 return ret; 1331 } 1332 1333 /* MSM specific command format in memory */ 1334 data[0] = packet.header[1]; 1335 data[1] = packet.header[2]; 1336 data[2] = packet.header[0]; 1337 data[3] = BIT(7); /* Last packet */ 1338 if (mipi_dsi_packet_format_is_long(msg->type)) 1339 data[3] |= BIT(6); 1340 if (msg->rx_buf && msg->rx_len) 1341 data[3] |= BIT(5); 1342 1343 /* Long packet */ 1344 if (packet.payload && packet.payload_length) 1345 memcpy(data + 4, packet.payload, packet.payload_length); 1346 1347 /* Append 0xff to the end */ 1348 if (packet.size < len) 1349 memset(data + packet.size, 0xff, len - packet.size); 1350 1351 if (cfg_hnd->ops->tx_buf_put) 1352 cfg_hnd->ops->tx_buf_put(msm_host); 1353 1354 return len; 1355} 1356 1357/* 1358 * dsi_short_read1_resp: 1 parameter 1359 */ 1360static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1361{ 1362 u8 *data = msg->rx_buf; 1363 1364 if (data && (msg->rx_len >= 1)) { 1365 *data = buf[1]; /* strip out dcs type */ 1366 return 1; 1367 } 1368 1369 pr_err("%s: read data does not match with rx_buf len %zu\n", 1370 __func__, msg->rx_len); 1371 return -EINVAL; 1372} 1373 1374/* 1375 * dsi_short_read2_resp: 2 parameter 1376 */ 1377static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1378{ 1379 u8 *data = msg->rx_buf; 1380 1381 if (data && (msg->rx_len >= 2)) { 1382 data[0] = buf[1]; /* strip out dcs type */ 1383 data[1] = buf[2]; 1384 return 2; 1385 } 1386 1387 pr_err("%s: read data does not match with rx_buf len %zu\n", 1388 __func__, msg->rx_len); 1389 return -EINVAL; 1390} 1391 1392static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1393{ 1394 /* strip out 4 byte dcs header */ 1395 if (msg->rx_buf && msg->rx_len) 1396 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1397 1398 return msg->rx_len; 1399} 1400 1401int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1402{ 1403 struct drm_device *dev = msm_host->dev; 1404 struct msm_drm_private *priv = dev->dev_private; 1405 1406 if (!dma_base) 1407 return -EINVAL; 1408 1409 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1410 priv->kms->vm, dma_base); 1411} 1412 1413int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1414{ 1415 if (!dma_base) 1416 return -EINVAL; 1417 1418 *dma_base = msm_host->tx_buf_paddr; 1419 return 0; 1420} 1421 1422static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1423{ 1424 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1425 int ret; 1426 uint64_t dma_base; 1427 bool triggered; 1428 1429 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1430 if (ret) { 1431 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1432 return ret; 1433 } 1434 1435 reinit_completion(&msm_host->dma_comp); 1436 1437 dsi_wait4video_eng_busy(msm_host); 1438 1439 triggered = msm_dsi_manager_cmd_xfer_trigger( 1440 msm_host->id, dma_base, len); 1441 if (triggered) { 1442 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1443 msecs_to_jiffies(200)); 1444 DBG("ret=%d", ret); 1445 if (ret == 0) 1446 ret = -ETIMEDOUT; 1447 else 1448 ret = len; 1449 } else { 1450 ret = len; 1451 } 1452 1453 return ret; 1454} 1455 1456static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1457 u8 *buf, int rx_byte, int pkt_size) 1458{ 1459 u32 *temp, data; 1460 int i, j = 0, cnt; 1461 u32 read_cnt; 1462 u8 reg[16]; 1463 int repeated_bytes = 0; 1464 int buf_offset = buf - msm_host->rx_buf; 1465 1466 temp = (u32 *)reg; 1467 cnt = (rx_byte + 3) >> 2; 1468 if (cnt > 4) 1469 cnt = 4; /* 4 x 32 bits registers only */ 1470 1471 if (rx_byte == 4) 1472 read_cnt = 4; 1473 else 1474 read_cnt = pkt_size + 6; 1475 1476 /* 1477 * In case of multiple reads from the panel, after the first read, there 1478 * is possibility that there are some bytes in the payload repeating in 1479 * the RDBK_DATA registers. Since we read all the parameters from the 1480 * panel right from the first byte for every pass. We need to skip the 1481 * repeating bytes and then append the new parameters to the rx buffer. 1482 */ 1483 if (read_cnt > 16) { 1484 int bytes_shifted; 1485 /* Any data more than 16 bytes will be shifted out. 1486 * The temp read buffer should already contain these bytes. 1487 * The remaining bytes in read buffer are the repeated bytes. 1488 */ 1489 bytes_shifted = read_cnt - 16; 1490 repeated_bytes = buf_offset - bytes_shifted; 1491 } 1492 1493 for (i = cnt - 1; i >= 0; i--) { 1494 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1495 *temp++ = ntohl(data); /* to host byte order */ 1496 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1497 } 1498 1499 for (i = repeated_bytes; i < 16; i++) 1500 buf[j++] = reg[i]; 1501 1502 return j; 1503} 1504 1505static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1506 const struct mipi_dsi_msg *msg) 1507{ 1508 int len, ret; 1509 int bllp_len = msm_host->mode->hdisplay * 1510 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1511 1512 len = dsi_cmd_dma_add(msm_host, msg); 1513 if (len < 0) { 1514 pr_err("%s: failed to add cmd type = 0x%x\n", 1515 __func__, msg->type); 1516 return len; 1517 } 1518 1519 /* 1520 * for video mode, do not send cmds more than 1521 * one pixel line, since it only transmit it 1522 * during BLLP. 1523 * 1524 * TODO: if the command is sent in LP mode, the bit rate is only 1525 * half of esc clk rate. In this case, if the video is already 1526 * actively streaming, we need to check more carefully if the 1527 * command can be fit into one BLLP. 1528 */ 1529 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1530 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1531 __func__, len); 1532 return -EINVAL; 1533 } 1534 1535 ret = dsi_cmd_dma_tx(msm_host, len); 1536 if (ret < 0) { 1537 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1538 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1539 return ret; 1540 } else if (ret < len) { 1541 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1542 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1543 return -EIO; 1544 } 1545 1546 return len; 1547} 1548 1549static void dsi_err_worker(struct work_struct *work) 1550{ 1551 struct msm_dsi_host *msm_host = 1552 container_of(work, struct msm_dsi_host, err_work); 1553 u32 status = msm_host->err_work_state; 1554 1555 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1556 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1557 dsi_sw_reset(msm_host); 1558 1559 /* It is safe to clear here because error irq is disabled. */ 1560 msm_host->err_work_state = 0; 1561 1562 /* enable dsi error interrupt */ 1563 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1564} 1565 1566static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1567{ 1568 u32 status; 1569 1570 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1571 1572 if (status) { 1573 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1574 /* Writing of an extra 0 needed to clear error bits */ 1575 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1576 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1577 } 1578} 1579 1580static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1581{ 1582 u32 status; 1583 1584 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1585 1586 if (status) { 1587 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1588 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1589 } 1590} 1591 1592static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1593{ 1594 u32 status; 1595 1596 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1597 1598 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1599 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1600 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1601 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1602 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1603 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1604 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1605 } 1606} 1607 1608static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1609{ 1610 u32 status; 1611 1612 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1613 1614 /* fifo underflow, overflow */ 1615 if (status) { 1616 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1617 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1618 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1619 msm_host->err_work_state |= 1620 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1621 } 1622} 1623 1624static void dsi_status(struct msm_dsi_host *msm_host) 1625{ 1626 u32 status; 1627 1628 status = dsi_read(msm_host, REG_DSI_STATUS0); 1629 1630 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1631 dsi_write(msm_host, REG_DSI_STATUS0, status); 1632 msm_host->err_work_state |= 1633 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1634 } 1635} 1636 1637static void dsi_clk_status(struct msm_dsi_host *msm_host) 1638{ 1639 u32 status; 1640 1641 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1642 1643 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1644 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1645 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1646 } 1647} 1648 1649static void dsi_error(struct msm_dsi_host *msm_host) 1650{ 1651 /* disable dsi error interrupt */ 1652 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1653 1654 dsi_clk_status(msm_host); 1655 dsi_fifo_status(msm_host); 1656 dsi_ack_err_status(msm_host); 1657 dsi_timeout_status(msm_host); 1658 dsi_status(msm_host); 1659 dsi_dln0_phy_err(msm_host); 1660 1661 queue_work(msm_host->workqueue, &msm_host->err_work); 1662} 1663 1664static irqreturn_t dsi_host_irq(int irq, void *ptr) 1665{ 1666 struct msm_dsi_host *msm_host = ptr; 1667 u32 isr; 1668 unsigned long flags; 1669 1670 if (!msm_host->ctrl_base) 1671 return IRQ_HANDLED; 1672 1673 spin_lock_irqsave(&msm_host->intr_lock, flags); 1674 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1675 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1676 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1677 1678 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1679 1680 if (isr & DSI_IRQ_ERROR) 1681 dsi_error(msm_host); 1682 1683 if (isr & DSI_IRQ_VIDEO_DONE) 1684 complete(&msm_host->video_comp); 1685 1686 if (isr & DSI_IRQ_CMD_DMA_DONE) 1687 complete(&msm_host->dma_comp); 1688 1689 return IRQ_HANDLED; 1690} 1691 1692static int dsi_host_attach(struct mipi_dsi_host *host, 1693 struct mipi_dsi_device *dsi) 1694{ 1695 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1696 int ret; 1697 1698 if (dsi->lanes > msm_host->num_data_lanes) 1699 return -EINVAL; 1700 1701 msm_host->channel = dsi->channel; 1702 msm_host->lanes = dsi->lanes; 1703 msm_host->format = dsi->format; 1704 msm_host->mode_flags = dsi->mode_flags; 1705 if (dsi->dsc) 1706 msm_host->dsc = dsi->dsc; 1707 1708 ret = dsi_dev_attach(msm_host->pdev); 1709 if (ret) 1710 return ret; 1711 1712 DBG("id=%d", msm_host->id); 1713 1714 return 0; 1715} 1716 1717static int dsi_host_detach(struct mipi_dsi_host *host, 1718 struct mipi_dsi_device *dsi) 1719{ 1720 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1721 1722 dsi_dev_detach(msm_host->pdev); 1723 1724 DBG("id=%d", msm_host->id); 1725 1726 return 0; 1727} 1728 1729static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1730 const struct mipi_dsi_msg *msg) 1731{ 1732 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1733 int ret; 1734 1735 if (!msg || !msm_host->power_on) 1736 return -EINVAL; 1737 1738 mutex_lock(&msm_host->cmd_mutex); 1739 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1740 mutex_unlock(&msm_host->cmd_mutex); 1741 1742 return ret; 1743} 1744 1745static const struct mipi_dsi_host_ops dsi_host_ops = { 1746 .attach = dsi_host_attach, 1747 .detach = dsi_host_detach, 1748 .transfer = dsi_host_transfer, 1749}; 1750 1751/* 1752 * List of supported physical to logical lane mappings. 1753 * For example, the 2nd entry represents the following mapping: 1754 * 1755 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1756 */ 1757static const int supported_data_lane_swaps[][4] = { 1758 { 0, 1, 2, 3 }, 1759 { 3, 0, 1, 2 }, 1760 { 2, 3, 0, 1 }, 1761 { 1, 2, 3, 0 }, 1762 { 0, 3, 2, 1 }, 1763 { 1, 0, 3, 2 }, 1764 { 2, 1, 0, 3 }, 1765 { 3, 2, 1, 0 }, 1766}; 1767 1768static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1769 struct device_node *ep) 1770{ 1771 struct device *dev = &msm_host->pdev->dev; 1772 struct property *prop; 1773 u32 lane_map[4]; 1774 int ret, i, len, num_lanes; 1775 1776 prop = of_find_property(ep, "data-lanes", &len); 1777 if (!prop) { 1778 DRM_DEV_DEBUG(dev, 1779 "failed to find data lane mapping, using default\n"); 1780 /* Set the number of date lanes to 4 by default. */ 1781 msm_host->num_data_lanes = 4; 1782 return 0; 1783 } 1784 1785 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1786 if (num_lanes < 0) { 1787 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1788 return num_lanes; 1789 } 1790 1791 msm_host->num_data_lanes = num_lanes; 1792 1793 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1794 num_lanes); 1795 if (ret) { 1796 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1797 return ret; 1798 } 1799 1800 /* 1801 * compare DT specified physical-logical lane mappings with the ones 1802 * supported by hardware 1803 */ 1804 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1805 const int *swap = supported_data_lane_swaps[i]; 1806 int j; 1807 1808 /* 1809 * the data-lanes array we get from DT has a logical->physical 1810 * mapping. The "data lane swap" register field represents 1811 * supported configurations in a physical->logical mapping. 1812 * Translate the DT mapping to what we understand and find a 1813 * configuration that works. 1814 */ 1815 for (j = 0; j < num_lanes; j++) { 1816 if (lane_map[j] < 0 || lane_map[j] > 3) 1817 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1818 lane_map[j]); 1819 1820 if (swap[lane_map[j]] != j) 1821 break; 1822 } 1823 1824 if (j == num_lanes) { 1825 msm_host->dlane_swap = i; 1826 return 0; 1827 } 1828 } 1829 1830 return -EINVAL; 1831} 1832 1833static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1834{ 1835 int ret; 1836 1837 if (dsc->bits_per_pixel & 0xf) { 1838 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1839 return -EINVAL; 1840 } 1841 1842 switch (dsc->bits_per_component) { 1843 case 8: 1844 case 10: 1845 case 12: 1846 /* 1847 * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. 1848 * If additional bpc values need to be supported, update 1849 * this quard with the appropriate DSC version verification. 1850 */ 1851 break; 1852 default: 1853 DRM_DEV_ERROR(&msm_host->pdev->dev, 1854 "Unsupported bits_per_component value: %d\n", 1855 dsc->bits_per_component); 1856 return -EOPNOTSUPP; 1857 } 1858 1859 dsc->simple_422 = 0; 1860 dsc->convert_rgb = 1; 1861 dsc->vbr_enable = 0; 1862 1863 drm_dsc_set_const_params(dsc); 1864 drm_dsc_set_rc_buf_thresh(dsc); 1865 1866 /* DPU supports only pre-SCR panels */ 1867 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1868 if (ret) { 1869 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1870 return ret; 1871 } 1872 1873 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1874 dsc->line_buf_depth = dsc->bits_per_component + 1; 1875 1876 return drm_dsc_compute_rc_parameters(dsc); 1877} 1878 1879static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1880{ 1881 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); 1882 struct device *dev = &msm_host->pdev->dev; 1883 struct device_node *np = dev->of_node; 1884 struct device_node *endpoint; 1885 const char *te_source; 1886 int ret = 0; 1887 1888 /* 1889 * Get the endpoint of the output port of the DSI host. In our case, 1890 * this is mapped to port number with reg = 1. Don't return an error if 1891 * the remote endpoint isn't defined. It's possible that there is 1892 * nothing connected to the dsi output. 1893 */ 1894 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1895 if (!endpoint) { 1896 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1897 return 0; 1898 } 1899 1900 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1901 if (ret) { 1902 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1903 __func__, ret); 1904 ret = -EINVAL; 1905 goto err; 1906 } 1907 1908 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); 1909 if (ret && ret != -EINVAL) { 1910 DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", 1911 __func__, ret); 1912 goto err; 1913 } 1914 if (!ret) { 1915 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); 1916 if (!msm_dsi->te_source) { 1917 DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", 1918 __func__); 1919 ret = -ENOMEM; 1920 goto err; 1921 } 1922 } 1923 ret = 0; 1924 1925 if (of_property_present(np, "syscon-sfpb")) { 1926 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1927 "syscon-sfpb"); 1928 if (IS_ERR(msm_host->sfpb)) { 1929 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1930 __func__); 1931 ret = PTR_ERR(msm_host->sfpb); 1932 } 1933 } 1934 1935err: 1936 of_node_put(endpoint); 1937 1938 return ret; 1939} 1940 1941static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1942{ 1943 struct platform_device *pdev = msm_host->pdev; 1944 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1945 struct resource *res; 1946 int i, j; 1947 1948 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1949 if (!res) 1950 return -EINVAL; 1951 1952 for (i = 0; i < VARIANTS_MAX; i++) 1953 for (j = 0; j < DSI_MAX; j++) 1954 if (cfg->io_start[i][j] == res->start) 1955 return j; 1956 1957 return -EINVAL; 1958} 1959 1960int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1961{ 1962 struct msm_dsi_host *msm_host = NULL; 1963 struct platform_device *pdev = msm_dsi->pdev; 1964 const struct msm_dsi_config *cfg; 1965 int ret; 1966 1967 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1968 if (!msm_host) 1969 return -ENOMEM; 1970 1971 msm_host->pdev = pdev; 1972 msm_dsi->host = &msm_host->base; 1973 1974 ret = dsi_host_parse_dt(msm_host); 1975 if (ret) 1976 return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", 1977 __func__); 1978 1979 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1980 if (IS_ERR(msm_host->ctrl_base)) 1981 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), 1982 "%s: unable to map Dsi ctrl base\n", __func__); 1983 1984 pm_runtime_enable(&pdev->dev); 1985 1986 msm_host->cfg_hnd = dsi_get_config(msm_host); 1987 if (!msm_host->cfg_hnd) 1988 return dev_err_probe(&pdev->dev, -EINVAL, 1989 "%s: get config failed\n", __func__); 1990 cfg = msm_host->cfg_hnd->cfg; 1991 1992 msm_host->id = dsi_host_get_id(msm_host); 1993 if (msm_host->id < 0) 1994 return dev_err_probe(&pdev->dev, msm_host->id, 1995 "%s: unable to identify DSI host index\n", 1996 __func__); 1997 1998 /* fixup base address by io offset */ 1999 msm_host->ctrl_base += cfg->io_offset; 2000 2001 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 2002 cfg->regulator_data, 2003 &msm_host->supplies); 2004 if (ret) 2005 return ret; 2006 2007 ret = dsi_clk_init(msm_host); 2008 if (ret) 2009 return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); 2010 2011 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 2012 if (!msm_host->rx_buf) 2013 return -ENOMEM; 2014 2015 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 2016 if (ret) 2017 return ret; 2018 /* OPP table is optional */ 2019 ret = devm_pm_opp_of_add_table(&pdev->dev); 2020 if (ret && ret != -ENODEV) 2021 return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); 2022 2023 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 2024 if (!msm_host->irq) 2025 return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); 2026 2027 /* do not autoenable, will be enabled later */ 2028 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 2029 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 2030 "dsi_isr", msm_host); 2031 if (ret < 0) 2032 return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", 2033 msm_host->irq); 2034 2035 init_completion(&msm_host->dma_comp); 2036 init_completion(&msm_host->video_comp); 2037 mutex_init(&msm_host->dev_mutex); 2038 mutex_init(&msm_host->cmd_mutex); 2039 spin_lock_init(&msm_host->intr_lock); 2040 2041 /* setup workqueue */ 2042 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 2043 if (!msm_host->workqueue) 2044 return -ENOMEM; 2045 2046 INIT_WORK(&msm_host->err_work, dsi_err_worker); 2047 2048 msm_dsi->id = msm_host->id; 2049 2050 DBG("Dsi Host %d initialized", msm_host->id); 2051 return 0; 2052} 2053 2054void msm_dsi_host_destroy(struct mipi_dsi_host *host) 2055{ 2056 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2057 2058 DBG(""); 2059 if (msm_host->workqueue) { 2060 destroy_workqueue(msm_host->workqueue); 2061 msm_host->workqueue = NULL; 2062 } 2063 2064 mutex_destroy(&msm_host->cmd_mutex); 2065 mutex_destroy(&msm_host->dev_mutex); 2066 2067 pm_runtime_disable(&msm_host->pdev->dev); 2068} 2069 2070int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2071 struct drm_device *dev) 2072{ 2073 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2074 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2075 int ret; 2076 2077 msm_host->dev = dev; 2078 2079 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2080 if (ret) { 2081 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2082 return ret; 2083 } 2084 2085 return 0; 2086} 2087 2088int msm_dsi_host_register(struct mipi_dsi_host *host) 2089{ 2090 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2091 int ret; 2092 2093 /* Register mipi dsi host */ 2094 if (!msm_host->registered) { 2095 host->dev = &msm_host->pdev->dev; 2096 host->ops = &dsi_host_ops; 2097 ret = mipi_dsi_host_register(host); 2098 if (ret) 2099 return ret; 2100 2101 msm_host->registered = true; 2102 } 2103 2104 return 0; 2105} 2106 2107void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2108{ 2109 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2110 2111 if (msm_host->registered) { 2112 mipi_dsi_host_unregister(host); 2113 host->dev = NULL; 2114 host->ops = NULL; 2115 msm_host->registered = false; 2116 } 2117} 2118 2119int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2120 const struct mipi_dsi_msg *msg) 2121{ 2122 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2123 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2124 2125 /* TODO: make sure dsi_cmd_mdp is idle. 2126 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2127 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2128 * How to handle the old versions? Wait for mdp cmd done? 2129 */ 2130 2131 /* 2132 * mdss interrupt is generated in mdp core clock domain 2133 * mdp clock need to be enabled to receive dsi interrupt 2134 */ 2135 pm_runtime_get_sync(&msm_host->pdev->dev); 2136 cfg_hnd->ops->link_clk_set_rate(msm_host); 2137 cfg_hnd->ops->link_clk_enable(msm_host); 2138 2139 /* TODO: vote for bus bandwidth */ 2140 2141 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2142 dsi_set_tx_power_mode(0, msm_host); 2143 2144 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2145 dsi_write(msm_host, REG_DSI_CTRL, 2146 msm_host->dma_cmd_ctrl_restore | 2147 DSI_CTRL_CMD_MODE_EN | 2148 DSI_CTRL_ENABLE); 2149 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2150 2151 return 0; 2152} 2153 2154void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2155 const struct mipi_dsi_msg *msg) 2156{ 2157 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2158 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2159 2160 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2161 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2162 2163 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2164 dsi_set_tx_power_mode(1, msm_host); 2165 2166 /* TODO: unvote for bus bandwidth */ 2167 2168 cfg_hnd->ops->link_clk_disable(msm_host); 2169 pm_runtime_put(&msm_host->pdev->dev); 2170} 2171 2172int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2173 const struct mipi_dsi_msg *msg) 2174{ 2175 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2176 2177 return dsi_cmds2buf_tx(msm_host, msg); 2178} 2179 2180int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2181 const struct mipi_dsi_msg *msg) 2182{ 2183 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2184 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2185 int data_byte, rx_byte, dlen, end; 2186 int short_response, diff, pkt_size, ret = 0; 2187 char cmd; 2188 int rlen = msg->rx_len; 2189 u8 *buf; 2190 2191 if (rlen <= 2) { 2192 short_response = 1; 2193 pkt_size = rlen; 2194 rx_byte = 4; 2195 } else { 2196 short_response = 0; 2197 data_byte = 10; /* first read */ 2198 if (rlen < data_byte) 2199 pkt_size = rlen; 2200 else 2201 pkt_size = data_byte; 2202 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2203 } 2204 2205 buf = msm_host->rx_buf; 2206 end = 0; 2207 while (!end) { 2208 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2209 struct mipi_dsi_msg max_pkt_size_msg = { 2210 .channel = msg->channel, 2211 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2212 .tx_len = 2, 2213 .tx_buf = tx, 2214 }; 2215 2216 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2217 rlen, pkt_size, rx_byte); 2218 2219 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2220 if (ret < 2) { 2221 pr_err("%s: Set max pkt size failed, %d\n", 2222 __func__, ret); 2223 return -EINVAL; 2224 } 2225 2226 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2227 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2228 /* Clear the RDBK_DATA registers */ 2229 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2230 DSI_RDBK_DATA_CTRL_CLR); 2231 wmb(); /* make sure the RDBK registers are cleared */ 2232 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2233 wmb(); /* release cleared status before transfer */ 2234 } 2235 2236 ret = dsi_cmds2buf_tx(msm_host, msg); 2237 if (ret < 0) { 2238 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2239 return ret; 2240 } else if (ret < msg->tx_len) { 2241 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2242 return -ECOMM; 2243 } 2244 2245 /* 2246 * once cmd_dma_done interrupt received, 2247 * return data from client is ready and stored 2248 * at RDBK_DATA register already 2249 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2250 * after that dcs header lost during shift into registers 2251 */ 2252 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2253 2254 if (dlen <= 0) 2255 return 0; 2256 2257 if (short_response) 2258 break; 2259 2260 if (rlen <= data_byte) { 2261 diff = data_byte - rlen; 2262 end = 1; 2263 } else { 2264 diff = 0; 2265 rlen -= data_byte; 2266 } 2267 2268 if (!end) { 2269 dlen -= 2; /* 2 crc */ 2270 dlen -= diff; 2271 buf += dlen; /* next start position */ 2272 data_byte = 14; /* NOT first read */ 2273 if (rlen < data_byte) 2274 pkt_size += rlen; 2275 else 2276 pkt_size += data_byte; 2277 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2278 } 2279 } 2280 2281 /* 2282 * For single Long read, if the requested rlen < 10, 2283 * we need to shift the start position of rx 2284 * data buffer to skip the bytes which are not 2285 * updated. 2286 */ 2287 if (pkt_size < 10 && !short_response) 2288 buf = msm_host->rx_buf + (10 - rlen); 2289 else 2290 buf = msm_host->rx_buf; 2291 2292 cmd = buf[0]; 2293 switch (cmd) { 2294 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2295 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2296 ret = 0; 2297 break; 2298 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2299 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2300 ret = dsi_short_read1_resp(buf, msg); 2301 break; 2302 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2303 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2304 ret = dsi_short_read2_resp(buf, msg); 2305 break; 2306 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2307 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2308 ret = dsi_long_read_resp(buf, msg); 2309 break; 2310 default: 2311 pr_warn("%s:Invalid response cmd\n", __func__); 2312 ret = 0; 2313 } 2314 2315 return ret; 2316} 2317 2318void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2319 u32 len) 2320{ 2321 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2322 2323 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2324 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2325 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2326 2327 /* Make sure trigger happens */ 2328 wmb(); 2329} 2330 2331void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2332 struct msm_dsi_phy *src_phy) 2333{ 2334 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2335 2336 msm_host->cphy_mode = src_phy->cphy_mode; 2337} 2338 2339void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2340{ 2341 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2342 2343 DBG(""); 2344 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2345 /* Make sure fully reset */ 2346 wmb(); 2347 udelay(1000); 2348 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2349 udelay(100); 2350} 2351 2352void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2353 struct msm_dsi_phy_clk_request *clk_req, 2354 bool is_bonded_dsi) 2355{ 2356 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2357 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2358 int ret; 2359 2360 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2361 if (ret) { 2362 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2363 return; 2364 } 2365 2366 /* CPHY transmits 16 bits over 7 clock cycles 2367 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2368 * so multiply by 7 to get the "bitclk rate" 2369 */ 2370 if (msm_host->cphy_mode) 2371 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2372 else 2373 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2374 clk_req->escclk_rate = msm_host->esc_clk_rate; 2375} 2376 2377void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2378{ 2379 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2380 2381 enable_irq(msm_host->irq); 2382} 2383 2384void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2385{ 2386 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2387 2388 disable_irq(msm_host->irq); 2389} 2390 2391int msm_dsi_host_enable(struct mipi_dsi_host *host) 2392{ 2393 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2394 2395 dsi_op_mode_config(msm_host, 2396 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2397 2398 /* TODO: clock should be turned off for command mode, 2399 * and only turned on before MDP START. 2400 * This part of code should be enabled once mdp driver support it. 2401 */ 2402 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2403 * dsi_link_clk_disable(msm_host); 2404 * pm_runtime_put(&msm_host->pdev->dev); 2405 * } 2406 */ 2407 msm_host->enabled = true; 2408 return 0; 2409} 2410 2411int msm_dsi_host_disable(struct mipi_dsi_host *host) 2412{ 2413 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2414 2415 msm_host->enabled = false; 2416 dsi_op_mode_config(msm_host, 2417 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2418 2419 /* Since we have disabled INTF, the video engine won't stop so that 2420 * the cmd engine will be blocked. 2421 * Reset to disable video engine so that we can send off cmd. 2422 */ 2423 dsi_sw_reset(msm_host); 2424 2425 return 0; 2426} 2427 2428static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2429{ 2430 enum sfpb_ahb_arb_master_port_en en; 2431 2432 if (!msm_host->sfpb) 2433 return; 2434 2435 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2436 2437 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2438 SFPB_GPREG_MASTER_PORT_EN__MASK, 2439 SFPB_GPREG_MASTER_PORT_EN(en)); 2440} 2441 2442int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2443 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2444 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2445{ 2446 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2447 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2448 int ret = 0; 2449 2450 mutex_lock(&msm_host->dev_mutex); 2451 if (msm_host->power_on) { 2452 DBG("dsi host already on"); 2453 goto unlock_ret; 2454 } 2455 2456 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2457 if (phy_shared_timings->byte_intf_clk_div_2) 2458 msm_host->byte_intf_clk_rate /= 2; 2459 2460 msm_dsi_sfpb_config(msm_host, true); 2461 2462 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2463 msm_host->supplies); 2464 if (ret) { 2465 pr_err("%s:Failed to enable vregs.ret=%d\n", 2466 __func__, ret); 2467 goto unlock_ret; 2468 } 2469 2470 pm_runtime_get_sync(&msm_host->pdev->dev); 2471 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2472 if (!ret) 2473 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2474 if (ret) { 2475 pr_err("%s: failed to enable link clocks. ret=%d\n", 2476 __func__, ret); 2477 goto fail_disable_reg; 2478 } 2479 2480 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2481 if (ret) { 2482 pr_err("%s: failed to set pinctrl default state, %d\n", 2483 __func__, ret); 2484 goto fail_disable_clk; 2485 } 2486 2487 dsi_timing_setup(msm_host, is_bonded_dsi); 2488 dsi_sw_reset(msm_host); 2489 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2490 2491 msm_host->power_on = true; 2492 mutex_unlock(&msm_host->dev_mutex); 2493 2494 return 0; 2495 2496fail_disable_clk: 2497 cfg_hnd->ops->link_clk_disable(msm_host); 2498 pm_runtime_put(&msm_host->pdev->dev); 2499fail_disable_reg: 2500 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2501 msm_host->supplies); 2502unlock_ret: 2503 mutex_unlock(&msm_host->dev_mutex); 2504 return ret; 2505} 2506 2507int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2508{ 2509 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2510 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2511 2512 mutex_lock(&msm_host->dev_mutex); 2513 if (!msm_host->power_on) { 2514 DBG("dsi host already off"); 2515 goto unlock_ret; 2516 } 2517 2518 dsi_ctrl_disable(msm_host); 2519 2520 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2521 2522 cfg_hnd->ops->link_clk_disable(msm_host); 2523 pm_runtime_put(&msm_host->pdev->dev); 2524 2525 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2526 msm_host->supplies); 2527 2528 msm_dsi_sfpb_config(msm_host, false); 2529 2530 DBG("-"); 2531 2532 msm_host->power_on = false; 2533 2534unlock_ret: 2535 mutex_unlock(&msm_host->dev_mutex); 2536 return 0; 2537} 2538 2539int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2540 const struct drm_display_mode *mode) 2541{ 2542 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2543 2544 if (msm_host->mode) { 2545 drm_mode_destroy(msm_host->dev, msm_host->mode); 2546 msm_host->mode = NULL; 2547 } 2548 2549 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2550 if (!msm_host->mode) { 2551 pr_err("%s: cannot duplicate mode\n", __func__); 2552 return -ENOMEM; 2553 } 2554 2555 return 0; 2556} 2557 2558enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2559 const struct drm_display_mode *mode) 2560{ 2561 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2562 struct drm_dsc_config *dsc = msm_host->dsc; 2563 int pic_width = mode->hdisplay; 2564 int pic_height = mode->vdisplay; 2565 2566 if (!msm_host->dsc) 2567 return MODE_OK; 2568 2569 if (pic_width % dsc->slice_width) { 2570 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2571 pic_width, dsc->slice_width); 2572 return MODE_H_ILLEGAL; 2573 } 2574 2575 if (pic_height % dsc->slice_height) { 2576 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2577 pic_height, dsc->slice_height); 2578 return MODE_V_ILLEGAL; 2579 } 2580 2581 return MODE_OK; 2582} 2583 2584unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2585{ 2586 return to_msm_dsi_host(host)->mode_flags; 2587} 2588 2589void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2590{ 2591 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2592 2593 pm_runtime_get_sync(&msm_host->pdev->dev); 2594 2595 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2596 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2597 2598 pm_runtime_put_sync(&msm_host->pdev->dev); 2599} 2600 2601static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2602{ 2603 u32 reg; 2604 2605 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2606 2607 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2608 /* draw checkered rectangle pattern */ 2609 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2610 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2611 /* use 24-bit RGB test pttern */ 2612 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2613 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2614 DSI_TPG_VIDEO_CONFIG_RGB); 2615 2616 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2617 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2618 2619 DBG("Video test pattern setup done\n"); 2620} 2621 2622static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2623{ 2624 u32 reg; 2625 2626 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2627 2628 /* initial value for test pattern */ 2629 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2630 2631 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2632 2633 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2634 /* draw checkered rectangle pattern */ 2635 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2636 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2637 2638 DBG("Cmd test pattern setup done\n"); 2639} 2640 2641void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2642{ 2643 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2644 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2645 u32 reg; 2646 2647 if (is_video_mode) 2648 msm_dsi_host_video_test_pattern_setup(msm_host); 2649 else 2650 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2651 2652 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2653 /* enable the test pattern generator */ 2654 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2655 2656 /* for command mode need to trigger one frame from tpg */ 2657 if (!is_video_mode) 2658 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2659 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2660} 2661 2662struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2663{ 2664 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2665 2666 return msm_host->dsc; 2667}
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