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mdp5_plane.c
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linux-6.19.14/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8#include <drm/drm_atomic.h> 9#include <drm/drm_blend.h> 10#include <drm/drm_damage_helper.h> 11#include <drm/drm_fourcc.h> 12#include <drm/drm_framebuffer.h> 13#include <drm/drm_gem_atomic_helper.h> 14#include <drm/drm_print.h> 15 16#include "mdp5_kms.h" 17 18struct mdp5_plane { 19 struct drm_plane base; 20}; 21#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) 22 23static int mdp5_plane_mode_set(struct drm_plane *plane, 24 struct drm_crtc *crtc, struct drm_framebuffer *fb, 25 struct drm_rect *src, struct drm_rect *dest); 26 27static struct mdp5_kms *get_kms(struct drm_plane *plane) 28{ 29 struct msm_drm_private *priv = plane->dev->dev_private; 30 return to_mdp5_kms(to_mdp_kms(priv->kms)); 31} 32 33static bool plane_enabled(struct drm_plane_state *state) 34{ 35 return state->visible; 36} 37 38/* helper to install properties which are common to planes and crtcs */ 39static void mdp5_plane_install_properties(struct drm_plane *plane, 40 struct drm_mode_object *obj) 41{ 42 unsigned int zpos; 43 44 drm_plane_create_rotation_property(plane, 45 DRM_MODE_ROTATE_0, 46 DRM_MODE_ROTATE_0 | 47 DRM_MODE_ROTATE_180 | 48 DRM_MODE_REFLECT_X | 49 DRM_MODE_REFLECT_Y); 50 drm_plane_create_alpha_property(plane); 51 drm_plane_create_blend_mode_property(plane, 52 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 53 BIT(DRM_MODE_BLEND_PREMULTI) | 54 BIT(DRM_MODE_BLEND_COVERAGE)); 55 56 if (plane->type == DRM_PLANE_TYPE_PRIMARY) 57 zpos = STAGE_BASE; 58 else 59 zpos = STAGE0 + drm_plane_index(plane); 60 drm_plane_create_zpos_property(plane, zpos, 1, 255); 61} 62 63static void 64mdp5_plane_atomic_print_state(struct drm_printer *p, 65 const struct drm_plane_state *state) 66{ 67 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 68 struct mdp5_kms *mdp5_kms = get_kms(state->plane); 69 70 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? 71 pstate->hwpipe->name : "(null)"); 72 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 73 drm_printf(p, "\tright-hwpipe=%s\n", 74 pstate->r_hwpipe ? pstate->r_hwpipe->name : 75 "(null)"); 76 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode); 77 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos); 78 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos); 79 drm_printf(p, "\talpha=%u\n", pstate->base.alpha); 80 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); 81} 82 83static void mdp5_plane_reset(struct drm_plane *plane) 84{ 85 struct mdp5_plane_state *mdp5_state; 86 87 if (plane->state) 88 __drm_atomic_helper_plane_destroy_state(plane->state); 89 90 kfree(to_mdp5_plane_state(plane->state)); 91 plane->state = NULL; 92 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); 93 if (!mdp5_state) 94 return; 95 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base); 96} 97 98static struct drm_plane_state * 99mdp5_plane_duplicate_state(struct drm_plane *plane) 100{ 101 struct mdp5_plane_state *mdp5_state; 102 103 if (WARN_ON(!plane->state)) 104 return NULL; 105 106 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), 107 sizeof(*mdp5_state), GFP_KERNEL); 108 if (!mdp5_state) 109 return NULL; 110 111 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); 112 113 return &mdp5_state->base; 114} 115 116static void mdp5_plane_destroy_state(struct drm_plane *plane, 117 struct drm_plane_state *state) 118{ 119 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); 120 121 __drm_atomic_helper_plane_destroy_state(state); 122 123 kfree(pstate); 124} 125 126static const struct drm_plane_funcs mdp5_plane_funcs = { 127 .update_plane = drm_atomic_helper_update_plane, 128 .disable_plane = drm_atomic_helper_disable_plane, 129 .reset = mdp5_plane_reset, 130 .atomic_duplicate_state = mdp5_plane_duplicate_state, 131 .atomic_destroy_state = mdp5_plane_destroy_state, 132 .atomic_print_state = mdp5_plane_atomic_print_state, 133}; 134 135static int mdp5_plane_prepare_fb(struct drm_plane *plane, 136 struct drm_plane_state *new_state) 137{ 138 bool needs_dirtyfb = to_mdp5_plane_state(new_state)->needs_dirtyfb; 139 140 if (!new_state->fb) 141 return 0; 142 143 drm_gem_plane_helper_prepare_fb(plane, new_state); 144 145 return msm_framebuffer_prepare(new_state->fb, needs_dirtyfb); 146} 147 148static void mdp5_plane_cleanup_fb(struct drm_plane *plane, 149 struct drm_plane_state *old_state) 150{ 151 struct drm_framebuffer *fb = old_state->fb; 152 bool needed_dirtyfb = to_mdp5_plane_state(old_state)->needs_dirtyfb; 153 154 if (!fb) 155 return; 156 157 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); 158 msm_framebuffer_cleanup(fb, needed_dirtyfb); 159} 160 161static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, 162 struct drm_plane_state *state) 163{ 164 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); 165 struct drm_plane *plane = state->plane; 166 struct drm_plane_state *old_state = plane->state; 167 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); 168 bool new_hwpipe = false; 169 bool need_right_hwpipe = false; 170 uint32_t max_width, max_height; 171 bool out_of_bounds = false; 172 uint32_t caps = 0; 173 int min_scale, max_scale; 174 int ret; 175 176 DBG("%s: check (%d -> %d)", plane->name, 177 plane_enabled(old_state), plane_enabled(state)); 178 179 max_width = config->hw->lm.max_width << 16; 180 max_height = config->hw->lm.max_height << 16; 181 182 /* Make sure source dimensions are within bounds. */ 183 if (state->src_h > max_height) 184 out_of_bounds = true; 185 186 if (state->src_w > max_width) { 187 /* If source split is supported, we can go up to 2x 188 * the max LM width, but we'd need to stage another 189 * hwpipe to the right LM. So, the drm_plane would 190 * consist of 2 hwpipes. 191 */ 192 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && 193 (state->src_w <= 2 * max_width)) 194 need_right_hwpipe = true; 195 else 196 out_of_bounds = true; 197 } 198 199 if (out_of_bounds) { 200 struct drm_rect src = drm_plane_state_src(state); 201 DBG("Invalid source size "DRM_RECT_FP_FMT, 202 DRM_RECT_FP_ARG(&src)); 203 return -ERANGE; 204 } 205 206 min_scale = FRAC_16_16(1, 8); 207 max_scale = FRAC_16_16(8, 1); 208 209 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 210 min_scale, max_scale, 211 true, true); 212 if (ret) 213 return ret; 214 215 if (plane_enabled(state)) { 216 unsigned int rotation; 217 const struct msm_format *format; 218 struct mdp5_kms *mdp5_kms = get_kms(plane); 219 uint32_t blkcfg = 0; 220 221 format = msm_framebuffer_format(state->fb); 222 if (MSM_FORMAT_IS_YUV(format)) 223 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; 224 225 if (((state->src_w >> 16) != state->crtc_w) || 226 ((state->src_h >> 16) != state->crtc_h)) 227 caps |= MDP_PIPE_CAP_SCALE; 228 229 rotation = drm_rotation_simplify(state->rotation, 230 DRM_MODE_ROTATE_0 | 231 DRM_MODE_REFLECT_X | 232 DRM_MODE_REFLECT_Y); 233 234 if (rotation & DRM_MODE_REFLECT_X) 235 caps |= MDP_PIPE_CAP_HFLIP; 236 237 if (rotation & DRM_MODE_REFLECT_Y) 238 caps |= MDP_PIPE_CAP_VFLIP; 239 240 if (plane->type == DRM_PLANE_TYPE_CURSOR) 241 caps |= MDP_PIPE_CAP_CURSOR; 242 243 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ 244 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) 245 new_hwpipe = true; 246 247 /* 248 * (re)allocte hw pipe if we're either requesting for 2 hw pipes 249 * or we're switching from 2 hw pipes to 1 hw pipe because the 250 * new src_w can be supported by 1 hw pipe itself. 251 */ 252 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || 253 (!need_right_hwpipe && mdp5_state->r_hwpipe)) 254 new_hwpipe = true; 255 256 if (mdp5_kms->smp) { 257 const struct msm_format *format = 258 msm_framebuffer_format(state->fb); 259 260 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, 261 state->src_w >> 16, false); 262 263 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) 264 new_hwpipe = true; 265 } 266 267 /* (re)assign hwpipe if needed, otherwise keep old one: */ 268 if (new_hwpipe) { 269 /* TODO maybe we want to re-assign hwpipe sometimes 270 * in cases when we no-longer need some caps to make 271 * it available for other planes? 272 */ 273 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; 274 struct mdp5_hw_pipe *old_right_hwpipe = 275 mdp5_state->r_hwpipe; 276 struct mdp5_hw_pipe *new_hwpipe = NULL; 277 struct mdp5_hw_pipe *new_right_hwpipe = NULL; 278 279 ret = mdp5_pipe_assign(state->state, plane, caps, 280 blkcfg, &new_hwpipe, 281 need_right_hwpipe ? 282 &new_right_hwpipe : NULL); 283 if (ret) { 284 DBG("%s: failed to assign hwpipe(s)!", 285 plane->name); 286 return ret; 287 } 288 289 mdp5_state->hwpipe = new_hwpipe; 290 if (need_right_hwpipe) 291 mdp5_state->r_hwpipe = new_right_hwpipe; 292 else 293 /* 294 * set it to NULL so that the driver knows we 295 * don't have a right hwpipe when committing a 296 * new state 297 */ 298 mdp5_state->r_hwpipe = NULL; 299 300 301 ret = mdp5_pipe_release(state->state, old_hwpipe); 302 if (ret) 303 return ret; 304 305 ret = mdp5_pipe_release(state->state, old_right_hwpipe); 306 if (ret) 307 return ret; 308 309 } 310 } else { 311 ret = mdp5_pipe_release(state->state, mdp5_state->hwpipe); 312 if (ret) 313 return ret; 314 315 ret = mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); 316 if (ret) 317 return ret; 318 319 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; 320 } 321 322 return 0; 323} 324 325static int mdp5_plane_atomic_check(struct drm_plane *plane, 326 struct drm_atomic_state *state) 327{ 328 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, 329 plane); 330 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 331 plane); 332 struct drm_crtc *crtc; 333 struct drm_crtc_state *crtc_state; 334 335 crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc; 336 if (!crtc) 337 return 0; 338 339 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 340 if (WARN_ON(!crtc_state)) 341 return -EINVAL; 342 343 return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state); 344} 345 346static void mdp5_plane_atomic_update(struct drm_plane *plane, 347 struct drm_atomic_state *state) 348{ 349 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 350 plane); 351 352 DBG("%s: update", plane->name); 353 354 if (plane_enabled(new_state)) { 355 int ret; 356 357 ret = mdp5_plane_mode_set(plane, 358 new_state->crtc, new_state->fb, 359 &new_state->src, &new_state->dst); 360 /* atomic_check should have ensured that this doesn't fail */ 361 WARN_ON(ret < 0); 362 } 363} 364 365static int mdp5_plane_atomic_async_check(struct drm_plane *plane, 366 struct drm_atomic_state *state, bool flip) 367{ 368 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 369 plane); 370 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state); 371 struct drm_crtc_state *crtc_state; 372 int min_scale, max_scale; 373 int ret; 374 375 crtc_state = drm_atomic_get_new_crtc_state(state, 376 new_plane_state->crtc); 377 if (WARN_ON(!crtc_state)) 378 return -EINVAL; 379 380 if (!crtc_state->active) 381 return -EINVAL; 382 383 /* don't use fast path if we don't have a hwpipe allocated yet */ 384 if (!mdp5_state->hwpipe) 385 return -EINVAL; 386 387 /* only allow changing of position(crtc x/y or src x/y) in fast path */ 388 if (plane->state->crtc != new_plane_state->crtc || 389 plane->state->src_w != new_plane_state->src_w || 390 plane->state->src_h != new_plane_state->src_h || 391 plane->state->crtc_w != new_plane_state->crtc_w || 392 plane->state->crtc_h != new_plane_state->crtc_h || 393 !plane->state->fb || 394 plane->state->fb != new_plane_state->fb) 395 return -EINVAL; 396 397 min_scale = FRAC_16_16(1, 8); 398 max_scale = FRAC_16_16(8, 1); 399 400 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 401 min_scale, max_scale, 402 true, true); 403 if (ret) 404 return ret; 405 406 /* 407 * if the visibility of the plane changes (i.e, if the cursor is 408 * clipped out completely, we can't take the async path because 409 * we need to stage/unstage the plane from the Layer Mixer(s). We 410 * also assign/unassign the hwpipe(s) tied to the plane. We avoid 411 * taking the fast path for both these reasons. 412 */ 413 if (new_plane_state->visible != plane->state->visible) 414 return -EINVAL; 415 416 return 0; 417} 418 419static void mdp5_plane_atomic_async_update(struct drm_plane *plane, 420 struct drm_atomic_state *state) 421{ 422 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 423 plane); 424 struct drm_framebuffer *old_fb = plane->state->fb; 425 426 plane->state->src_x = new_state->src_x; 427 plane->state->src_y = new_state->src_y; 428 plane->state->crtc_x = new_state->crtc_x; 429 plane->state->crtc_y = new_state->crtc_y; 430 431 if (plane_enabled(new_state)) { 432 struct mdp5_ctl *ctl; 433 struct mdp5_pipeline *pipeline = 434 mdp5_crtc_get_pipeline(new_state->crtc); 435 int ret; 436 437 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb, 438 &new_state->src, &new_state->dst); 439 WARN_ON(ret < 0); 440 441 ctl = mdp5_crtc_get_ctl(new_state->crtc); 442 443 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); 444 } 445 446 *to_mdp5_plane_state(plane->state) = 447 *to_mdp5_plane_state(new_state); 448 449 new_state->fb = old_fb; 450} 451 452static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { 453 .prepare_fb = mdp5_plane_prepare_fb, 454 .cleanup_fb = mdp5_plane_cleanup_fb, 455 .atomic_check = mdp5_plane_atomic_check, 456 .atomic_update = mdp5_plane_atomic_update, 457 .atomic_async_check = mdp5_plane_atomic_async_check, 458 .atomic_async_update = mdp5_plane_atomic_async_update, 459}; 460 461static void set_scanout_locked(struct mdp5_kms *mdp5_kms, 462 enum mdp5_pipe pipe, 463 struct drm_framebuffer *fb) 464{ 465 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), 466 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | 467 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); 468 469 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), 470 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | 471 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); 472 473 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), 474 msm_framebuffer_iova(fb, 0)); 475 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), 476 msm_framebuffer_iova(fb, 1)); 477 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), 478 msm_framebuffer_iova(fb, 2)); 479 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), 480 msm_framebuffer_iova(fb, 3)); 481} 482 483/* Note: mdp5_plane->pipe_lock must be locked */ 484static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) 485{ 486 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & 487 ~MDP5_PIPE_OP_MODE_CSC_1_EN; 488 489 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); 490} 491 492/* Note: mdp5_plane->pipe_lock must be locked */ 493static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 494 struct csc_cfg *csc) 495{ 496 uint32_t i, mode = 0; /* RGB, no CSC */ 497 uint32_t *matrix; 498 499 if (unlikely(!csc)) 500 return; 501 502 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) 503 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); 504 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) 505 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); 506 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; 507 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); 508 509 matrix = csc->matrix; 510 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), 511 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | 512 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); 513 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), 514 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | 515 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); 516 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), 517 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | 518 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); 519 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), 520 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | 521 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); 522 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), 523 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); 524 525 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { 526 uint32_t *pre_clamp = csc->pre_clamp; 527 uint32_t *post_clamp = csc->post_clamp; 528 529 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), 530 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | 531 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); 532 533 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), 534 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | 535 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); 536 537 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), 538 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); 539 540 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), 541 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); 542 } 543} 544 545#define PHASE_STEP_SHIFT 21 546#define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ 547 548static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) 549{ 550 uint32_t unit; 551 552 if (src == 0 || dst == 0) 553 return -EINVAL; 554 555 /* 556 * PHASE_STEP_X/Y is coded on 26 bits (25:0), 557 * where 2^21 represents the unity "1" in fixed-point hardware design. 558 * This leaves 5 bits for the integer part (downscale case): 559 * -> maximum downscale ratio = 0b1_1111 = 31 560 */ 561 if (src > (dst * DOWN_SCALE_RATIO_MAX)) 562 return -EOVERFLOW; 563 564 unit = 1 << PHASE_STEP_SHIFT; 565 *out_phase = mult_frac(unit, src, dst); 566 567 return 0; 568} 569 570static int calc_scalex_steps(struct drm_plane *plane, 571 uint32_t pixel_format, uint32_t src, uint32_t dest, 572 uint32_t phasex_steps[COMP_MAX]) 573{ 574 const struct drm_format_info *info = drm_format_info(pixel_format); 575 struct mdp5_kms *mdp5_kms = get_kms(plane); 576 struct device *dev = mdp5_kms->dev->dev; 577 uint32_t phasex_step; 578 int ret; 579 580 ret = calc_phase_step(src, dest, &phasex_step); 581 if (ret) { 582 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); 583 return ret; 584 } 585 586 phasex_steps[COMP_0] = phasex_step; 587 phasex_steps[COMP_3] = phasex_step; 588 phasex_steps[COMP_1_2] = phasex_step / info->hsub; 589 590 return 0; 591} 592 593static int calc_scaley_steps(struct drm_plane *plane, 594 uint32_t pixel_format, uint32_t src, uint32_t dest, 595 uint32_t phasey_steps[COMP_MAX]) 596{ 597 const struct drm_format_info *info = drm_format_info(pixel_format); 598 struct mdp5_kms *mdp5_kms = get_kms(plane); 599 struct device *dev = mdp5_kms->dev->dev; 600 uint32_t phasey_step; 601 int ret; 602 603 ret = calc_phase_step(src, dest, &phasey_step); 604 if (ret) { 605 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); 606 return ret; 607 } 608 609 phasey_steps[COMP_0] = phasey_step; 610 phasey_steps[COMP_3] = phasey_step; 611 phasey_steps[COMP_1_2] = phasey_step / info->vsub; 612 613 return 0; 614} 615 616static uint32_t get_scale_config(const struct msm_format *format, 617 uint32_t src, uint32_t dst, bool horz) 618{ 619 const struct drm_format_info *info = drm_format_info(format->pixel_format); 620 bool yuv = MSM_FORMAT_IS_YUV(format); 621 bool scaling = yuv ? true : (src != dst); 622 uint32_t sub; 623 uint32_t ya_filter, uv_filter; 624 625 if (!scaling) 626 return 0; 627 628 if (yuv) { 629 sub = horz ? info->hsub : info->vsub; 630 uv_filter = ((src / sub) <= dst) ? 631 SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 632 } 633 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; 634 635 if (horz) 636 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | 637 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | 638 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | 639 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); 640 else 641 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | 642 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | 643 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | 644 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); 645} 646 647static void calc_pixel_ext(const struct msm_format *format, 648 uint32_t src, uint32_t dst, uint32_t phase_step[2], 649 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 650 bool horz) 651{ 652 bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst); 653 int i; 654 655 /* 656 * Note: 657 * We assume here that: 658 * 1. PCMN filter is used for downscale 659 * 2. bilinear filter is used for upscale 660 * 3. we are in a single pipe configuration 661 */ 662 663 for (i = 0; i < COMP_MAX; i++) { 664 pix_ext_edge1[i] = 0; 665 pix_ext_edge2[i] = scaling ? 1 : 0; 666 } 667} 668 669static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, 670 const struct msm_format *format, 671 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], 672 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) 673{ 674 const struct drm_format_info *info = drm_format_info(format->pixel_format); 675 uint32_t lr, tb, req; 676 int i; 677 678 for (i = 0; i < COMP_MAX; i++) { 679 uint32_t roi_w = src_w; 680 uint32_t roi_h = src_h; 681 682 if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) { 683 roi_w /= info->hsub; 684 roi_h /= info->vsub; 685 } 686 687 lr = (pe_left[i] >= 0) ? 688 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : 689 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); 690 691 lr |= (pe_right[i] >= 0) ? 692 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : 693 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); 694 695 tb = (pe_top[i] >= 0) ? 696 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : 697 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); 698 699 tb |= (pe_bottom[i] >= 0) ? 700 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : 701 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); 702 703 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + 704 pe_left[i] + pe_right[i]); 705 706 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + 707 pe_top[i] + pe_bottom[i]); 708 709 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); 710 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); 711 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); 712 713 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, 714 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), 715 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), 716 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), 717 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), 718 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); 719 720 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, 721 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), 722 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), 723 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), 724 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), 725 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); 726 } 727} 728 729struct pixel_ext { 730 int left[COMP_MAX]; 731 int right[COMP_MAX]; 732 int top[COMP_MAX]; 733 int bottom[COMP_MAX]; 734}; 735 736struct phase_step { 737 u32 x[COMP_MAX]; 738 u32 y[COMP_MAX]; 739}; 740 741static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, 742 struct mdp5_hw_pipe *hwpipe, 743 struct drm_framebuffer *fb, 744 struct phase_step *step, 745 struct pixel_ext *pe, 746 u32 scale_config, u32 hdecm, u32 vdecm, 747 bool hflip, bool vflip, 748 int crtc_x, int crtc_y, 749 unsigned int crtc_w, unsigned int crtc_h, 750 u32 src_img_w, u32 src_img_h, 751 u32 src_x, u32 src_y, 752 u32 src_w, u32 src_h) 753{ 754 enum mdp5_pipe pipe = hwpipe->pipe; 755 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; 756 const struct msm_format *format = 757 msm_framebuffer_format(fb); 758 759 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), 760 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | 761 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); 762 763 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), 764 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | 765 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); 766 767 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), 768 MDP5_PIPE_SRC_XY_X(src_x) | 769 MDP5_PIPE_SRC_XY_Y(src_y)); 770 771 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), 772 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | 773 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); 774 775 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), 776 MDP5_PIPE_OUT_XY_X(crtc_x) | 777 MDP5_PIPE_OUT_XY_Y(crtc_y)); 778 779 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), 780 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | 781 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) | 782 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) | 783 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) | 784 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | 785 MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) | 786 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | 787 COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT, 788 MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | 789 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | 790 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); 791 792 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), 793 MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) | 794 MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) | 795 MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) | 796 MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3])); 797 798 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), 799 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | 800 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | 801 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | 802 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); 803 804 /* not using secure mode: */ 805 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); 806 807 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) 808 mdp5_write_pixel_ext(mdp5_kms, pipe, format, 809 src_w, pe->left, pe->right, 810 src_h, pe->top, pe->bottom); 811 812 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { 813 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), 814 step->x[COMP_0]); 815 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), 816 step->y[COMP_0]); 817 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), 818 step->x[COMP_1_2]); 819 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), 820 step->y[COMP_1_2]); 821 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), 822 MDP5_PIPE_DECIMATION_VERT(vdecm) | 823 MDP5_PIPE_DECIMATION_HORZ(hdecm)); 824 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), 825 scale_config); 826 } 827 828 if (hwpipe->caps & MDP_PIPE_CAP_CSC) { 829 if (MSM_FORMAT_IS_YUV(format)) 830 csc_enable(mdp5_kms, pipe, 831 mdp_get_default_csc_cfg(CSC_YUV2RGB)); 832 else 833 csc_disable(mdp5_kms, pipe); 834 } 835 836 set_scanout_locked(mdp5_kms, pipe, fb); 837} 838 839static int mdp5_plane_mode_set(struct drm_plane *plane, 840 struct drm_crtc *crtc, struct drm_framebuffer *fb, 841 struct drm_rect *src, struct drm_rect *dest) 842{ 843 struct drm_plane_state *pstate = plane->state; 844 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; 845 struct mdp5_kms *mdp5_kms = get_kms(plane); 846 enum mdp5_pipe pipe = hwpipe->pipe; 847 struct mdp5_hw_pipe *right_hwpipe; 848 const struct msm_format *format; 849 uint32_t nplanes, config = 0; 850 struct phase_step step = { { 0 } }; 851 struct pixel_ext pe = { { 0 } }; 852 uint32_t hdecm = 0, vdecm = 0; 853 uint32_t pix_format; 854 unsigned int rotation; 855 bool vflip, hflip; 856 int crtc_x, crtc_y; 857 unsigned int crtc_w, crtc_h; 858 uint32_t src_x, src_y; 859 uint32_t src_w, src_h; 860 uint32_t src_img_w, src_img_h; 861 int ret; 862 863 nplanes = fb->format->num_planes; 864 865 /* bad formats should already be rejected: */ 866 if (WARN_ON(nplanes > pipe2nclients(pipe))) 867 return -EINVAL; 868 869 format = msm_framebuffer_format(fb); 870 pix_format = format->pixel_format; 871 872 src_x = src->x1; 873 src_y = src->y1; 874 src_w = drm_rect_width(src); 875 src_h = drm_rect_height(src); 876 877 crtc_x = dest->x1; 878 crtc_y = dest->y1; 879 crtc_w = drm_rect_width(dest); 880 crtc_h = drm_rect_height(dest); 881 882 /* src values are in Q16 fixed point, convert to integer: */ 883 src_x = src_x >> 16; 884 src_y = src_y >> 16; 885 src_w = src_w >> 16; 886 src_h = src_h >> 16; 887 888 src_img_w = min(fb->width, src_w); 889 src_img_h = min(fb->height, src_h); 890 891 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, 892 fb->base.id, src_x, src_y, src_w, src_h, 893 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); 894 895 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; 896 if (right_hwpipe) { 897 /* 898 * if the plane comprises of 2 hw pipes, assume that the width 899 * is split equally across them. The only parameters that varies 900 * between the 2 pipes are src_x and crtc_x 901 */ 902 crtc_w /= 2; 903 src_w /= 2; 904 src_img_w /= 2; 905 } 906 907 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); 908 if (ret) 909 return ret; 910 911 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); 912 if (ret) 913 return ret; 914 915 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { 916 calc_pixel_ext(format, src_w, crtc_w, step.x, 917 pe.left, pe.right, true); 918 calc_pixel_ext(format, src_h, crtc_h, step.y, 919 pe.top, pe.bottom, false); 920 } 921 922 /* TODO calc hdecm, vdecm */ 923 924 /* SCALE is used to both scale and up-sample chroma components */ 925 config |= get_scale_config(format, src_w, crtc_w, true); 926 config |= get_scale_config(format, src_h, crtc_h, false); 927 DBG("scale config = %x", config); 928 929 rotation = drm_rotation_simplify(pstate->rotation, 930 DRM_MODE_ROTATE_0 | 931 DRM_MODE_REFLECT_X | 932 DRM_MODE_REFLECT_Y); 933 hflip = !!(rotation & DRM_MODE_REFLECT_X); 934 vflip = !!(rotation & DRM_MODE_REFLECT_Y); 935 936 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, 937 config, hdecm, vdecm, hflip, vflip, 938 crtc_x, crtc_y, crtc_w, crtc_h, 939 src_img_w, src_img_h, 940 src_x, src_y, src_w, src_h); 941 if (right_hwpipe) 942 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, 943 config, hdecm, vdecm, hflip, vflip, 944 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h, 945 src_img_w, src_img_h, 946 src_x + src_w, src_y, src_w, src_h); 947 948 return ret; 949} 950 951/* 952 * Use this func and the one below only after the atomic state has been 953 * successfully swapped 954 */ 955enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) 956{ 957 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 958 959 if (WARN_ON(!pstate->hwpipe)) 960 return SSPP_NONE; 961 962 return pstate->hwpipe->pipe; 963} 964 965enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) 966{ 967 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 968 969 if (!pstate->r_hwpipe) 970 return SSPP_NONE; 971 972 return pstate->r_hwpipe->pipe; 973} 974 975uint32_t mdp5_plane_get_flush(struct drm_plane *plane) 976{ 977 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); 978 u32 mask; 979 980 if (WARN_ON(!pstate->hwpipe)) 981 return 0; 982 983 mask = pstate->hwpipe->flush_mask; 984 985 if (pstate->r_hwpipe) 986 mask |= pstate->r_hwpipe->flush_mask; 987 988 return mask; 989} 990 991static const uint32_t mdp5_plane_formats[] = { 992 DRM_FORMAT_ARGB8888, 993 DRM_FORMAT_ABGR8888, 994 DRM_FORMAT_RGBA8888, 995 DRM_FORMAT_BGRA8888, 996 DRM_FORMAT_XRGB8888, 997 DRM_FORMAT_XBGR8888, 998 DRM_FORMAT_RGBX8888, 999 DRM_FORMAT_BGRX8888, 1000 DRM_FORMAT_RGB888, 1001 DRM_FORMAT_BGR888, 1002 DRM_FORMAT_RGB565, 1003 DRM_FORMAT_BGR565, 1004 1005 DRM_FORMAT_NV12, 1006 DRM_FORMAT_NV21, 1007 DRM_FORMAT_NV16, 1008 DRM_FORMAT_NV61, 1009 DRM_FORMAT_VYUY, 1010 DRM_FORMAT_UYVY, 1011 DRM_FORMAT_YUYV, 1012 DRM_FORMAT_YVYU, 1013 DRM_FORMAT_YUV420, 1014 DRM_FORMAT_YVU420, 1015}; 1016 1017/* initialize plane */ 1018struct drm_plane *mdp5_plane_init(struct drm_device *dev, 1019 enum drm_plane_type type) 1020{ 1021 struct drm_plane *plane = NULL; 1022 struct mdp5_plane *mdp5_plane; 1023 1024 mdp5_plane = drmm_universal_plane_alloc(dev, struct mdp5_plane, base, 1025 0xff, &mdp5_plane_funcs, 1026 mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats), 1027 NULL, type, NULL); 1028 if (IS_ERR(mdp5_plane)) 1029 return ERR_CAST(mdp5_plane); 1030 1031 plane = &mdp5_plane->base; 1032 1033 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); 1034 1035 mdp5_plane_install_properties(plane, &plane->base); 1036 1037 drm_plane_enable_fb_damage_clips(plane); 1038 1039 return plane; 1040}
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