mdp5_crtc.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   4 * Copyright (C) 2013 Red Hat
   5 * Author: Rob Clark <robdclark@gmail.com>
   6 */
   7
   8#include <linux/sort.h>
   9
  10#include <drm/drm_atomic.h>
  11#include <drm/drm_blend.h>
  12#include <drm/drm_mode.h>
  13#include <drm/drm_crtc.h>
  14#include <drm/drm_flip_work.h>
  15#include <drm/drm_fourcc.h>
  16#include <drm/drm_managed.h>
  17#include <drm/drm_probe_helper.h>
  18#include <drm/drm_vblank.h>
  19
  20#include "mdp5_kms.h"
  21#include "msm_gem.h"
  22
  23#define CURSOR_WIDTH	64
  24#define CURSOR_HEIGHT	64
  25
  26struct mdp5_crtc {
  27	struct drm_crtc base;
  28	int id;
  29	bool enabled;
  30
  31	spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  32
  33	/* if there is a pending flip, these will be non-null: */
  34	struct drm_pending_vblank_event *event;
  35
  36	/* Bits have been flushed at the last commit,
  37	 * used to decide if a vsync has happened since last commit.
  38	 */
  39	u32 flushed_mask;
  40
  41#define PENDING_CURSOR 0x1
  42#define PENDING_FLIP   0x2
  43	atomic_t pending;
  44
  45	/* for unref'ing cursor bo's after scanout completes: */
  46	struct drm_flip_work unref_cursor_work;
  47
  48	struct mdp_irq vblank;
  49	struct mdp_irq err;
  50	struct mdp_irq pp_done;
  51
  52	struct completion pp_completion;
  53
  54	bool lm_cursor_enabled;
  55
  56	struct {
  57		/* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  58		spinlock_t lock;
  59
  60		/* current cursor being scanned out: */
  61		struct drm_gem_object *scanout_bo;
  62		uint64_t iova;
  63		uint32_t width, height;
  64		int x, y;
  65	} cursor;
  66};
  67#define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  68
  69static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc);
  70
  71static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  72{
  73	struct msm_drm_private *priv = crtc->dev->dev_private;
  74	return to_mdp5_kms(to_mdp_kms(priv->kms));
  75}
  76
  77static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  78{
  79	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  80
  81	atomic_or(pending, &mdp5_crtc->pending);
  82	mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  83}
  84
  85static void request_pp_done_pending(struct drm_crtc *crtc)
  86{
  87	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  88	reinit_completion(&mdp5_crtc->pp_completion);
  89}
  90
  91static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
  92{
  93	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
  94	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
  95	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
  96	bool start = !mdp5_cstate->defer_start;
  97
  98	mdp5_cstate->defer_start = false;
  99
 100	DBG("%s: flush=%08x", crtc->name, flush_mask);
 101
 102	return mdp5_ctl_commit(ctl, pipeline, flush_mask, start);
 103}
 104
 105/*
 106 * flush updates, to make sure hw is updated to new scanout fb,
 107 * so that we can safely queue unref to current fb (ie. next
 108 * vblank we know hw is done w/ previous scanout_fb).
 109 */
 110static u32 crtc_flush_all(struct drm_crtc *crtc)
 111{
 112	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 113	struct mdp5_hw_mixer *mixer, *r_mixer;
 114	struct drm_plane *plane;
 115	uint32_t flush_mask = 0;
 116
 117	/* this should not happen: */
 118	if (WARN_ON(!mdp5_cstate->ctl))
 119		return 0;
 120
 121	drm_atomic_crtc_for_each_plane(plane, crtc) {
 122		if (!plane->state->visible)
 123			continue;
 124		flush_mask |= mdp5_plane_get_flush(plane);
 125	}
 126
 127	mixer = mdp5_cstate->pipeline.mixer;
 128	flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm);
 129
 130	r_mixer = mdp5_cstate->pipeline.r_mixer;
 131	if (r_mixer)
 132		flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm);
 133
 134	return crtc_flush(crtc, flush_mask);
 135}
 136
 137/* if file!=NULL, this is preclose potential cancel-flip path */
 138static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 139{
 140	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 141	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 142	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 143	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
 144	struct drm_device *dev = crtc->dev;
 145	struct drm_pending_vblank_event *event;
 146	unsigned long flags;
 147
 148	spin_lock_irqsave(&dev->event_lock, flags);
 149	event = mdp5_crtc->event;
 150	if (event) {
 151		mdp5_crtc->event = NULL;
 152		DBG("%s: send event: %p", crtc->name, event);
 153		drm_crtc_send_vblank_event(crtc, event);
 154	}
 155	spin_unlock_irqrestore(&dev->event_lock, flags);
 156
 157	if (ctl && !crtc->state->enable) {
 158		/* set STAGE_UNUSED for all layers */
 159		mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0);
 160		/* XXX: What to do here? */
 161		/* mdp5_crtc->ctl = NULL; */
 162	}
 163}
 164
 165static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 166{
 167	struct mdp5_crtc *mdp5_crtc =
 168		container_of(work, struct mdp5_crtc, unref_cursor_work);
 169	struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 170	struct msm_kms *kms = &mdp5_kms->base.base;
 171
 172	msm_gem_unpin_iova(val, kms->vm);
 173	drm_gem_object_put(val);
 174}
 175
 176static void mdp5_crtc_flip_cleanup(struct drm_device *dev, void *ptr)
 177{
 178	struct mdp5_crtc *mdp5_crtc = ptr;
 179
 180	drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 181}
 182
 183static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)
 184{
 185	switch (stage) {
 186	case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA;
 187	case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA;
 188	case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA;
 189	case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA;
 190	case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA;
 191	case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA;
 192	case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA;
 193	default:
 194		return 0;
 195	}
 196}
 197
 198/*
 199 * left/right pipe offsets for the stage array used in blend_setup()
 200 */
 201#define PIPE_LEFT	0
 202#define PIPE_RIGHT	1
 203
 204/*
 205 * blend_setup() - blend all the planes of a CRTC
 206 *
 207 * If no base layer is available, border will be enabled as the base layer.
 208 * Otherwise all layers will be blended based on their stage calculated
 209 * in mdp5_crtc_atomic_check.
 210 */
 211static void blend_setup(struct drm_crtc *crtc)
 212{
 213	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 214	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 215	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 216	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 217	struct drm_plane *plane;
 218	struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
 219	const struct msm_format *format;
 220	struct mdp5_hw_mixer *mixer = pipeline->mixer;
 221	uint32_t lm = mixer->lm;
 222	struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
 223	uint32_t r_lm = r_mixer ? r_mixer->lm : 0;
 224	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
 225	uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0;
 226	unsigned long flags;
 227	enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
 228	enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
 229	int i, plane_cnt = 0;
 230	bool bg_alpha_enabled = false;
 231	u32 mixer_op_mode = 0;
 232	u32 val;
 233#define blender(stage)	((stage) - STAGE0)
 234
 235	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 236
 237	/* ctl could be released already when we are shutting down: */
 238	/* XXX: Can this happen now? */
 239	if (!ctl)
 240		goto out;
 241
 242	/* Collect all plane information */
 243	drm_atomic_crtc_for_each_plane(plane, crtc) {
 244		enum mdp5_pipe right_pipe;
 245
 246		if (!plane->state->visible)
 247			continue;
 248
 249		pstate = to_mdp5_plane_state(plane->state);
 250		pstates[pstate->stage] = pstate;
 251		stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
 252		/*
 253		 * if we have a right mixer, stage the same pipe as we
 254		 * have on the left mixer
 255		 */
 256		if (r_mixer)
 257			r_stage[pstate->stage][PIPE_LEFT] =
 258						mdp5_plane_pipe(plane);
 259		/*
 260		 * if we have a right pipe (i.e, the plane comprises of 2
 261		 * hwpipes, then stage the right pipe on the right side of both
 262		 * the layer mixers
 263		 */
 264		right_pipe = mdp5_plane_right_pipe(plane);
 265		if (right_pipe) {
 266			stage[pstate->stage][PIPE_RIGHT] = right_pipe;
 267			r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
 268		}
 269
 270		plane_cnt++;
 271	}
 272
 273	if (!pstates[STAGE_BASE]) {
 274		ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
 275		DBG("Border Color is enabled");
 276	} else if (plane_cnt) {
 277		format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
 278
 279		if (format->alpha_enable)
 280			bg_alpha_enabled = true;
 281	}
 282
 283	/* The reset for blending */
 284	for (i = STAGE0; i <= STAGE_MAX; i++) {
 285		if (!pstates[i])
 286			continue;
 287
 288		format = msm_framebuffer_format(pstates[i]->base.fb);
 289		plane = pstates[i]->base.plane;
 290		blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 291			MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
 292		fg_alpha = pstates[i]->base.alpha >> 8;
 293		bg_alpha = 0xFF - fg_alpha;
 294
 295		if (!format->alpha_enable && bg_alpha_enabled)
 296			mixer_op_mode = 0;
 297		else
 298			mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i);
 299
 300		DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha);
 301
 302		if (format->alpha_enable &&
 303		    pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
 304			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 305				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 306			if (fg_alpha != 0xff) {
 307				bg_alpha = fg_alpha;
 308				blend_op |=
 309					MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 310					MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 311			} else {
 312				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 313			}
 314		} else if (format->alpha_enable &&
 315			   pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
 316			blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) |
 317				MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL);
 318			if (fg_alpha != 0xff) {
 319				bg_alpha = fg_alpha;
 320				blend_op |=
 321				       MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA |
 322				       MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA |
 323				       MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA |
 324				       MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA;
 325			} else {
 326				blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA;
 327			}
 328		}
 329
 330		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
 331				blender(i)), blend_op);
 332		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 333				blender(i)), fg_alpha);
 334		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 335				blender(i)), bg_alpha);
 336		if (r_mixer) {
 337			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
 338					blender(i)), blend_op);
 339			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
 340					blender(i)), fg_alpha);
 341			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
 342					blender(i)), bg_alpha);
 343		}
 344	}
 345
 346	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
 347	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
 348		   val | mixer_op_mode);
 349	if (r_mixer) {
 350		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
 351		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
 352			   val | mixer_op_mode);
 353	}
 354
 355	mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
 356		       ctl_blend_flags);
 357out:
 358	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 359}
 360
 361static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 362{
 363	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 364	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 365	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 366	struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer;
 367	struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer;
 368	uint32_t lm = mixer->lm;
 369	u32 mixer_width, val;
 370	unsigned long flags;
 371	struct drm_display_mode *mode;
 372
 373	if (WARN_ON(!crtc->state))
 374		return;
 375
 376	mode = &crtc->state->adjusted_mode;
 377
 378	DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode));
 379
 380	mixer_width = mode->hdisplay;
 381	if (r_mixer)
 382		mixer_width /= 2;
 383
 384	spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 385	mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
 386			MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
 387			MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 388
 389	/* Assign mixer to LEFT side in source split mode */
 390	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
 391	val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
 392	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
 393
 394	if (r_mixer) {
 395		u32 r_lm = r_mixer->lm;
 396
 397		mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
 398			   MDP5_LM_OUT_SIZE_WIDTH(mixer_width) |
 399			   MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 400
 401		/* Assign mixer to RIGHT side in source split mode */
 402		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
 403		val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT;
 404		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
 405	}
 406
 407	spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 408}
 409
 410static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
 411{
 412	struct drm_device *dev = crtc->dev;
 413	struct drm_encoder *encoder;
 414
 415	drm_for_each_encoder(encoder, dev)
 416		if (encoder->crtc == crtc)
 417			return encoder;
 418
 419	return NULL;
 420}
 421
 422static bool mdp5_crtc_get_scanout_position(struct drm_crtc *crtc,
 423					   bool in_vblank_irq,
 424					   int *vpos, int *hpos,
 425					   ktime_t *stime, ktime_t *etime,
 426					   const struct drm_display_mode *mode)
 427{
 428	unsigned int pipe = crtc->index;
 429	struct drm_encoder *encoder;
 430	int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
 431
 432
 433	encoder = get_encoder_from_crtc(crtc);
 434	if (!encoder) {
 435		DRM_ERROR("no encoder found for crtc %d\n", pipe);
 436		return false;
 437	}
 438
 439	vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
 440	vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
 441
 442	/*
 443	 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
 444	 * the end of VFP. Translate the porch values relative to the line
 445	 * counter positions.
 446	 */
 447
 448	vactive_start = vsw + vbp + 1;
 449
 450	vactive_end = vactive_start + mode->crtc_vdisplay;
 451
 452	/* last scan line before VSYNC */
 453	vfp_end = mode->crtc_vtotal;
 454
 455	if (stime)
 456		*stime = ktime_get();
 457
 458	line = mdp5_encoder_get_linecount(encoder);
 459
 460	if (line < vactive_start)
 461		line -= vactive_start;
 462	else if (line > vactive_end)
 463		line = line - vfp_end - vactive_start;
 464	else
 465		line -= vactive_start;
 466
 467	*vpos = line;
 468	*hpos = 0;
 469
 470	if (etime)
 471		*etime = ktime_get();
 472
 473	return true;
 474}
 475
 476static u32 mdp5_crtc_get_vblank_counter(struct drm_crtc *crtc)
 477{
 478	struct drm_encoder *encoder;
 479
 480	encoder = get_encoder_from_crtc(crtc);
 481	if (!encoder)
 482		return 0;
 483
 484	return mdp5_encoder_get_framecount(encoder);
 485}
 486
 487static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
 488				     struct drm_atomic_state *state)
 489{
 490	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 491	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 492	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 493	struct device *dev = &mdp5_kms->pdev->dev;
 494	unsigned long flags;
 495
 496	DBG("%s", crtc->name);
 497
 498	if (WARN_ON(!mdp5_crtc->enabled))
 499		return;
 500
 501	/* Disable/save vblank irq handling before power is disabled */
 502	drm_crtc_vblank_off(crtc);
 503
 504	if (mdp5_cstate->cmd_mode)
 505		mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 506
 507	mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 508	pm_runtime_put_sync(dev);
 509
 510	if (crtc->state->event && !crtc->state->active) {
 511		WARN_ON(mdp5_crtc->event);
 512		spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
 513		drm_crtc_send_vblank_event(crtc, crtc->state->event);
 514		crtc->state->event = NULL;
 515		spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
 516	}
 517
 518	mdp5_crtc->enabled = false;
 519}
 520
 521static void mdp5_crtc_vblank_on(struct drm_crtc *crtc)
 522{
 523	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 524	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
 525	u32 count;
 526
 527	count = intf->mode == MDP5_INTF_DSI_MODE_COMMAND ? 0 : 0xffffffff;
 528	drm_crtc_set_max_vblank_count(crtc, count);
 529
 530	drm_crtc_vblank_on(crtc);
 531}
 532
 533static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,
 534				    struct drm_atomic_state *state)
 535{
 536	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 537	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 538	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 539	struct device *dev = &mdp5_kms->pdev->dev;
 540
 541	DBG("%s", crtc->name);
 542
 543	if (WARN_ON(mdp5_crtc->enabled))
 544		return;
 545
 546	pm_runtime_get_sync(dev);
 547
 548	if (mdp5_crtc->lm_cursor_enabled) {
 549		/*
 550		 * Restore LM cursor state, as it might have been lost
 551		 * with suspend:
 552		 */
 553		if (mdp5_crtc->cursor.iova) {
 554			unsigned long flags;
 555
 556			spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 557			mdp5_crtc_restore_cursor(crtc);
 558			spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 559
 560			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
 561					    &mdp5_cstate->pipeline, 0, true);
 562		} else {
 563			mdp5_ctl_set_cursor(mdp5_cstate->ctl,
 564					    &mdp5_cstate->pipeline, 0, false);
 565		}
 566	}
 567
 568	/* Restore vblank irq handling after power is enabled */
 569	mdp5_crtc_vblank_on(crtc);
 570
 571	mdp5_crtc_mode_set_nofb(crtc);
 572
 573	mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 574
 575	if (mdp5_cstate->cmd_mode)
 576		mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 577
 578	mdp5_crtc->enabled = true;
 579}
 580
 581static int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc,
 582				    struct drm_crtc_state *new_crtc_state,
 583				    bool need_right_mixer)
 584{
 585	struct mdp5_crtc_state *mdp5_cstate =
 586			to_mdp5_crtc_state(new_crtc_state);
 587	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 588	struct mdp5_interface *intf;
 589	bool new_mixer = false;
 590
 591	new_mixer = !pipeline->mixer;
 592
 593	if ((need_right_mixer && !pipeline->r_mixer) ||
 594	    (!need_right_mixer && pipeline->r_mixer))
 595		new_mixer = true;
 596
 597	if (new_mixer) {
 598		struct mdp5_hw_mixer *old_mixer = pipeline->mixer;
 599		struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer;
 600		u32 caps;
 601		int ret;
 602
 603		caps = MDP_LM_CAP_DISPLAY;
 604		if (need_right_mixer)
 605			caps |= MDP_LM_CAP_PAIR;
 606
 607		ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps,
 608					&pipeline->mixer, need_right_mixer ?
 609					&pipeline->r_mixer : NULL);
 610		if (ret)
 611			return ret;
 612
 613		ret = mdp5_mixer_release(new_crtc_state->state, old_mixer);
 614		if (ret)
 615			return ret;
 616
 617		if (old_r_mixer) {
 618			ret = mdp5_mixer_release(new_crtc_state->state, old_r_mixer);
 619			if (ret)
 620				return ret;
 621
 622			if (!need_right_mixer)
 623				pipeline->r_mixer = NULL;
 624		}
 625	}
 626
 627	/*
 628	 * these should have been already set up in the encoder's atomic
 629	 * check (called by drm_atomic_helper_check_modeset)
 630	 */
 631	intf = pipeline->intf;
 632
 633	mdp5_cstate->err_irqmask = intf2err(intf->num);
 634	mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf);
 635
 636	if ((intf->type == INTF_DSI) &&
 637	    (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 638		mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer);
 639		mdp5_cstate->cmd_mode = true;
 640	} else {
 641		mdp5_cstate->pp_done_irqmask = 0;
 642		mdp5_cstate->cmd_mode = false;
 643	}
 644
 645	return 0;
 646}
 647
 648struct plane_state {
 649	struct drm_plane *plane;
 650	struct mdp5_plane_state *state;
 651};
 652
 653static int pstate_cmp(const void *a, const void *b)
 654{
 655	struct plane_state *pa = (struct plane_state *)a;
 656	struct plane_state *pb = (struct plane_state *)b;
 657	return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos;
 658}
 659
 660/* is there a helper for this? */
 661static bool is_fullscreen(struct drm_crtc_state *cstate,
 662		struct drm_plane_state *pstate)
 663{
 664	return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
 665		((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
 666		((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
 667}
 668
 669static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc,
 670					struct drm_crtc_state *new_crtc_state,
 671					struct drm_plane_state *bpstate)
 672{
 673	struct mdp5_crtc_state *mdp5_cstate =
 674			to_mdp5_crtc_state(new_crtc_state);
 675
 676	/*
 677	 * if we're in source split mode, it's mandatory to have
 678	 * border out on the base stage
 679	 */
 680	if (mdp5_cstate->pipeline.r_mixer)
 681		return STAGE0;
 682
 683	/* if the bottom-most layer is not fullscreen, we need to use
 684	 * it for solid-color:
 685	 */
 686	if (!is_fullscreen(new_crtc_state, bpstate))
 687		return STAGE0;
 688
 689	return STAGE_BASE;
 690}
 691
 692static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 693		struct drm_atomic_state *state)
 694{
 695	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 696									  crtc);
 697	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
 698	struct mdp5_interface *intf = mdp5_cstate->pipeline.intf;
 699	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 700	struct drm_plane *plane;
 701	struct drm_device *dev = crtc->dev;
 702	struct plane_state pstates[STAGE_MAX + 1];
 703	const struct mdp5_cfg_hw *hw_cfg;
 704	const struct drm_plane_state *pstate;
 705	const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 706	bool cursor_plane = false;
 707	bool need_right_mixer = false;
 708	int cnt = 0, i;
 709	int ret;
 710	enum mdp_mixer_stage_id start;
 711
 712	DBG("%s: check", crtc->name);
 713
 714	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
 715		struct mdp5_plane_state *mdp5_pstate =
 716				to_mdp5_plane_state(pstate);
 717
 718		if (!pstate->visible)
 719			continue;
 720
 721		pstates[cnt].plane = plane;
 722		pstates[cnt].state = to_mdp5_plane_state(pstate);
 723
 724		mdp5_pstate->needs_dirtyfb =
 725			intf->mode == MDP5_INTF_DSI_MODE_COMMAND;
 726
 727		/*
 728		 * if any plane on this crtc uses 2 hwpipes, then we need
 729		 * the crtc to have a right hwmixer.
 730		 */
 731		if (pstates[cnt].state->r_hwpipe)
 732			need_right_mixer = true;
 733		cnt++;
 734
 735		if (plane->type == DRM_PLANE_TYPE_CURSOR)
 736			cursor_plane = true;
 737	}
 738
 739	/* bail out early if there aren't any planes */
 740	if (!cnt)
 741		return 0;
 742
 743	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 744
 745	/*
 746	 * we need a right hwmixer if the mode's width is greater than a single
 747	 * LM's max width
 748	 */
 749	if (mode->hdisplay > hw_cfg->lm.max_width)
 750		need_right_mixer = true;
 751
 752	ret = mdp5_crtc_setup_pipeline(crtc, crtc_state, need_right_mixer);
 753	if (ret) {
 754		DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret);
 755		return ret;
 756	}
 757
 758	/* assign a stage based on sorted zpos property */
 759	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 760
 761	/* trigger a warning if cursor isn't the highest zorder */
 762	WARN_ON(cursor_plane &&
 763		(pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));
 764
 765	start = get_start_stage(crtc, crtc_state, &pstates[0].state->base);
 766
 767	/* verify that there are not too many planes attached to crtc
 768	 * and that we don't have conflicting mixer stages:
 769	 */
 770	if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
 771		DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n",
 772			cnt, start);
 773		return -EINVAL;
 774	}
 775
 776	for (i = 0; i < cnt; i++) {
 777		if (cursor_plane && (i == (cnt - 1)))
 778			pstates[i].state->stage = hw_cfg->lm.nb_stages;
 779		else
 780			pstates[i].state->stage = start + i;
 781		DBG("%s: assign pipe %s on stage=%d", crtc->name,
 782				pstates[i].plane->name,
 783				pstates[i].state->stage);
 784	}
 785
 786	return 0;
 787}
 788
 789static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,
 790				   struct drm_atomic_state *state)
 791{
 792	DBG("%s: begin", crtc->name);
 793}
 794
 795static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 796				   struct drm_atomic_state *state)
 797{
 798	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 799	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 800	struct drm_device *dev = crtc->dev;
 801	unsigned long flags;
 802
 803	DBG("%s: event: %p", crtc->name, crtc->state->event);
 804
 805	WARN_ON(mdp5_crtc->event);
 806
 807	spin_lock_irqsave(&dev->event_lock, flags);
 808	mdp5_crtc->event = crtc->state->event;
 809	crtc->state->event = NULL;
 810	spin_unlock_irqrestore(&dev->event_lock, flags);
 811
 812	/*
 813	 * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 814	 * it means we are trying to flush a CRTC whose state is disabled:
 815	 * nothing else needs to be done.
 816	 */
 817	/* XXX: Can this happen now ? */
 818	if (unlikely(!mdp5_cstate->ctl))
 819		return;
 820
 821	blend_setup(crtc);
 822
 823	/* PP_DONE irq is only used by command mode for now.
 824	 * It is better to request pending before FLUSH and START trigger
 825	 * to make sure no pp_done irq missed.
 826	 * This is safe because no pp_done will happen before SW trigger
 827	 * in command mode.
 828	 */
 829	if (mdp5_cstate->cmd_mode)
 830		request_pp_done_pending(crtc);
 831
 832	mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 833
 834	/* XXX are we leaking out state here? */
 835	mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask;
 836	mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask;
 837	mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask;
 838
 839	request_pending(crtc, PENDING_FLIP);
 840}
 841
 842static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 843{
 844	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 845	uint32_t xres = crtc->mode.hdisplay;
 846	uint32_t yres = crtc->mode.vdisplay;
 847
 848	/*
 849	 * Cursor Region Of Interest (ROI) is a plane read from cursor
 850	 * buffer to render. The ROI region is determined by the visibility of
 851	 * the cursor point. In the default Cursor image the cursor point will
 852	 * be at the top left of the cursor image.
 853	 *
 854	 * Without rotation:
 855	 * If the cursor point reaches the right (xres - x < cursor.width) or
 856	 * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 857	 * width and ROI height need to be evaluated to crop the cursor image
 858	 * accordingly.
 859	 * (xres-x) will be new cursor width when x > (xres - cursor.width)
 860	 * (yres-y) will be new cursor height when y > (yres - cursor.height)
 861	 *
 862	 * With rotation:
 863	 * We get negative x and/or y coordinates.
 864	 * (cursor.width - abs(x)) will be new cursor width when x < 0
 865	 * (cursor.height - abs(y)) will be new cursor width when y < 0
 866	 */
 867	if (mdp5_crtc->cursor.x >= 0)
 868		*roi_w = min(mdp5_crtc->cursor.width, xres -
 869			mdp5_crtc->cursor.x);
 870	else
 871		*roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x);
 872	if (mdp5_crtc->cursor.y >= 0)
 873		*roi_h = min(mdp5_crtc->cursor.height, yres -
 874			mdp5_crtc->cursor.y);
 875	else
 876		*roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y);
 877}
 878
 879static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc)
 880{
 881	const struct drm_format_info *info = drm_format_info(DRM_FORMAT_ARGB8888);
 882	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 883	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 884	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 885	const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 886	uint32_t blendcfg, stride;
 887	uint32_t x, y, src_x, src_y, width, height;
 888	uint32_t roi_w, roi_h;
 889	int lm;
 890
 891	assert_spin_locked(&mdp5_crtc->cursor.lock);
 892
 893	lm = mdp5_cstate->pipeline.mixer->lm;
 894
 895	x = mdp5_crtc->cursor.x;
 896	y = mdp5_crtc->cursor.y;
 897	width = mdp5_crtc->cursor.width;
 898	height = mdp5_crtc->cursor.height;
 899
 900	stride = width * info->cpp[0];
 901
 902	get_roi(crtc, &roi_w, &roi_h);
 903
 904	/* If cusror buffer overlaps due to rotation on the
 905	 * upper or left screen border the pixel offset inside
 906	 * the cursor buffer of the ROI is the positive overlap
 907	 * distance.
 908	 */
 909	if (mdp5_crtc->cursor.x < 0) {
 910		src_x = abs(mdp5_crtc->cursor.x);
 911		x = 0;
 912	} else {
 913		src_x = 0;
 914	}
 915	if (mdp5_crtc->cursor.y < 0) {
 916		src_y = abs(mdp5_crtc->cursor.y);
 917		y = 0;
 918	} else {
 919		src_y = 0;
 920	}
 921	DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d",
 922		crtc->name, x, y, roi_w, roi_h, src_x, src_y);
 923
 924	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 925	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 926			MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 927	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 928			MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 929			MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 930	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 931			MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 932			MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 933	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
 934			MDP5_LM_CURSOR_START_XY_Y_START(y) |
 935			MDP5_LM_CURSOR_START_XY_X_START(x));
 936	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
 937			MDP5_LM_CURSOR_XY_SRC_Y(src_y) |
 938			MDP5_LM_CURSOR_XY_SRC_X(src_x));
 939	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
 940			mdp5_crtc->cursor.iova);
 941
 942	blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 943	blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 944	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 945}
 946
 947static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 948		struct drm_file *file, uint32_t handle,
 949		uint32_t width, uint32_t height)
 950{
 951	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 952	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
 953	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
 954	struct drm_device *dev = crtc->dev;
 955	struct mdp5_kms *mdp5_kms = get_kms(crtc);
 956	struct platform_device *pdev = mdp5_kms->pdev;
 957	struct msm_kms *kms = &mdp5_kms->base.base;
 958	struct drm_gem_object *cursor_bo, *old_bo = NULL;
 959	struct mdp5_ctl *ctl;
 960	int ret;
 961	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 962	bool cursor_enable = true;
 963	unsigned long flags;
 964
 965	if (!mdp5_crtc->lm_cursor_enabled) {
 966		dev_warn(dev->dev,
 967			 "cursor_set is deprecated with cursor planes\n");
 968		return -EINVAL;
 969	}
 970
 971	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 972		DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height);
 973		return -EINVAL;
 974	}
 975
 976	ctl = mdp5_cstate->ctl;
 977	if (!ctl)
 978		return -EINVAL;
 979
 980	/* don't support LM cursors when we have source split enabled */
 981	if (mdp5_cstate->pipeline.r_mixer)
 982		return -EINVAL;
 983
 984	if (!handle) {
 985		DBG("Cursor off");
 986		cursor_enable = false;
 987		mdp5_crtc->cursor.iova = 0;
 988		pm_runtime_get_sync(&pdev->dev);
 989		goto set_cursor;
 990	}
 991
 992	cursor_bo = drm_gem_object_lookup(file, handle);
 993	if (!cursor_bo)
 994		return -ENOENT;
 995
 996	ret = msm_gem_get_and_pin_iova(cursor_bo, kms->vm,
 997			&mdp5_crtc->cursor.iova);
 998	if (ret) {
 999		drm_gem_object_put(cursor_bo);
1000		return -EINVAL;
1001	}
1002
1003	pm_runtime_get_sync(&pdev->dev);
1004
1005	spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
1006	old_bo = mdp5_crtc->cursor.scanout_bo;
1007
1008	mdp5_crtc->cursor.scanout_bo = cursor_bo;
1009	mdp5_crtc->cursor.width = width;
1010	mdp5_crtc->cursor.height = height;
1011
1012	mdp5_crtc_restore_cursor(crtc);
1013
1014	spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
1015
1016set_cursor:
1017	ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable);
1018	if (ret) {
1019		DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n",
1020				cursor_enable ? "en" : "dis", ret);
1021		goto end;
1022	}
1023
1024	crtc_flush(crtc, flush_mask);
1025
1026end:
1027	pm_runtime_put_sync(&pdev->dev);
1028	if (old_bo) {
1029		drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
1030		/* enable vblank to complete cursor work: */
1031		request_pending(crtc, PENDING_CURSOR);
1032	}
1033	return ret;
1034}
1035
1036static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1037{
1038	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1039	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1040	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1041	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
1042	struct drm_device *dev = crtc->dev;
1043	uint32_t roi_w;
1044	uint32_t roi_h;
1045	unsigned long flags;
1046
1047	if (!mdp5_crtc->lm_cursor_enabled) {
1048		dev_warn(dev->dev,
1049			 "cursor_move is deprecated with cursor planes\n");
1050		return -EINVAL;
1051	}
1052
1053	/* don't support LM cursors when we have source split enabled */
1054	if (mdp5_cstate->pipeline.r_mixer)
1055		return -EINVAL;
1056
1057	/* In case the CRTC is disabled, just drop the cursor update */
1058	if (unlikely(!crtc->state->enable))
1059		return 0;
1060
1061	/* accept negative x/y coordinates up to maximum cursor overlap */
1062	mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width);
1063	mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height);
1064
1065	get_roi(crtc, &roi_w, &roi_h);
1066
1067	pm_runtime_get_sync(&mdp5_kms->pdev->dev);
1068
1069	spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
1070	mdp5_crtc_restore_cursor(crtc);
1071	spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
1072
1073	crtc_flush(crtc, flush_mask);
1074
1075	pm_runtime_put_sync(&mdp5_kms->pdev->dev);
1076
1077	return 0;
1078}
1079
1080static void
1081mdp5_crtc_atomic_print_state(struct drm_printer *p,
1082			     const struct drm_crtc_state *state)
1083{
1084	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1085	struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
1086	struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
1087
1088	if (WARN_ON(!pipeline))
1089		return;
1090
1091	if (mdp5_cstate->ctl)
1092		drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl));
1093
1094	drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ?
1095			pipeline->mixer->name : "(null)");
1096
1097	if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
1098		drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ?
1099			   pipeline->r_mixer->name : "(null)");
1100
1101	drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
1102}
1103
1104static struct drm_crtc_state *
1105mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
1106{
1107	struct mdp5_crtc_state *mdp5_cstate;
1108
1109	if (WARN_ON(!crtc->state))
1110		return NULL;
1111
1112	mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state),
1113			      sizeof(*mdp5_cstate), GFP_KERNEL);
1114	if (!mdp5_cstate)
1115		return NULL;
1116
1117	__drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base);
1118
1119	return &mdp5_cstate->base;
1120}
1121
1122static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state)
1123{
1124	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state);
1125
1126	__drm_atomic_helper_crtc_destroy_state(state);
1127
1128	kfree(mdp5_cstate);
1129}
1130
1131static void mdp5_crtc_reset(struct drm_crtc *crtc)
1132{
1133	struct mdp5_crtc_state *mdp5_cstate =
1134		kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
1135
1136	if (crtc->state)
1137		mdp5_crtc_destroy_state(crtc, crtc->state);
1138
1139	if (mdp5_cstate)
1140		__drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base);
1141	else
1142		__drm_atomic_helper_crtc_reset(crtc, NULL);
1143}
1144
1145static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
1146	.set_config = drm_atomic_helper_set_config,
1147	.page_flip = drm_atomic_helper_page_flip,
1148	.reset = mdp5_crtc_reset,
1149	.atomic_duplicate_state = mdp5_crtc_duplicate_state,
1150	.atomic_destroy_state = mdp5_crtc_destroy_state,
1151	.atomic_print_state = mdp5_crtc_atomic_print_state,
1152	.get_vblank_counter = mdp5_crtc_get_vblank_counter,
1153	.enable_vblank  = msm_crtc_enable_vblank,
1154	.disable_vblank = msm_crtc_disable_vblank,
1155	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1156};
1157
1158static const struct drm_crtc_funcs mdp5_crtc_funcs = {
1159	.set_config = drm_atomic_helper_set_config,
1160	.page_flip = drm_atomic_helper_page_flip,
1161	.reset = mdp5_crtc_reset,
1162	.atomic_duplicate_state = mdp5_crtc_duplicate_state,
1163	.atomic_destroy_state = mdp5_crtc_destroy_state,
1164	.cursor_set = mdp5_crtc_cursor_set,
1165	.cursor_move = mdp5_crtc_cursor_move,
1166	.atomic_print_state = mdp5_crtc_atomic_print_state,
1167	.get_vblank_counter = mdp5_crtc_get_vblank_counter,
1168	.enable_vblank  = msm_crtc_enable_vblank,
1169	.disable_vblank = msm_crtc_disable_vblank,
1170	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1171};
1172
1173static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
1174	.mode_set_nofb = mdp5_crtc_mode_set_nofb,
1175	.atomic_check = mdp5_crtc_atomic_check,
1176	.atomic_begin = mdp5_crtc_atomic_begin,
1177	.atomic_flush = mdp5_crtc_atomic_flush,
1178	.atomic_enable = mdp5_crtc_atomic_enable,
1179	.atomic_disable = mdp5_crtc_atomic_disable,
1180	.get_scanout_position = mdp5_crtc_get_scanout_position,
1181};
1182
1183static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
1184{
1185	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
1186	struct drm_crtc *crtc = &mdp5_crtc->base;
1187	struct msm_drm_private *priv = crtc->dev->dev_private;
1188	unsigned pending;
1189
1190	mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
1191
1192	pending = atomic_xchg(&mdp5_crtc->pending, 0);
1193
1194	if (pending & PENDING_FLIP) {
1195		complete_flip(crtc, NULL);
1196	}
1197
1198	if (pending & PENDING_CURSOR)
1199		drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->kms->wq);
1200}
1201
1202static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
1203{
1204	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
1205
1206	DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus);
1207}
1208
1209static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
1210{
1211	struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
1212								pp_done);
1213
1214	complete_all(&mdp5_crtc->pp_completion);
1215}
1216
1217static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
1218{
1219	struct drm_device *dev = crtc->dev;
1220	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1221	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1222	int ret;
1223
1224	ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
1225						msecs_to_jiffies(50));
1226	if (ret == 0)
1227		dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
1228				     mdp5_cstate->pipeline.mixer->lm);
1229}
1230
1231static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
1232{
1233	struct drm_device *dev = crtc->dev;
1234	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1235	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1236	struct mdp5_ctl *ctl = mdp5_cstate->ctl;
1237	wait_queue_head_t *queue = drm_crtc_vblank_waitqueue(crtc);
1238	int ret;
1239
1240	/* Should not call this function if crtc is disabled. */
1241	if (!ctl)
1242		return;
1243
1244	ret = drm_crtc_vblank_get(crtc);
1245	if (ret)
1246		return;
1247
1248	ret = wait_event_timeout(*queue,
1249		((mdp5_ctl_get_commit_status(ctl) &
1250		mdp5_crtc->flushed_mask) == 0),
1251		msecs_to_jiffies(50));
1252	if (ret <= 0)
1253		dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
1254
1255	mdp5_crtc->flushed_mask = 0;
1256
1257	drm_crtc_vblank_put(crtc);
1258}
1259
1260uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
1261{
1262	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
1263	return mdp5_crtc->vblank.irqmask;
1264}
1265
1266void mdp5_crtc_set_pipeline(struct drm_crtc *crtc)
1267{
1268	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1269	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1270
1271	/* should this be done elsewhere ? */
1272	mdp_irq_update(&mdp5_kms->base);
1273
1274	mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline);
1275}
1276
1277struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
1278{
1279	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1280
1281	return mdp5_cstate->ctl;
1282}
1283
1284struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc)
1285{
1286	struct mdp5_crtc_state *mdp5_cstate;
1287
1288	if (WARN_ON(!crtc))
1289		return ERR_PTR(-EINVAL);
1290
1291	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1292
1293	return WARN_ON(!mdp5_cstate->pipeline.mixer) ?
1294		ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer;
1295}
1296
1297struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc)
1298{
1299	struct mdp5_crtc_state *mdp5_cstate;
1300
1301	if (WARN_ON(!crtc))
1302		return ERR_PTR(-EINVAL);
1303
1304	mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1305
1306	return &mdp5_cstate->pipeline;
1307}
1308
1309void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
1310{
1311	struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
1312
1313	if (mdp5_cstate->cmd_mode)
1314		mdp5_crtc_wait_for_pp_done(crtc);
1315	else
1316		mdp5_crtc_wait_for_flush_done(crtc);
1317}
1318
1319/* initialize crtc */
1320struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
1321				struct drm_plane *plane,
1322				struct drm_plane *cursor_plane, int id)
1323{
1324	struct drm_crtc *crtc = NULL;
1325	struct mdp5_crtc *mdp5_crtc;
1326	int ret;
1327
1328	mdp5_crtc = drmm_crtc_alloc_with_planes(dev, struct mdp5_crtc, base,
1329						plane, cursor_plane,
1330						cursor_plane ?
1331						&mdp5_crtc_no_lm_cursor_funcs :
1332						&mdp5_crtc_funcs,
1333						NULL);
1334	if (IS_ERR(mdp5_crtc))
1335		return ERR_CAST(mdp5_crtc);
1336
1337	crtc = &mdp5_crtc->base;
1338
1339	mdp5_crtc->id = id;
1340
1341	spin_lock_init(&mdp5_crtc->lm_lock);
1342	spin_lock_init(&mdp5_crtc->cursor.lock);
1343	init_completion(&mdp5_crtc->pp_completion);
1344
1345	mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
1346	mdp5_crtc->err.irq = mdp5_crtc_err_irq;
1347	mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
1348
1349	mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true;
1350
1351	drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
1352			"unref cursor", unref_cursor_worker);
1353	ret = drmm_add_action_or_reset(dev, mdp5_crtc_flip_cleanup, mdp5_crtc);
1354	if (ret)
1355		return ERR_PTR(ret);
1356
1357	drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
1358
1359	return crtc;
1360}