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mdp5_cfg.c

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linux-6.19.14/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c C 
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   4 */
   5
   6#include "mdp5_kms.h"
   7#include "mdp5_cfg.h"
   8
   9struct mdp5_cfg_handler {
  10	int revision;
  11	struct mdp5_cfg config;
  12};
  13
  14/* mdp5_cfg must be exposed (used in mdp5.xml.h) */
  15const struct mdp5_cfg_hw *mdp5_cfg = NULL;
  16
  17static const struct mdp5_cfg_hw msm8x74v1_config = {
  18	.name = "msm8x74v1",
  19	.mdp = {
  20		.count = 1,
  21		.caps = MDP_CAP_SMP |
  22			0,
  23	},
  24	.smp = {
  25		.mmb_count = 22,
  26		.mmb_size = 4096,
  27		.clients = {
  28			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
  29			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
  30			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
  31		},
  32	},
  33	.ctl = {
  34		.count = 5,
  35		.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
  36		.flush_hw_mask = 0x0003ffff,
  37	},
  38	.pipe_vig = {
  39		.count = 3,
  40		.base = { 0x01100, 0x01500, 0x01900 },
  41		.caps = MDP_PIPE_CAP_HFLIP |
  42			MDP_PIPE_CAP_VFLIP |
  43			MDP_PIPE_CAP_SCALE |
  44			MDP_PIPE_CAP_CSC   |
  45			0,
  46	},
  47	.pipe_rgb = {
  48		.count = 3,
  49		.base = { 0x01d00, 0x02100, 0x02500 },
  50		.caps = MDP_PIPE_CAP_HFLIP |
  51			MDP_PIPE_CAP_VFLIP |
  52			MDP_PIPE_CAP_SCALE |
  53			0,
  54	},
  55	.pipe_dma = {
  56		.count = 2,
  57		.base = { 0x02900, 0x02d00 },
  58		.caps = MDP_PIPE_CAP_HFLIP |
  59			MDP_PIPE_CAP_VFLIP |
  60			0,
  61	},
  62	.lm = {
  63		.count = 5,
  64		.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
  65		.instances = {
  66				{ .id = 0, .pp = 0, .dspp = 0,
  67				  .caps = MDP_LM_CAP_DISPLAY, },
  68				{ .id = 1, .pp = 1, .dspp = 1,
  69				  .caps = MDP_LM_CAP_DISPLAY, },
  70				{ .id = 2, .pp = 2, .dspp = 2,
  71				  .caps = MDP_LM_CAP_DISPLAY, },
  72				{ .id = 3, .pp = -1, .dspp = -1,
  73				  .caps = MDP_LM_CAP_WB },
  74				{ .id = 4, .pp = -1, .dspp = -1,
  75				  .caps = MDP_LM_CAP_WB },
  76			     },
  77		.nb_stages = 5,
  78		.max_width = 2048,
  79		.max_height = 0xFFFF,
  80	},
  81	.dspp = {
  82		.count = 3,
  83		.base = { 0x04500, 0x04900, 0x04d00 },
  84	},
  85	.pp = {
  86		.count = 3,
  87		.base = { 0x21a00, 0x21b00, 0x21c00 },
  88	},
  89	.intf = {
  90		.base = { 0x21000, 0x21200, 0x21400, 0x21600 },
  91		.connect = {
  92			[0] = INTF_eDP,
  93			[1] = INTF_DSI,
  94			[2] = INTF_DSI,
  95			[3] = INTF_HDMI,
  96		},
  97	},
  98	.perf = {
  99		.ab_inefficiency = 200,
 100		.ib_inefficiency = 120,
 101		.clk_inefficiency = 125
 102	},
 103	.max_clk = 200000000,
 104};
 105
 106static const struct mdp5_cfg_hw msm8x26_config = {
 107	.name = "msm8x26",
 108	.mdp = {
 109		.count = 1,
 110		.caps = MDP_CAP_SMP |
 111			0,
 112	},
 113	.smp = {
 114		.mmb_count = 7,
 115		.mmb_size = 4096,
 116		.clients = {
 117			[SSPP_VIG0] =  1,
 118			[SSPP_DMA0] = 4,
 119			[SSPP_RGB0] = 7,
 120		},
 121	},
 122	.ctl = {
 123		.count = 2,
 124		.base = { 0x00500, 0x00600 },
 125		.flush_hw_mask = 0x0003ffff,
 126	},
 127	.pipe_vig = {
 128		.count = 1,
 129		.base = { 0x01100 },
 130		.caps = MDP_PIPE_CAP_HFLIP |
 131			MDP_PIPE_CAP_VFLIP |
 132			MDP_PIPE_CAP_SCALE |
 133			MDP_PIPE_CAP_CSC   |
 134			0,
 135	},
 136	.pipe_rgb = {
 137		.count = 1,
 138		.base = { 0x01d00 },
 139		.caps = MDP_PIPE_CAP_HFLIP |
 140			MDP_PIPE_CAP_VFLIP |
 141			MDP_PIPE_CAP_SCALE |
 142			0,
 143	},
 144	.pipe_dma = {
 145		.count = 1,
 146		.base = { 0x02900 },
 147		.caps = MDP_PIPE_CAP_HFLIP |
 148			MDP_PIPE_CAP_VFLIP |
 149			0,
 150	},
 151	.lm = {
 152		.count = 2,
 153		.base = { 0x03100, 0x03d00 },
 154		.instances = {
 155				{ .id = 0, .pp = 0, .dspp = 0,
 156				  .caps = MDP_LM_CAP_DISPLAY, },
 157				{ .id = 1, .pp = -1, .dspp = -1,
 158				  .caps = MDP_LM_CAP_WB },
 159			     },
 160		.nb_stages = 2,
 161		.max_width = 2048,
 162		.max_height = 0xFFFF,
 163	},
 164	.dspp = {
 165		.count = 1,
 166		.base = { 0x04500 },
 167	},
 168	.pp = {
 169		.count = 1,
 170		.base = { 0x21a00 },
 171	},
 172	.intf = {
 173		.base = { 0x00000, 0x21200 },
 174		.connect = {
 175			[0] = INTF_DISABLED,
 176			[1] = INTF_DSI,
 177		},
 178	},
 179	.perf = {
 180		.ab_inefficiency = 100,
 181		.ib_inefficiency = 200,
 182		.clk_inefficiency = 125
 183	},
 184	.max_clk = 200000000,
 185};
 186
 187static const struct mdp5_cfg_hw msm8x74v2_config = {
 188	.name = "msm8x74",
 189	.mdp = {
 190		.count = 1,
 191		.caps = MDP_CAP_SMP |
 192			0,
 193	},
 194	.smp = {
 195		.mmb_count = 22,
 196		.mmb_size = 4096,
 197		.clients = {
 198			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
 199			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 200			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
 201		},
 202	},
 203	.ctl = {
 204		.count = 5,
 205		.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
 206		.flush_hw_mask = 0x0003ffff,
 207	},
 208	.pipe_vig = {
 209		.count = 3,
 210		.base = { 0x01100, 0x01500, 0x01900 },
 211		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 212				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 213				MDP_PIPE_CAP_DECIMATION,
 214	},
 215	.pipe_rgb = {
 216		.count = 3,
 217		.base = { 0x01d00, 0x02100, 0x02500 },
 218		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 219				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 220	},
 221	.pipe_dma = {
 222		.count = 2,
 223		.base = { 0x02900, 0x02d00 },
 224		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 225	},
 226	.lm = {
 227		.count = 5,
 228		.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
 229		.instances = {
 230				{ .id = 0, .pp = 0, .dspp = 0,
 231				  .caps = MDP_LM_CAP_DISPLAY, },
 232				{ .id = 1, .pp = 1, .dspp = 1,
 233				  .caps = MDP_LM_CAP_DISPLAY, },
 234				{ .id = 2, .pp = 2, .dspp = 2,
 235				  .caps = MDP_LM_CAP_DISPLAY, },
 236				{ .id = 3, .pp = -1, .dspp = -1,
 237				  .caps = MDP_LM_CAP_WB, },
 238				{ .id = 4, .pp = -1, .dspp = -1,
 239				  .caps = MDP_LM_CAP_WB, },
 240			     },
 241		.nb_stages = 5,
 242		.max_width = 2048,
 243		.max_height = 0xFFFF,
 244	},
 245	.dspp = {
 246		.count = 3,
 247		.base = { 0x04500, 0x04900, 0x04d00 },
 248	},
 249	.ad = {
 250		.count = 2,
 251		.base = { 0x13000, 0x13200 },
 252	},
 253	.pp = {
 254		.count = 3,
 255		.base = { 0x12c00, 0x12d00, 0x12e00 },
 256	},
 257	.intf = {
 258		.base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
 259		.connect = {
 260			[0] = INTF_eDP,
 261			[1] = INTF_DSI,
 262			[2] = INTF_DSI,
 263			[3] = INTF_HDMI,
 264		},
 265	},
 266	.perf = {
 267		.ab_inefficiency = 200,
 268		.ib_inefficiency = 120,
 269		.clk_inefficiency = 125
 270	},
 271	.max_clk = 320000000,
 272};
 273
 274static const struct mdp5_cfg_hw apq8084_config = {
 275	.name = "apq8084",
 276	.mdp = {
 277		.count = 1,
 278		.caps = MDP_CAP_SMP |
 279			MDP_CAP_SRC_SPLIT |
 280			0,
 281	},
 282	.smp = {
 283		.mmb_count = 44,
 284		.mmb_size = 8192,
 285		.clients = {
 286			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
 287			[SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
 288			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 289			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 290			[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 291		},
 292		.reserved_state[0] = GENMASK(7, 0),	/* first 8 MMBs */
 293		.reserved = {
 294			/* Two SMP blocks are statically tied to RGB pipes: */
 295			[16] = 2, [17] = 2, [18] = 2, [22] = 2,
 296		},
 297	},
 298	.ctl = {
 299		.count = 5,
 300		.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
 301		.flush_hw_mask = 0x003fffff,
 302	},
 303	.pipe_vig = {
 304		.count = 4,
 305		.base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
 306		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 307				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 308				MDP_PIPE_CAP_DECIMATION,
 309	},
 310	.pipe_rgb = {
 311		.count = 4,
 312		.base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
 313		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 314				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 315	},
 316	.pipe_dma = {
 317		.count = 2,
 318		.base = { 0x03100, 0x03500 },
 319		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 320	},
 321	.lm = {
 322		.count = 6,
 323		.base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
 324		.instances = {
 325				{ .id = 0, .pp = 0, .dspp = 0,
 326				  .caps = MDP_LM_CAP_DISPLAY |
 327					  MDP_LM_CAP_PAIR, },
 328				{ .id = 1, .pp = 1, .dspp = 1,
 329				  .caps = MDP_LM_CAP_DISPLAY, },
 330				{ .id = 2, .pp = 2, .dspp = 2,
 331				  .caps = MDP_LM_CAP_DISPLAY |
 332					  MDP_LM_CAP_PAIR, },
 333				{ .id = 3, .pp = -1, .dspp = -1,
 334				  .caps = MDP_LM_CAP_WB, },
 335				{ .id = 4, .pp = -1, .dspp = -1,
 336				  .caps = MDP_LM_CAP_WB, },
 337				{ .id = 5, .pp = 3, .dspp = 3,
 338				  .caps = MDP_LM_CAP_DISPLAY, },
 339			     },
 340		.nb_stages = 5,
 341		.max_width = 2048,
 342		.max_height = 0xFFFF,
 343	},
 344	.dspp = {
 345		.count = 4,
 346		.base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
 347
 348	},
 349	.ad = {
 350		.count = 3,
 351		.base = { 0x13400, 0x13600, 0x13800 },
 352	},
 353	.pp = {
 354		.count = 4,
 355		.base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
 356	},
 357	.intf = {
 358		.base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
 359		.connect = {
 360			[0] = INTF_eDP,
 361			[1] = INTF_DSI,
 362			[2] = INTF_DSI,
 363			[3] = INTF_HDMI,
 364		},
 365	},
 366	.perf = {
 367		.ab_inefficiency = 200,
 368		.ib_inefficiency = 120,
 369		.clk_inefficiency = 105
 370	},
 371	.max_clk = 320000000,
 372};
 373
 374static const struct mdp5_cfg_hw msm8x16_config = {
 375	.name = "msm8x16",
 376	.mdp = {
 377		.count = 1,
 378		.base = { 0x0 },
 379		.caps = MDP_CAP_SMP |
 380			0,
 381	},
 382	.smp = {
 383		.mmb_count = 8,
 384		.mmb_size = 8192,
 385		.clients = {
 386			[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
 387			[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 388		},
 389	},
 390	.ctl = {
 391		.count = 5,
 392		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 393		.flush_hw_mask = 0x4003ffff,
 394	},
 395	.pipe_vig = {
 396		.count = 1,
 397		.base = { 0x04000 },
 398		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 399				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 400				MDP_PIPE_CAP_DECIMATION,
 401	},
 402	.pipe_rgb = {
 403		.count = 2,
 404		.base = { 0x14000, 0x16000 },
 405		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 406				MDP_PIPE_CAP_DECIMATION,
 407	},
 408	.pipe_dma = {
 409		.count = 1,
 410		.base = { 0x24000 },
 411		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 412	},
 413	.lm = {
 414		.count = 2, /* LM0 and LM3 */
 415		.base = { 0x44000, 0x47000 },
 416		.instances = {
 417				{ .id = 0, .pp = 0, .dspp = 0,
 418				  .caps = MDP_LM_CAP_DISPLAY, },
 419				{ .id = 3, .pp = -1, .dspp = -1,
 420				  .caps = MDP_LM_CAP_WB },
 421			     },
 422		.nb_stages = 8,
 423		.max_width = 2048,
 424		.max_height = 0xFFFF,
 425	},
 426	.dspp = {
 427		.count = 1,
 428		.base = { 0x54000 },
 429
 430	},
 431	.intf = {
 432		.base = { 0x00000, 0x6a800 },
 433		.connect = {
 434			[0] = INTF_DISABLED,
 435			[1] = INTF_DSI,
 436		},
 437	},
 438	.perf = {
 439		.ab_inefficiency = 100,
 440		.ib_inefficiency = 200,
 441		.clk_inefficiency = 105
 442	},
 443	.max_clk = 320000000,
 444};
 445
 446static const struct mdp5_cfg_hw msm8x36_config = {
 447	.name = "msm8x36",
 448	.mdp = {
 449		.count = 1,
 450		.base = { 0x0 },
 451		.caps = MDP_CAP_SMP |
 452			0,
 453	},
 454	.smp = {
 455		.mmb_count = 8,
 456		.mmb_size = 10240,
 457		.clients = {
 458			[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
 459			[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 460		},
 461	},
 462	.ctl = {
 463		.count = 3,
 464		.base = { 0x01000, 0x01200, 0x01400 },
 465		.flush_hw_mask = 0x4003ffff,
 466	},
 467	.pipe_vig = {
 468		.count = 1,
 469		.base = { 0x04000 },
 470		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 471				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 472				MDP_PIPE_CAP_DECIMATION,
 473	},
 474	.pipe_rgb = {
 475		.count = 2,
 476		.base = { 0x14000, 0x16000 },
 477		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 478				MDP_PIPE_CAP_DECIMATION,
 479	},
 480	.pipe_dma = {
 481		.count = 1,
 482		.base = { 0x24000 },
 483		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 484	},
 485	.lm = {
 486		.count = 2,
 487		.base = { 0x44000, 0x47000 },
 488		.instances = {
 489				{ .id = 0, .pp = 0, .dspp = 0,
 490				  .caps = MDP_LM_CAP_DISPLAY, },
 491				{ .id = 1, .pp = -1, .dspp = -1,
 492				  .caps = MDP_LM_CAP_WB, },
 493				},
 494		.nb_stages = 8,
 495		.max_width = 2560,
 496		.max_height = 0xFFFF,
 497	},
 498	.pp = {
 499		.count = 1,
 500		.base = { 0x70000 },
 501	},
 502	.ad = {
 503		.count = 1,
 504		.base = { 0x78000 },
 505	},
 506	.dspp = {
 507		.count = 1,
 508		.base = { 0x54000 },
 509	},
 510	.intf = {
 511		.base = { 0x00000, 0x6a800, 0x6b000 },
 512		.connect = {
 513			[0] = INTF_DISABLED,
 514			[1] = INTF_DSI,
 515			[2] = INTF_DSI,
 516		},
 517	},
 518	.perf = {
 519		.ab_inefficiency = 100,
 520		.ib_inefficiency = 200,
 521		.clk_inefficiency = 105
 522	},
 523	.max_clk = 366670000,
 524};
 525
 526static const struct mdp5_cfg_hw msm8x94_config = {
 527	.name = "msm8x94",
 528	.mdp = {
 529		.count = 1,
 530		.caps = MDP_CAP_SMP |
 531			MDP_CAP_SRC_SPLIT |
 532			0,
 533	},
 534	.smp = {
 535		.mmb_count = 44,
 536		.mmb_size = 8192,
 537		.clients = {
 538			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
 539			[SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
 540			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 541			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 542			[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 543		},
 544		.reserved_state[0] = GENMASK(23, 0),	/* first 24 MMBs */
 545		.reserved = {
 546			 [1] = 1,  [4] = 1,  [7] = 1, [19] = 1,
 547			[16] = 5, [17] = 5, [18] = 5, [22] = 5,
 548		},
 549	},
 550	.ctl = {
 551		.count = 5,
 552		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 553		.flush_hw_mask = 0xf0ffffff,
 554	},
 555	.pipe_vig = {
 556		.count = 4,
 557		.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 558		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 559				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 560				MDP_PIPE_CAP_DECIMATION,
 561	},
 562	.pipe_rgb = {
 563		.count = 4,
 564		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 565		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 566				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 567	},
 568	.pipe_dma = {
 569		.count = 2,
 570		.base = { 0x24000, 0x26000 },
 571		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 572	},
 573	.lm = {
 574		.count = 6,
 575		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 576		.instances = {
 577				{ .id = 0, .pp = 0, .dspp = 0,
 578				  .caps = MDP_LM_CAP_DISPLAY |
 579					  MDP_LM_CAP_PAIR, },
 580				{ .id = 1, .pp = 1, .dspp = 1,
 581				  .caps = MDP_LM_CAP_DISPLAY, },
 582				{ .id = 2, .pp = 2, .dspp = 2,
 583				  .caps = MDP_LM_CAP_DISPLAY |
 584					  MDP_LM_CAP_PAIR, },
 585				{ .id = 3, .pp = -1, .dspp = -1,
 586				  .caps = MDP_LM_CAP_WB, },
 587				{ .id = 4, .pp = -1, .dspp = -1,
 588				  .caps = MDP_LM_CAP_WB, },
 589				{ .id = 5, .pp = 3, .dspp = 3,
 590				  .caps = MDP_LM_CAP_DISPLAY, },
 591			     },
 592		.nb_stages = 8,
 593		.max_width = 2048,
 594		.max_height = 0xFFFF,
 595	},
 596	.dspp = {
 597		.count = 4,
 598		.base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
 599
 600	},
 601	.ad = {
 602		.count = 3,
 603		.base = { 0x78000, 0x78800, 0x79000 },
 604	},
 605	.pp = {
 606		.count = 4,
 607		.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
 608	},
 609	.intf = {
 610		.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
 611		.connect = {
 612			[0] = INTF_DISABLED,
 613			[1] = INTF_DSI,
 614			[2] = INTF_DSI,
 615			[3] = INTF_HDMI,
 616		},
 617	},
 618	.perf = {
 619		.ab_inefficiency = 100,
 620		.ib_inefficiency = 100,
 621		.clk_inefficiency = 105
 622	},
 623	.max_clk = 400000000,
 624};
 625
 626static const struct mdp5_cfg_hw msm8x96_config = {
 627	.name = "msm8x96",
 628	.mdp = {
 629		.count = 1,
 630		.caps = MDP_CAP_DSC |
 631			MDP_CAP_CDM |
 632			MDP_CAP_SRC_SPLIT |
 633			0,
 634	},
 635	.ctl = {
 636		.count = 5,
 637		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 638		.flush_hw_mask = 0xf4ffffff,
 639	},
 640	.pipe_vig = {
 641		.count = 4,
 642		.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 643		.caps = MDP_PIPE_CAP_HFLIP	|
 644			MDP_PIPE_CAP_VFLIP	|
 645			MDP_PIPE_CAP_SCALE	|
 646			MDP_PIPE_CAP_CSC	|
 647			MDP_PIPE_CAP_DECIMATION	|
 648			MDP_PIPE_CAP_SW_PIX_EXT	|
 649			0,
 650	},
 651	.pipe_rgb = {
 652		.count = 4,
 653		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 654		.caps = MDP_PIPE_CAP_HFLIP	|
 655			MDP_PIPE_CAP_VFLIP	|
 656			MDP_PIPE_CAP_SCALE	|
 657			MDP_PIPE_CAP_DECIMATION	|
 658			MDP_PIPE_CAP_SW_PIX_EXT	|
 659			0,
 660	},
 661	.pipe_dma = {
 662		.count = 2,
 663		.base = { 0x24000, 0x26000 },
 664		.caps = MDP_PIPE_CAP_HFLIP	|
 665			MDP_PIPE_CAP_VFLIP	|
 666			MDP_PIPE_CAP_SW_PIX_EXT	|
 667			0,
 668	},
 669	.pipe_cursor = {
 670		.count = 2,
 671		.base = { 0x34000, 0x36000 },
 672		.caps = MDP_PIPE_CAP_HFLIP	|
 673			MDP_PIPE_CAP_VFLIP	|
 674			MDP_PIPE_CAP_SW_PIX_EXT	|
 675			MDP_PIPE_CAP_CURSOR	|
 676			0,
 677	},
 678
 679	.lm = {
 680		.count = 6,
 681		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 682		.instances = {
 683				{ .id = 0, .pp = 0, .dspp = 0,
 684				  .caps = MDP_LM_CAP_DISPLAY |
 685					  MDP_LM_CAP_PAIR, },
 686				{ .id = 1, .pp = 1, .dspp = 1,
 687				  .caps = MDP_LM_CAP_DISPLAY, },
 688				{ .id = 2, .pp = 2, .dspp = -1,
 689				  .caps = MDP_LM_CAP_DISPLAY |
 690					  MDP_LM_CAP_PAIR, },
 691				{ .id = 3, .pp = -1, .dspp = -1,
 692				  .caps = MDP_LM_CAP_WB, },
 693				{ .id = 4, .pp = -1, .dspp = -1,
 694				  .caps = MDP_LM_CAP_WB, },
 695				{ .id = 5, .pp = 3, .dspp = -1,
 696				  .caps = MDP_LM_CAP_DISPLAY, },
 697			     },
 698		.nb_stages = 8,
 699		.max_width = 2560,
 700		.max_height = 0xFFFF,
 701	},
 702	.dspp = {
 703		.count = 2,
 704		.base = { 0x54000, 0x56000 },
 705	},
 706	.ad = {
 707		.count = 3,
 708		.base = { 0x78000, 0x78800, 0x79000 },
 709	},
 710	.pp = {
 711		.count = 4,
 712		.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
 713	},
 714	.cdm = {
 715		.count = 1,
 716		.base = { 0x79200 },
 717	},
 718	.dsc = {
 719		.count = 2,
 720		.base = { 0x80000, 0x80400 },
 721	},
 722	.intf = {
 723		.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
 724		.connect = {
 725			[0] = INTF_DISABLED,
 726			[1] = INTF_DSI,
 727			[2] = INTF_DSI,
 728			[3] = INTF_HDMI,
 729		},
 730	},
 731	.perf = {
 732		.ab_inefficiency = 100,
 733		.ib_inefficiency = 200,
 734		.clk_inefficiency = 105
 735	},
 736	.max_clk = 412500000,
 737};
 738
 739static const struct mdp5_cfg_hw msm8x76_config = {
 740	.name = "msm8x76",
 741	.mdp = {
 742		.count = 1,
 743		.caps = MDP_CAP_SMP |
 744			MDP_CAP_DSC |
 745			MDP_CAP_SRC_SPLIT |
 746			0,
 747	},
 748	.ctl = {
 749		.count = 3,
 750		.base = { 0x01000, 0x01200, 0x01400 },
 751		.flush_hw_mask = 0xffffffff,
 752	},
 753	.smp = {
 754		.mmb_count = 10,
 755		.mmb_size = 10240,
 756		.clients = {
 757			[SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
 758			[SSPP_DMA0] = 4,
 759			[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 760		},
 761	},
 762	.pipe_vig = {
 763		.count = 2,
 764		.base = { 0x04000, 0x06000 },
 765		.caps = MDP_PIPE_CAP_HFLIP	|
 766			MDP_PIPE_CAP_VFLIP	|
 767			MDP_PIPE_CAP_SCALE	|
 768			MDP_PIPE_CAP_CSC	|
 769			MDP_PIPE_CAP_DECIMATION	|
 770			MDP_PIPE_CAP_SW_PIX_EXT	|
 771			0,
 772	},
 773	.pipe_rgb = {
 774		.count = 2,
 775		.base = { 0x14000, 0x16000 },
 776		.caps = MDP_PIPE_CAP_HFLIP	|
 777			MDP_PIPE_CAP_VFLIP	|
 778			MDP_PIPE_CAP_DECIMATION	|
 779			MDP_PIPE_CAP_SW_PIX_EXT	|
 780			0,
 781	},
 782	.pipe_dma = {
 783		.count = 1,
 784		.base = { 0x24000 },
 785		.caps = MDP_PIPE_CAP_HFLIP	|
 786			MDP_PIPE_CAP_VFLIP	|
 787			MDP_PIPE_CAP_SW_PIX_EXT	|
 788			0,
 789	},
 790	.pipe_cursor = {
 791		.count = 1,
 792		.base = { 0x440DC },
 793		.caps = MDP_PIPE_CAP_HFLIP	|
 794			MDP_PIPE_CAP_VFLIP	|
 795			MDP_PIPE_CAP_SW_PIX_EXT	|
 796			MDP_PIPE_CAP_CURSOR	|
 797			0,
 798	},
 799	.lm = {
 800		.count = 2,
 801		.base = { 0x44000, 0x45000 },
 802		.instances = {
 803				{ .id = 0, .pp = 0, .dspp = 0,
 804				  .caps = MDP_LM_CAP_DISPLAY, },
 805				{ .id = 1, .pp = -1, .dspp = -1,
 806				  .caps = MDP_LM_CAP_WB },
 807			     },
 808		.nb_stages = 8,
 809		.max_width = 2560,
 810		.max_height = 0xFFFF,
 811	},
 812	.dspp = {
 813		.count = 1,
 814		.base = { 0x54000 },
 815
 816	},
 817	.pp = {
 818		.count = 3,
 819		.base = { 0x70000, 0x70800, 0x72000 },
 820	},
 821	.dsc = {
 822		.count = 2,
 823		.base = { 0x80000, 0x80400 },
 824	},
 825	.intf = {
 826		.base = { 0x6a000, 0x6a800, 0x6b000 },
 827		.connect = {
 828			[0] = INTF_DISABLED,
 829			[1] = INTF_DSI,
 830			[2] = INTF_DSI,
 831		},
 832	},
 833	.max_clk = 360000000,
 834};
 835
 836static const struct mdp5_cfg_hw msm8x53_config = {
 837	.name = "msm8x53",
 838	.mdp = {
 839		.count = 1,
 840		.caps = MDP_CAP_CDM,
 841	},
 842	.ctl = {
 843		.count = 3,
 844		.base = { 0x01000, 0x01200, 0x01400 },
 845		.flush_hw_mask = 0xffffffff,
 846	},
 847	.pipe_vig = {
 848		.count = 1,
 849		.base = { 0x04000 },
 850		.caps = MDP_PIPE_CAP_HFLIP	|
 851			MDP_PIPE_CAP_VFLIP	|
 852			MDP_PIPE_CAP_SCALE	|
 853			MDP_PIPE_CAP_CSC	|
 854			MDP_PIPE_CAP_DECIMATION	|
 855			MDP_PIPE_CAP_SW_PIX_EXT	|
 856			0,
 857	},
 858	.pipe_rgb = {
 859		.count = 2,
 860		.base = { 0x14000, 0x16000 },
 861		.caps = MDP_PIPE_CAP_HFLIP	|
 862			MDP_PIPE_CAP_VFLIP	|
 863			MDP_PIPE_CAP_DECIMATION	|
 864			MDP_PIPE_CAP_SW_PIX_EXT	|
 865			0,
 866	},
 867	.pipe_dma = {
 868		.count = 1,
 869		.base = { 0x24000 },
 870		.caps = MDP_PIPE_CAP_HFLIP	|
 871			MDP_PIPE_CAP_VFLIP	|
 872			MDP_PIPE_CAP_SW_PIX_EXT	|
 873			0,
 874	},
 875	.pipe_cursor = {
 876		.count = 1,
 877		.base = { 0x34000 },
 878		.caps = MDP_PIPE_CAP_HFLIP	|
 879			MDP_PIPE_CAP_VFLIP	|
 880			MDP_PIPE_CAP_SW_PIX_EXT	|
 881			MDP_PIPE_CAP_CURSOR	|
 882			0,
 883	},
 884
 885	.lm = {
 886		.count = 3,
 887		.base = { 0x44000, 0x45000 },
 888		.instances = {
 889				{ .id = 0, .pp = 0, .dspp = 0,
 890				  .caps = MDP_LM_CAP_DISPLAY |
 891					  MDP_LM_CAP_PAIR },
 892				{ .id = 1, .pp = 1, .dspp = -1,
 893				  .caps = MDP_LM_CAP_DISPLAY },
 894			     },
 895		.nb_stages = 5,
 896		.max_width = 2048,
 897		.max_height = 0xFFFF,
 898	},
 899	.dspp = {
 900		.count = 1,
 901		.base = { 0x54000 },
 902
 903	},
 904	.pp = {
 905		.count = 2,
 906		.base = { 0x70000, 0x70800 },
 907	},
 908	.cdm = {
 909		.count = 1,
 910		.base = { 0x79200 },
 911	},
 912	.intf = {
 913		.base = { 0x6a000, 0x6a800, 0x6b000 },
 914		.connect = {
 915			[0] = INTF_DISABLED,
 916			[1] = INTF_DSI,
 917			[2] = INTF_DSI,
 918		},
 919	},
 920	.perf = {
 921		.ab_inefficiency = 100,
 922		.ib_inefficiency = 200,
 923		.clk_inefficiency = 105
 924	},
 925	.max_clk = 400000000,
 926};
 927
 928static const struct mdp5_cfg_hw msm8917_config = {
 929	.name = "msm8917",
 930	.mdp = {
 931		.count = 1,
 932		.caps = MDP_CAP_CDM,
 933	},
 934	.ctl = {
 935		.count = 3,
 936		.base = { 0x01000, 0x01200, 0x01400 },
 937		.flush_hw_mask = 0xffffffff,
 938	},
 939	.pipe_vig = {
 940		.count = 1,
 941		.base = { 0x04000 },
 942		.caps = MDP_PIPE_CAP_HFLIP	|
 943			MDP_PIPE_CAP_VFLIP	|
 944			MDP_PIPE_CAP_SCALE	|
 945			MDP_PIPE_CAP_CSC	|
 946			MDP_PIPE_CAP_DECIMATION	|
 947			MDP_PIPE_CAP_SW_PIX_EXT	|
 948			0,
 949	},
 950	.pipe_rgb = {
 951		.count = 2,
 952		.base = { 0x14000, 0x16000 },
 953		.caps = MDP_PIPE_CAP_HFLIP	|
 954			MDP_PIPE_CAP_VFLIP	|
 955			MDP_PIPE_CAP_DECIMATION	|
 956			MDP_PIPE_CAP_SW_PIX_EXT	|
 957			0,
 958	},
 959	.pipe_dma = {
 960		.count = 1,
 961		.base = { 0x24000 },
 962		.caps = MDP_PIPE_CAP_HFLIP	|
 963			MDP_PIPE_CAP_VFLIP	|
 964			MDP_PIPE_CAP_SW_PIX_EXT	|
 965			0,
 966	},
 967	.pipe_cursor = {
 968		.count = 1,
 969		.base = { 0x34000 },
 970		.caps = MDP_PIPE_CAP_HFLIP	|
 971			MDP_PIPE_CAP_VFLIP	|
 972			MDP_PIPE_CAP_SW_PIX_EXT	|
 973			MDP_PIPE_CAP_CURSOR	|
 974			0,
 975	},
 976
 977	.lm = {
 978		.count = 2,
 979		.base = { 0x44000, 0x45000 },
 980		.instances = {
 981				{ .id = 0, .pp = 0, .dspp = 0,
 982				  .caps = MDP_LM_CAP_DISPLAY, },
 983				{ .id = 1, .pp = -1, .dspp = -1,
 984				  .caps = MDP_LM_CAP_WB },
 985			     },
 986		.nb_stages = 8,
 987		.max_width = 2048,
 988		.max_height = 0xFFFF,
 989	},
 990	.dspp = {
 991		.count = 1,
 992		.base = { 0x54000 },
 993
 994	},
 995	.pp = {
 996		.count = 1,
 997		.base = { 0x70000 },
 998	},
 999	.cdm = {
1000		.count = 1,
1001		.base = { 0x79200 },
1002	},
1003	.intf = {
1004		.base = { 0x6a000, 0x6a800 },
1005		.connect = {
1006			[0] = INTF_DISABLED,
1007			[1] = INTF_DSI,
1008		},
1009	},
1010	.max_clk = 320000000,
1011};
1012
1013static const struct mdp5_cfg_hw msm8937_config = {
1014	.name = "msm8937",
1015	.mdp = {
1016		.count = 1,
1017		.caps = MDP_CAP_CDM,
1018	},
1019	.ctl = {
1020		.count = 3,
1021		.base = { 0x01000, 0x01200, 0x01400 },
1022		.flush_hw_mask = 0xffffffff,
1023	},
1024	.pipe_vig = {
1025		.count = 1,
1026		.base = { 0x04000 },
1027		.caps = MDP_PIPE_CAP_HFLIP	|
1028			MDP_PIPE_CAP_VFLIP	|
1029			MDP_PIPE_CAP_SCALE	|
1030			MDP_PIPE_CAP_CSC	|
1031			MDP_PIPE_CAP_DECIMATION	|
1032			MDP_PIPE_CAP_SW_PIX_EXT	|
1033			0,
1034	},
1035	.pipe_rgb = {
1036		.count = 2,
1037		.base = { 0x14000, 0x16000 },
1038		.caps = MDP_PIPE_CAP_HFLIP	|
1039			MDP_PIPE_CAP_VFLIP	|
1040			MDP_PIPE_CAP_DECIMATION	|
1041			MDP_PIPE_CAP_SW_PIX_EXT	|
1042			0,
1043	},
1044	.pipe_dma = {
1045		.count = 1,
1046		.base = { 0x24000 },
1047		.caps = MDP_PIPE_CAP_HFLIP	|
1048			MDP_PIPE_CAP_VFLIP	|
1049			MDP_PIPE_CAP_SW_PIX_EXT	|
1050			0,
1051	},
1052	.pipe_cursor = {
1053		.count = 1,
1054		.base = { 0x34000 },
1055		.caps = MDP_PIPE_CAP_HFLIP	|
1056			MDP_PIPE_CAP_VFLIP	|
1057			MDP_PIPE_CAP_SW_PIX_EXT	|
1058			MDP_PIPE_CAP_CURSOR	|
1059			0,
1060	},
1061
1062	.lm = {
1063		.count = 2,
1064		.base = { 0x44000, 0x45000 },
1065		.instances = {
1066				{ .id = 0, .pp = 0, .dspp = 0,
1067				  .caps = MDP_LM_CAP_DISPLAY |
1068					  MDP_LM_CAP_PAIR },
1069				{ .id = 1, .pp = 1, .dspp = -1,
1070				  .caps = MDP_LM_CAP_DISPLAY },
1071			     },
1072		.nb_stages = 5,
1073		.max_width = 2048,
1074		.max_height = 0xFFFF,
1075	},
1076	.dspp = {
1077		.count = 1,
1078		.base = { 0x54000 },
1079
1080	},
1081	.pp = {
1082		.count = 2,
1083		.base = { 0x70000, 0x70800 },
1084	},
1085	.cdm = {
1086		.count = 1,
1087		.base = { 0x79200 },
1088	},
1089	.intf = {
1090		.base = { 0x00000, 0x6a800, 0x6b000 },
1091		.connect = {
1092			[0] = INTF_DISABLED,
1093			[1] = INTF_DSI,
1094			[2] = INTF_DSI,
1095		},
1096	},
1097	.max_clk = 320000000,
1098};
1099
1100static const struct mdp5_cfg_hw msm8998_config = {
1101	.name = "msm8998",
1102	.mdp = {
1103		.count = 1,
1104		.caps = MDP_CAP_DSC |
1105			MDP_CAP_CDM |
1106			MDP_CAP_SRC_SPLIT |
1107			0,
1108	},
1109	.ctl = {
1110		.count = 5,
1111		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1112		.flush_hw_mask = 0xf7ffffff,
1113	},
1114	.pipe_vig = {
1115		.count = 4,
1116		.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
1117		.caps = MDP_PIPE_CAP_HFLIP	|
1118			MDP_PIPE_CAP_VFLIP	|
1119			MDP_PIPE_CAP_SCALE	|
1120			MDP_PIPE_CAP_CSC	|
1121			MDP_PIPE_CAP_DECIMATION	|
1122			MDP_PIPE_CAP_SW_PIX_EXT	|
1123			0,
1124	},
1125	.pipe_rgb = {
1126		.count = 4,
1127		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1128		.caps = MDP_PIPE_CAP_HFLIP	|
1129			MDP_PIPE_CAP_VFLIP	|
1130			MDP_PIPE_CAP_SCALE	|
1131			MDP_PIPE_CAP_DECIMATION	|
1132			MDP_PIPE_CAP_SW_PIX_EXT	|
1133			0,
1134	},
1135	.pipe_dma = {
1136		.count = 2, /* driver supports max of 2 currently */
1137		.base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
1138		.caps = MDP_PIPE_CAP_HFLIP	|
1139			MDP_PIPE_CAP_VFLIP	|
1140			MDP_PIPE_CAP_SW_PIX_EXT	|
1141			0,
1142	},
1143	.pipe_cursor = {
1144		.count = 2,
1145		.base = { 0x34000, 0x36000 },
1146		.caps = MDP_PIPE_CAP_HFLIP	|
1147			MDP_PIPE_CAP_VFLIP	|
1148			MDP_PIPE_CAP_SW_PIX_EXT	|
1149			MDP_PIPE_CAP_CURSOR	|
1150			0,
1151	},
1152
1153	.lm = {
1154		.count = 6,
1155		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
1156		.instances = {
1157				{ .id = 0, .pp = 0, .dspp = 0,
1158				  .caps = MDP_LM_CAP_DISPLAY |
1159					  MDP_LM_CAP_PAIR, },
1160				{ .id = 1, .pp = 1, .dspp = 1,
1161				  .caps = MDP_LM_CAP_DISPLAY, },
1162				{ .id = 2, .pp = 2, .dspp = -1,
1163				  .caps = MDP_LM_CAP_DISPLAY |
1164					  MDP_LM_CAP_PAIR, },
1165				{ .id = 3, .pp = -1, .dspp = -1,
1166				  .caps = MDP_LM_CAP_WB, },
1167				{ .id = 4, .pp = -1, .dspp = -1,
1168				  .caps = MDP_LM_CAP_WB, },
1169				{ .id = 5, .pp = 3, .dspp = -1,
1170				  .caps = MDP_LM_CAP_DISPLAY, },
1171			     },
1172		.nb_stages = 8,
1173		.max_width = 2560,
1174		.max_height = 0xFFFF,
1175	},
1176	.dspp = {
1177		.count = 2,
1178		.base = { 0x54000, 0x56000 },
1179	},
1180	.ad = {
1181		.count = 3,
1182		.base = { 0x78000, 0x78800, 0x79000 },
1183	},
1184	.pp = {
1185		.count = 4,
1186		.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
1187	},
1188	.cdm = {
1189		.count = 1,
1190		.base = { 0x79200 },
1191	},
1192	.dsc = {
1193		.count = 2,
1194		.base = { 0x80000, 0x80400 },
1195	},
1196	.intf = {
1197		.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
1198		.connect = {
1199			[0] = INTF_eDP,
1200			[1] = INTF_DSI,
1201			[2] = INTF_DSI,
1202			[3] = INTF_HDMI,
1203		},
1204	},
1205	.max_clk = 412500000,
1206};
1207
1208static const struct mdp5_cfg_hw sdm630_config = {
1209	.name = "sdm630",
1210	.mdp = {
1211		.count = 1,
1212		.caps = MDP_CAP_CDM |
1213			MDP_CAP_SRC_SPLIT |
1214			0,
1215	},
1216	.ctl = {
1217		.count = 5,
1218		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1219		.flush_hw_mask = 0xf4ffffff,
1220	},
1221	.pipe_vig = {
1222		.count = 1,
1223		.base = { 0x04000 },
1224		.caps = MDP_PIPE_CAP_HFLIP	|
1225			MDP_PIPE_CAP_VFLIP	|
1226			MDP_PIPE_CAP_SCALE	|
1227			MDP_PIPE_CAP_CSC	|
1228			MDP_PIPE_CAP_DECIMATION	|
1229			MDP_PIPE_CAP_SW_PIX_EXT	|
1230			0,
1231	},
1232	.pipe_rgb = {
1233		.count = 4,
1234		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1235		.caps = MDP_PIPE_CAP_HFLIP	|
1236			MDP_PIPE_CAP_VFLIP	|
1237			MDP_PIPE_CAP_SCALE	|
1238			MDP_PIPE_CAP_DECIMATION	|
1239			MDP_PIPE_CAP_SW_PIX_EXT	|
1240			0,
1241	},
1242	.pipe_dma = {
1243		.count = 2, /* driver supports max of 2 currently */
1244		.base = { 0x24000, 0x26000, 0x28000 },
1245		.caps = MDP_PIPE_CAP_HFLIP	|
1246			MDP_PIPE_CAP_VFLIP	|
1247			MDP_PIPE_CAP_SW_PIX_EXT	|
1248			0,
1249	},
1250	.pipe_cursor = {
1251		.count = 1,
1252		.base = { 0x34000 },
1253		.caps = MDP_PIPE_CAP_HFLIP	|
1254			MDP_PIPE_CAP_VFLIP	|
1255			MDP_PIPE_CAP_SW_PIX_EXT	|
1256			MDP_PIPE_CAP_CURSOR	|
1257			0,
1258	},
1259
1260	.lm = {
1261		.count = 2,
1262		.base = { 0x44000, 0x46000 },
1263		.instances = {
1264				{ .id = 0, .pp = 0, .dspp = 0,
1265				  .caps = MDP_LM_CAP_DISPLAY |
1266					  MDP_LM_CAP_PAIR, },
1267				{ .id = 1, .pp = 1, .dspp = -1,
1268				  .caps = MDP_LM_CAP_WB, },
1269				},
1270		.nb_stages = 8,
1271		.max_width = 2048,
1272		.max_height = 0xFFFF,
1273	},
1274	.dspp = {
1275		.count = 1,
1276		.base = { 0x54000 },
1277	},
1278	.ad = {
1279		.count = 2,
1280		.base = { 0x78000, 0x78800 },
1281	},
1282	.pp = {
1283		.count = 3,
1284		.base = { 0x70000, 0x71000, 0x72000 },
1285	},
1286	.cdm = {
1287		.count = 1,
1288		.base = { 0x79200 },
1289	},
1290	.intf = {
1291		.base = { 0x6a000, 0x6a800 },
1292		.connect = {
1293			[0] = INTF_DISABLED,
1294			[1] = INTF_DSI,
1295		},
1296	},
1297	.max_clk = 412500000,
1298};
1299
1300static const struct mdp5_cfg_hw sdm660_config = {
1301	.name = "sdm660",
1302	.mdp = {
1303		.count = 1,
1304		.caps = MDP_CAP_DSC |
1305			MDP_CAP_CDM |
1306			MDP_CAP_SRC_SPLIT |
1307			0,
1308	},
1309	.ctl = {
1310		.count = 5,
1311		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1312		.flush_hw_mask = 0xf4ffffff,
1313	},
1314	.pipe_vig = {
1315		.count = 2,
1316		.base = { 0x04000, 0x6000 },
1317		.caps = MDP_PIPE_CAP_HFLIP	|
1318			MDP_PIPE_CAP_VFLIP	|
1319			MDP_PIPE_CAP_SCALE	|
1320			MDP_PIPE_CAP_CSC	|
1321			MDP_PIPE_CAP_DECIMATION	|
1322			MDP_PIPE_CAP_SW_PIX_EXT	|
1323			0,
1324	},
1325	.pipe_rgb = {
1326		.count = 4,
1327		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1328		.caps = MDP_PIPE_CAP_HFLIP	|
1329			MDP_PIPE_CAP_VFLIP	|
1330			MDP_PIPE_CAP_SCALE	|
1331			MDP_PIPE_CAP_DECIMATION	|
1332			MDP_PIPE_CAP_SW_PIX_EXT	|
1333			0,
1334	},
1335	.pipe_dma = {
1336		.count = 2, /* driver supports max of 2 currently */
1337		.base = { 0x24000, 0x26000, 0x28000 },
1338		.caps = MDP_PIPE_CAP_HFLIP	|
1339			MDP_PIPE_CAP_VFLIP	|
1340			MDP_PIPE_CAP_SW_PIX_EXT	|
1341			0,
1342	},
1343	.pipe_cursor = {
1344		.count = 1,
1345		.base = { 0x34000 },
1346		.caps = MDP_PIPE_CAP_HFLIP	|
1347			MDP_PIPE_CAP_VFLIP	|
1348			MDP_PIPE_CAP_SW_PIX_EXT	|
1349			MDP_PIPE_CAP_CURSOR	|
1350			0,
1351	},
1352
1353	.lm = {
1354		.count = 4,
1355		.base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1356		.instances = {
1357				{ .id = 0, .pp = 0, .dspp = 0,
1358				  .caps = MDP_LM_CAP_DISPLAY |
1359					  MDP_LM_CAP_PAIR, },
1360				{ .id = 1, .pp = 1, .dspp = 1,
1361				  .caps = MDP_LM_CAP_DISPLAY, },
1362				{ .id = 2, .pp = 2, .dspp = -1,
1363				  .caps = MDP_LM_CAP_DISPLAY |
1364					  MDP_LM_CAP_PAIR, },
1365				{ .id = 3, .pp = 3, .dspp = -1,
1366				  .caps = MDP_LM_CAP_WB, },
1367				},
1368		.nb_stages = 8,
1369		.max_width = 2560,
1370		.max_height = 0xFFFF,
1371	},
1372	.dspp = {
1373		.count = 2,
1374		.base = { 0x54000, 0x56000 },
1375	},
1376	.ad = {
1377		.count = 2,
1378		.base = { 0x78000, 0x78800 },
1379	},
1380	.pp = {
1381		.count = 5,
1382		.base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1383	},
1384	.cdm = {
1385		.count = 1,
1386		.base = { 0x79200 },
1387	},
1388	.dsc = {
1389		.count = 2,
1390		.base = { 0x80000, 0x80400 },
1391	},
1392	.intf = {
1393		.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1394		.connect = {
1395			[0] = INTF_DISABLED,
1396			[1] = INTF_DSI,
1397			[2] = INTF_DSI,
1398			[3] = INTF_HDMI,
1399		},
1400	},
1401	.max_clk = 412500000,
1402};
1403
1404static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1405	{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
1406	{ .revision = 1, .config = { .hw = &msm8x26_config } },
1407	{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
1408	{ .revision = 3, .config = { .hw = &apq8084_config } },
1409	{ .revision = 6, .config = { .hw = &msm8x16_config } },
1410	{ .revision = 8, .config = { .hw = &msm8x36_config } },
1411	{ .revision = 9, .config = { .hw = &msm8x94_config } },
1412	{ .revision = 7, .config = { .hw = &msm8x96_config } },
1413	{ .revision = 11, .config = { .hw = &msm8x76_config } },
1414	{ .revision = 14, .config = { .hw = &msm8937_config } },
1415	{ .revision = 15, .config = { .hw = &msm8917_config } },
1416	{ .revision = 16, .config = { .hw = &msm8x53_config } },
1417};
1418
1419static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1420	{ .revision = 0, .config = { .hw = &msm8998_config } },
1421	{ .revision = 2, .config = { .hw = &sdm660_config } },
1422	{ .revision = 3, .config = { .hw = &sdm630_config } },
1423};
1424
1425const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1426{
1427	return cfg_handler->config.hw;
1428}
1429
1430struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1431{
1432	return &cfg_handler->config;
1433}
1434
1435int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1436{
1437	return cfg_handler->revision;
1438}
1439
1440struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1441		uint32_t major, uint32_t minor)
1442{
1443	struct drm_device *dev = mdp5_kms->dev;
1444	struct mdp5_cfg_handler *cfg_handler;
1445	const struct mdp5_cfg_handler *cfg_handlers;
1446	int i, num_handlers;
1447
1448	cfg_handler = devm_kzalloc(dev->dev, sizeof(*cfg_handler), GFP_KERNEL);
1449	if (unlikely(!cfg_handler)) {
1450		return ERR_PTR(-ENOMEM);
1451	}
1452
1453	switch (major) {
1454	case 1:
1455		cfg_handlers = cfg_handlers_v1;
1456		num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1457		break;
1458	case 3:
1459		cfg_handlers = cfg_handlers_v3;
1460		num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1461		break;
1462	default:
1463		DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1464				major, minor);
1465		return ERR_PTR(-ENXIO);
1466	}
1467
1468	/* only after mdp5_cfg global pointer's init can we access the hw */
1469	for (i = 0; i < num_handlers; i++) {
1470		if (cfg_handlers[i].revision != minor)
1471			continue;
1472		mdp5_cfg = cfg_handlers[i].config.hw;
1473
1474		break;
1475	}
1476	if (unlikely(!mdp5_cfg)) {
1477		DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1478				major, minor);
1479		return ERR_PTR(-ENXIO);
1480	}
1481
1482	cfg_handler->revision = minor;
1483	cfg_handler->config.hw = mdp5_cfg;
1484
1485	DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1486
1487	return cfg_handler;
1488}
~/ Read-only file preview.