mdp4_dsi_encoder.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2014, Inforce Computing. All rights reserved.
  5 *
  6 * Author: Vinay Simha <vinaysimha@inforcecomputing.com>
  7 */
  8
  9#include <drm/drm_crtc.h>
 10#include <drm/drm_probe_helper.h>
 11
 12#include "mdp4_kms.h"
 13
 14#ifdef CONFIG_DRM_MSM_DSI
 15
 16struct mdp4_dsi_encoder {
 17	struct drm_encoder base;
 18	struct drm_panel *panel;
 19	bool enabled;
 20};
 21#define to_mdp4_dsi_encoder(x) container_of(x, struct mdp4_dsi_encoder, base)
 22
 23static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
 24{
 25	struct msm_drm_private *priv = encoder->dev->dev_private;
 26	return to_mdp4_kms(to_mdp_kms(priv->kms));
 27}
 28
 29static void mdp4_dsi_encoder_mode_set(struct drm_encoder *encoder,
 30				      struct drm_display_mode *mode,
 31				      struct drm_display_mode *adjusted_mode)
 32{
 33	struct mdp4_kms *mdp4_kms = get_kms(encoder);
 34	uint32_t dsi_hsync_skew, vsync_period, vsync_len, ctrl_pol;
 35	uint32_t display_v_start, display_v_end;
 36	uint32_t hsync_start_x, hsync_end_x;
 37
 38	mode = adjusted_mode;
 39
 40	DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
 41
 42	ctrl_pol = 0;
 43	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 44		ctrl_pol |= MDP4_DSI_CTRL_POLARITY_HSYNC_LOW;
 45	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 46		ctrl_pol |= MDP4_DSI_CTRL_POLARITY_VSYNC_LOW;
 47	/* probably need to get DATA_EN polarity from panel.. */
 48
 49	dsi_hsync_skew = 0;  /* get this from panel? */
 50
 51	hsync_start_x = (mode->htotal - mode->hsync_start);
 52	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
 53
 54	vsync_period = mode->vtotal * mode->htotal;
 55	vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
 56	display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dsi_hsync_skew;
 57	display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_skew - 1;
 58
 59	mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL,
 60			MDP4_DSI_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
 61			MDP4_DSI_HSYNC_CTRL_PERIOD(mode->htotal));
 62	mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period);
 63	mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len);
 64	mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL,
 65			MDP4_DSI_DISPLAY_HCTRL_START(hsync_start_x) |
 66			MDP4_DSI_DISPLAY_HCTRL_END(hsync_end_x));
 67	mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start);
 68	mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end);
 69
 70	mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol);
 71	mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR,
 72			MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY |
 73			MDP4_DSI_UNDERFLOW_CLR_COLOR(0xff));
 74	mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL,
 75			MDP4_DSI_ACTIVE_HCTL_START(0) |
 76			MDP4_DSI_ACTIVE_HCTL_END(0));
 77	mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_SKEW, dsi_hsync_skew);
 78	mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0);
 79	mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VSTART, 0);
 80	mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0);
 81}
 82
 83static void mdp4_dsi_encoder_disable(struct drm_encoder *encoder)
 84{
 85	struct mdp4_dsi_encoder *mdp4_dsi_encoder = to_mdp4_dsi_encoder(encoder);
 86	struct mdp4_kms *mdp4_kms = get_kms(encoder);
 87
 88	if (!mdp4_dsi_encoder->enabled)
 89		return;
 90
 91	mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 92
 93	/*
 94	 * Wait for a vsync so we know the ENABLE=0 latched before
 95	 * the (connector) source of the vsync's gets disabled,
 96	 * otherwise we end up in a funny state if we re-enable
 97	 * before the disable latches, which results that some of
 98	 * the settings changes for the new modeset (like new
 99	 * scanout buffer) don't latch properly..
100	 */
101	mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_PRIMARY_VSYNC);
102
103	mdp4_dsi_encoder->enabled = false;
104}
105
106static void mdp4_dsi_encoder_enable(struct drm_encoder *encoder)
107{
108	struct mdp4_dsi_encoder *mdp4_dsi_encoder = to_mdp4_dsi_encoder(encoder);
109	struct mdp4_kms *mdp4_kms = get_kms(encoder);
110
111	if (mdp4_dsi_encoder->enabled)
112		return;
113
114	mdp4_crtc_set_config(encoder->crtc,
115			MDP4_DMA_CONFIG_PACK_ALIGN_MSB |
116			MDP4_DMA_CONFIG_DEFLKR_EN |
117			MDP4_DMA_CONFIG_DITHER_EN |
118			MDP4_DMA_CONFIG_R_BPC(BPC8) |
119			MDP4_DMA_CONFIG_G_BPC(BPC8) |
120			MDP4_DMA_CONFIG_B_BPC(BPC8) |
121			MDP4_DMA_CONFIG_PACK(0x21));
122
123	mdp4_crtc_set_intf(encoder->crtc, INTF_DSI_VIDEO, 0);
124
125	mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 1);
126
127	mdp4_dsi_encoder->enabled = true;
128}
129
130static const struct drm_encoder_helper_funcs mdp4_dsi_encoder_helper_funcs = {
131	.mode_set = mdp4_dsi_encoder_mode_set,
132	.disable = mdp4_dsi_encoder_disable,
133	.enable = mdp4_dsi_encoder_enable,
134};
135
136/* initialize encoder */
137struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
138{
139	struct drm_encoder *encoder;
140	struct mdp4_dsi_encoder *mdp4_dsi_encoder;
141
142	mdp4_dsi_encoder = drmm_encoder_alloc(dev, struct mdp4_dsi_encoder, base,
143					      NULL, DRM_MODE_ENCODER_DSI, NULL);
144	if (IS_ERR(mdp4_dsi_encoder))
145		return ERR_CAST(mdp4_dsi_encoder);
146
147	encoder = &mdp4_dsi_encoder->base;
148
149	drm_encoder_helper_add(encoder, &mdp4_dsi_encoder_helper_funcs);
150
151	return encoder;
152}
153#endif /* CONFIG_DRM_MSM_DSI */