dpu_rm.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef __DPU_RM_H__
  7#define __DPU_RM_H__
  8
  9#include <linux/list.h>
 10
 11#include "msm_kms.h"
 12#include "dpu_hw_top.h"
 13
 14struct dpu_global_state;
 15
 16/**
 17 * struct dpu_rm - DPU dynamic hardware resource manager
 18 * @pingpong_blks: array of pingpong hardware resources
 19 * @mixer_blks: array of layer mixer hardware resources
 20 * @ctl_blks: array of ctl hardware resources
 21 * @hw_intf: array of intf hardware resources
 22 * @hw_wb: array of wb hardware resources
 23 * @hw_cwb: array of cwb hardware resources
 24 * @dspp_blks: array of dspp hardware resources
 25 * @hw_sspp: array of sspp hardware resources
 26 * @cdm_blk: cdm hardware resource
 27 * @has_legacy_ctls: DPU uses pre-ACTIVE CTL blocks.
 28 */
 29struct dpu_rm {
 30	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
 31	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
 32	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
 33	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
 34	struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
 35	struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0];
 36	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
 37	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
 38	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
 39	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
 40	struct dpu_hw_blk *cdm_blk;
 41	bool has_legacy_ctls;
 42};
 43
 44struct dpu_rm_sspp_requirements {
 45	bool yuv;
 46	bool scale;
 47	bool rot90;
 48};
 49
 50/**
 51 * struct msm_display_topology - defines a display topology pipeline
 52 * @num_lm:       number of layer mixers used
 53 * @num_intf:     number of interfaces the panel is mounted on
 54 * @num_dspp:     number of dspp blocks used
 55 * @num_dsc:      number of Display Stream Compression (DSC) blocks used
 56 * @num_cdm:      indicates how many outputs are requesting cdm block for
 57 *                    this display topology
 58 * @cwb_enabled:  indicates whether CWB is enabled for this display topology
 59 */
 60struct msm_display_topology {
 61	u32 num_lm;
 62	u32 num_intf;
 63	u32 num_dspp;
 64	u32 num_dsc;
 65	int num_cdm;
 66	bool cwb_enabled;
 67};
 68
 69int dpu_rm_init(struct drm_device *dev,
 70		struct dpu_rm *rm,
 71		const struct dpu_mdss_cfg *cat,
 72		const struct qcom_ubwc_cfg_data *mdss_data,
 73		void __iomem *mmio);
 74
 75int dpu_rm_reserve(struct dpu_rm *rm,
 76		struct dpu_global_state *global_state,
 77		struct drm_crtc *crtc,
 78		struct msm_display_topology *topology);
 79
 80void dpu_rm_release(struct dpu_global_state *global_state,
 81		struct drm_crtc *crtc);
 82
 83struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm,
 84					struct dpu_global_state *global_state,
 85					struct drm_crtc *crtc,
 86					struct dpu_rm_sspp_requirements *reqs);
 87
 88void dpu_rm_release_all_sspp(struct dpu_global_state *global_state,
 89			     struct drm_crtc *crtc);
 90
 91int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
 92	struct dpu_global_state *global_state, struct drm_crtc *crtc,
 93	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
 94
 95void dpu_rm_print_state(struct drm_printer *p,
 96			const struct dpu_global_state *global_state);
 97
 98/**
 99 * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
100 * @rm: DPU Resource Manager handle
101 * @intf_idx: INTF's index
102 */
103static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
104{
105	return rm->hw_intf[intf_idx - INTF_0];
106}
107
108/**
109 * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
110 * @rm: DPU Resource Manager handle
111 * @wb_idx: WB index
112 */
113static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
114{
115	return rm->hw_wb[wb_idx - WB_0];
116}
117
118/**
119 * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
120 * @rm: DPU Resource Manager handle
121 * @sspp_idx: SSPP index
122 */
123static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
124{
125	return rm->hw_sspp[sspp_idx - SSPP_NONE];
126}
127
128#endif /* __DPU_RM_H__ */
129