dpu_hw_util.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_HW_UTIL_H
  8#define _DPU_HW_UTIL_H
  9
 10#include <linux/io.h>
 11#include <linux/slab.h>
 12#include "dpu_hw_mdss.h"
 13#include "dpu_hw_catalog.h"
 14
 15#define REG_MASK(n)                     ((BIT(n)) - 1)
 16#define MISR_FRAME_COUNT                0x1
 17#define MISR_CTRL_ENABLE                BIT(8)
 18#define MISR_CTRL_STATUS                BIT(9)
 19#define MISR_CTRL_STATUS_CLEAR          BIT(10)
 20#define MISR_CTRL_FREE_RUN_MASK         BIT(31)
 21
 22#define TO_S15D16(_x_)((_x_) << 7)
 23
 24#define MDP_TICK_COUNT                    16
 25#define XO_CLK_RATE                       19200
 26#define MS_TICKS_IN_SEC                   1000
 27
 28#define CALCULATE_WD_LOAD_VALUE(fps) \
 29	((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
 30
 31extern const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L;
 32extern const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L;
 33extern const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l;
 34
 35/*
 36 * This is the common struct maintained by each sub block
 37 * for mapping the register offsets in this block to the
 38 * absoulute IO address
 39 * @blk_addr:     hw block register mapped address
 40 * @log_mask:     log mask for this block
 41 */
 42struct dpu_hw_blk_reg_map {
 43	void __iomem *blk_addr;
 44	u32 log_mask;
 45};
 46
 47/**
 48 * struct dpu_hw_blk - opaque hardware block object
 49 */
 50struct dpu_hw_blk {
 51	/* opaque */
 52};
 53
 54/**
 55 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
 56 * @enable:         detail enhancer enable/disable
 57 * @sharpen_level1: sharpening strength for noise
 58 * @sharpen_level2: sharpening strength for signal
 59 * @ clip:          clip shift
 60 * @ limit:         limit value
 61 * @ thr_quiet:     quiet threshold
 62 * @ thr_dieout:    dieout threshold
 63 * @ thr_high:      low threshold
 64 * @ thr_high:      high threshold
 65 * @ prec_shift:    precision shift
 66 * @ adjust_a:      A-coefficients for mapping curve
 67 * @ adjust_b:      B-coefficients for mapping curve
 68 * @ adjust_c:      C-coefficients for mapping curve
 69 */
 70struct dpu_hw_scaler3_de_cfg {
 71	u32 enable;
 72	int16_t sharpen_level1;
 73	int16_t sharpen_level2;
 74	uint16_t clip;
 75	uint16_t limit;
 76	uint16_t thr_quiet;
 77	uint16_t thr_dieout;
 78	uint16_t thr_low;
 79	uint16_t thr_high;
 80	uint16_t prec_shift;
 81	int16_t adjust_a[DPU_MAX_DE_CURVES];
 82	int16_t adjust_b[DPU_MAX_DE_CURVES];
 83	int16_t adjust_c[DPU_MAX_DE_CURVES];
 84};
 85
 86
 87/**
 88 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
 89 * @enable:        scaler enable
 90 * @dir_en:        direction detection block enable
 91 * @ init_phase_x: horizontal initial phase
 92 * @ phase_step_x: horizontal phase step
 93 * @ init_phase_y: vertical initial phase
 94 * @ phase_step_y: vertical phase step
 95 * @ preload_x:    horizontal preload value
 96 * @ preload_y:    vertical preload value
 97 * @ src_width:    source width
 98 * @ src_height:   source height
 99 * @ dst_width:    destination width
100 * @ dst_height:   destination height
101 * @ y_rgb_filter_cfg: y/rgb plane filter configuration
102 * @ uv_filter_cfg: uv plane filter configuration
103 * @ alpha_filter_cfg: alpha filter configuration
104 * @ blend_cfg:    blend coefficients configuration
105 * @ lut_flag:     scaler LUT update flags
106 *                 0x1 swap LUT bank
107 *                 0x2 update 2D filter LUT
108 *                 0x4 update y circular filter LUT
109 *                 0x8 update uv circular filter LUT
110 *                 0x10 update y separable filter LUT
111 *                 0x20 update uv separable filter LUT
112 * @ dir_lut_idx:  2D filter LUT index
113 * @ y_rgb_cir_lut_idx: y circular filter LUT index
114 * @ uv_cir_lut_idx: uv circular filter LUT index
115 * @ y_rgb_sep_lut_idx: y circular filter LUT index
116 * @ uv_sep_lut_idx: uv separable filter LUT index
117 * @ dir_lut:      pointer to 2D LUT
118 * @ cir_lut:      pointer to circular filter LUT
119 * @ sep_lut:      pointer to separable filter LUT
120 * @ de: detail enhancer configuration
121 * @ dir_weight:   Directional weight
122 */
123struct dpu_hw_scaler3_cfg {
124	u32 enable;
125	u32 dir_en;
126	int32_t init_phase_x[DPU_MAX_PLANES];
127	int32_t phase_step_x[DPU_MAX_PLANES];
128	int32_t init_phase_y[DPU_MAX_PLANES];
129	int32_t phase_step_y[DPU_MAX_PLANES];
130
131	u32 preload_x[DPU_MAX_PLANES];
132	u32 preload_y[DPU_MAX_PLANES];
133	u32 src_width[DPU_MAX_PLANES];
134	u32 src_height[DPU_MAX_PLANES];
135
136	u32 dst_width;
137	u32 dst_height;
138
139	u32 y_rgb_filter_cfg;
140	u32 uv_filter_cfg;
141	u32 alpha_filter_cfg;
142	u32 blend_cfg;
143
144	u32 lut_flag;
145	u32 dir_lut_idx;
146
147	u32 y_rgb_cir_lut_idx;
148	u32 uv_cir_lut_idx;
149	u32 y_rgb_sep_lut_idx;
150	u32 uv_sep_lut_idx;
151	u32 *dir_lut;
152	size_t dir_len;
153	u32 *cir_lut;
154	size_t cir_len;
155	u32 *sep_lut;
156	size_t sep_len;
157
158	/*
159	 * Detail enhancer settings
160	 */
161	struct dpu_hw_scaler3_de_cfg de;
162
163	u32 dir_weight;
164};
165
166/**
167 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
168 * @num_ext_pxls_lr: Number of total horizontal pixels
169 * @num_ext_pxls_tb: Number of total vertical lines
170 * @left_ftch:       Number of extra pixels to overfetch from left
171 * @right_ftch:      Number of extra pixels to overfetch from right
172 * @top_ftch:        Number of extra lines to overfetch from top
173 * @btm_ftch:        Number of extra lines to overfetch from bottom
174 * @left_rpt:        Number of extra pixels to repeat from left
175 * @right_rpt:       Number of extra pixels to repeat from right
176 * @top_rpt:         Number of extra lines to repeat from top
177 * @btm_rpt:         Number of extra lines to repeat from bottom
178 */
179struct dpu_drm_pix_ext_v1 {
180	/*
181	 * Number of pixels ext in left, right, top and bottom direction
182	 * for all color components.
183	 */
184	int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
185	int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
186
187	/*
188	 * Number of pixels needs to be overfetched in left, right, top
189	 * and bottom directions from source image for scaling.
190	 */
191	int32_t left_ftch[DPU_MAX_PLANES];
192	int32_t right_ftch[DPU_MAX_PLANES];
193	int32_t top_ftch[DPU_MAX_PLANES];
194	int32_t btm_ftch[DPU_MAX_PLANES];
195	/*
196	 * Number of pixels needs to be repeated in left, right, top and
197	 * bottom directions for scaling.
198	 */
199	int32_t left_rpt[DPU_MAX_PLANES];
200	int32_t right_rpt[DPU_MAX_PLANES];
201	int32_t top_rpt[DPU_MAX_PLANES];
202	int32_t btm_rpt[DPU_MAX_PLANES];
203
204};
205
206/**
207 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
208 * @enable:         Enables/disables detail enhancer
209 * @sharpen_level1: Sharpening strength for noise
210 * @sharpen_level2: Sharpening strength for context
211 * @clip:           Clip coefficient
212 * @limit:          Detail enhancer limit factor
213 * @thr_quiet:      Quite zone threshold
214 * @thr_dieout:     Die-out zone threshold
215 * @thr_low:        Linear zone left threshold
216 * @thr_high:       Linear zone right threshold
217 * @prec_shift:     Detail enhancer precision
218 * @adjust_a:       Mapping curves A coefficients
219 * @adjust_b:       Mapping curves B coefficients
220 * @adjust_c:       Mapping curves C coefficients
221 */
222struct dpu_drm_de_v1 {
223	uint32_t enable;
224	int16_t sharpen_level1;
225	int16_t sharpen_level2;
226	uint16_t clip;
227	uint16_t limit;
228	uint16_t thr_quiet;
229	uint16_t thr_dieout;
230	uint16_t thr_low;
231	uint16_t thr_high;
232	uint16_t prec_shift;
233	int16_t adjust_a[DPU_MAX_DE_CURVES];
234	int16_t adjust_b[DPU_MAX_DE_CURVES];
235	int16_t adjust_c[DPU_MAX_DE_CURVES];
236};
237
238/**
239 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
240 * @enable:            Scaler enable
241 * @dir_en:            Detail enhancer enable
242 * @pe:                Pixel extension settings
243 * @horz_decimate:     Horizontal decimation factor
244 * @vert_decimate:     Vertical decimation factor
245 * @init_phase_x:      Initial scaler phase values for x
246 * @phase_step_x:      Phase step values for x
247 * @init_phase_y:      Initial scaler phase values for y
248 * @phase_step_y:      Phase step values for y
249 * @preload_x:         Horizontal preload value
250 * @preload_y:         Vertical preload value
251 * @src_width:         Source width
252 * @src_height:        Source height
253 * @dst_width:         Destination width
254 * @dst_height:        Destination height
255 * @y_rgb_filter_cfg:  Y/RGB plane filter configuration
256 * @uv_filter_cfg:     UV plane filter configuration
257 * @alpha_filter_cfg:  Alpha filter configuration
258 * @blend_cfg:         Selection of blend coefficients
259 * @lut_flag:          LUT configuration flags
260 * @dir_lut_idx:       2d 4x4 LUT index
261 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
262 * @uv_cir_lut_idx:    UV circular LUT index
263 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
264 * @uv_sep_lut_idx:    UV separable LUT index
265 * @de:                Detail enhancer settings
266 */
267struct dpu_drm_scaler_v2 {
268	/*
269	 * General definitions
270	 */
271	uint32_t enable;
272	uint32_t dir_en;
273
274	/*
275	 * Pix ext settings
276	 */
277	struct dpu_drm_pix_ext_v1 pe;
278
279	/*
280	 * Decimation settings
281	 */
282	uint32_t horz_decimate;
283	uint32_t vert_decimate;
284
285	/*
286	 * Phase settings
287	 */
288	int32_t init_phase_x[DPU_MAX_PLANES];
289	int32_t phase_step_x[DPU_MAX_PLANES];
290	int32_t init_phase_y[DPU_MAX_PLANES];
291	int32_t phase_step_y[DPU_MAX_PLANES];
292
293	uint32_t preload_x[DPU_MAX_PLANES];
294	uint32_t preload_y[DPU_MAX_PLANES];
295	uint32_t src_width[DPU_MAX_PLANES];
296	uint32_t src_height[DPU_MAX_PLANES];
297
298	uint32_t dst_width;
299	uint32_t dst_height;
300
301	uint32_t y_rgb_filter_cfg;
302	uint32_t uv_filter_cfg;
303	uint32_t alpha_filter_cfg;
304	uint32_t blend_cfg;
305
306	uint32_t lut_flag;
307	uint32_t dir_lut_idx;
308
309	/* for Y(RGB) and UV planes*/
310	uint32_t y_rgb_cir_lut_idx;
311	uint32_t uv_cir_lut_idx;
312	uint32_t y_rgb_sep_lut_idx;
313	uint32_t uv_sep_lut_idx;
314
315	/*
316	 * Detail enhancer settings
317	 */
318	struct dpu_drm_de_v1 de;
319};
320
321/**
322 * struct dpu_hw_qos_cfg: pipe QoS configuration
323 * @danger_lut: LUT for generate danger level based on fill level
324 * @safe_lut: LUT for generate safe level based on fill level
325 * @creq_lut: LUT for generate creq level based on fill level
326 * @creq_vblank: creq value generated to vbif during vertical blanking
327 * @danger_vblank: danger value generated during vertical blanking
328 * @vblank_en: enable creq_vblank and danger_vblank during vblank
329 * @danger_safe_en: enable danger safe generation
330 */
331struct dpu_hw_qos_cfg {
332	u32 danger_lut;
333	u32 safe_lut;
334	u64 creq_lut;
335	bool danger_safe_en;
336};
337
338u32 *dpu_hw_util_get_log_mask_ptr(void);
339
340void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
341		u32 reg_off,
342		u32 val,
343		const char *name);
344int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
345
346#define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
347#define DPU_REG_READ(c, off) dpu_reg_read(c, off)
348
349void *dpu_hw_util_get_dir(void);
350
351void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
352		struct dpu_hw_scaler3_cfg *scaler3_cfg,
353		u32 scaler_offset, u32 scaler_version,
354		const struct msm_format *format);
355
356void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
357		u32 csc_reg_off,
358		const struct dpu_csc_cfg *data, bool csc10);
359
360void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
361		   const struct msm_format *fmt, bool enable);
362
363u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
364		u32 total_fl);
365
366void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
367			   bool qos_8lvl,
368			   const struct dpu_hw_qos_cfg *cfg);
369
370void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
371		u32 misr_ctrl_offset, u8 input_sel);
372
373int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
374		u32 misr_ctrl_offset,
375		u32 misr_signature_offset,
376		u32 *misr_value);
377
378bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,
379			   const struct dpu_clk_ctrl_reg *clk_ctrl_reg,
380			   bool enable);
381
382#endif /* _DPU_HW_UTIL_H */