dpu_hw_sspp.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  3 */
  4
  5#ifndef _DPU_HW_SSPP_H
  6#define _DPU_HW_SSPP_H
  7
  8#include "dpu_hw_catalog.h"
  9#include "dpu_hw_mdss.h"
 10#include "dpu_hw_util.h"
 11#include "dpu_formats.h"
 12
 13struct dpu_hw_sspp;
 14
 15#define DPU_SSPP_MAX_PITCH_SIZE		0xffff
 16
 17/*
 18 * Flags
 19 */
 20#define DPU_SSPP_FLIP_LR		BIT(0)
 21#define DPU_SSPP_FLIP_UD		BIT(1)
 22#define DPU_SSPP_SOURCE_ROTATED_90	BIT(2)
 23#define DPU_SSPP_ROT_90			BIT(3)
 24#define DPU_SSPP_SOLID_FILL		BIT(4)
 25
 26/*
 27 * Component indices
 28 */
 29enum {
 30	DPU_SSPP_COMP_0,
 31	DPU_SSPP_COMP_1_2,
 32	DPU_SSPP_COMP_2,
 33	DPU_SSPP_COMP_3,
 34
 35	DPU_SSPP_COMP_MAX
 36};
 37
 38/**
 39 * enum dpu_sspp_multirect_index - multirect mode
 40 * @DPU_SSPP_RECT_SOLO: multirect disabled
 41 * @DPU_SSPP_RECT_0: rect0 of a multirect pipe
 42 * @DPU_SSPP_RECT_1: rect1 of a multirect pipe
 43 *
 44 * Note: HW supports multirect with either RECT0 or
 45 * RECT1. Considering no benefit of such configs over
 46 * SOLO mode and to keep the plane management simple,
 47 * we dont support single rect multirect configs.
 48 */
 49enum dpu_sspp_multirect_index {
 50	DPU_SSPP_RECT_SOLO = 0,
 51	DPU_SSPP_RECT_0,
 52	DPU_SSPP_RECT_1,
 53};
 54
 55enum dpu_sspp_multirect_mode {
 56	DPU_SSPP_MULTIRECT_NONE = 0,
 57	DPU_SSPP_MULTIRECT_PARALLEL,
 58	DPU_SSPP_MULTIRECT_TIME_MX,
 59};
 60
 61enum {
 62	DPU_FRAME_LINEAR,
 63	DPU_FRAME_TILE_A4X,
 64	DPU_FRAME_TILE_A5X,
 65};
 66
 67enum dpu_hw_filter {
 68	DPU_SCALE_FILTER_NEAREST = 0,
 69	DPU_SCALE_FILTER_BIL,
 70	DPU_SCALE_FILTER_PCMN,
 71	DPU_SCALE_FILTER_CA,
 72	DPU_SCALE_FILTER_MAX
 73};
 74
 75enum dpu_hw_filter_alpa {
 76	DPU_SCALE_ALPHA_PIXEL_REP,
 77	DPU_SCALE_ALPHA_BIL
 78};
 79
 80enum dpu_hw_filter_yuv {
 81	DPU_SCALE_2D_4X4,
 82	DPU_SCALE_2D_CIR,
 83	DPU_SCALE_1D_SEP,
 84	DPU_SCALE_BIL
 85};
 86
 87struct dpu_hw_sharp_cfg {
 88	u32 strength;
 89	u32 edge_thr;
 90	u32 smooth_thr;
 91	u32 noise_thr;
 92};
 93
 94struct dpu_hw_pixel_ext {
 95	/* scaling factors are enabled for this input layer */
 96	uint8_t enable_pxl_ext;
 97
 98	int init_phase_x[DPU_MAX_PLANES];
 99	int phase_step_x[DPU_MAX_PLANES];
100	int init_phase_y[DPU_MAX_PLANES];
101	int phase_step_y[DPU_MAX_PLANES];
102
103	/*
104	 * Number of pixels extension in left, right, top and bottom direction
105	 * for all color components. This pixel value for each color component
106	 * should be sum of fetch + repeat pixels.
107	 */
108	int num_ext_pxls_left[DPU_MAX_PLANES];
109	int num_ext_pxls_right[DPU_MAX_PLANES];
110	int num_ext_pxls_top[DPU_MAX_PLANES];
111	int num_ext_pxls_btm[DPU_MAX_PLANES];
112
113	/*
114	 * Number of pixels needs to be overfetched in left, right, top and
115	 * bottom directions from source image for scaling.
116	 */
117	int left_ftch[DPU_MAX_PLANES];
118	int right_ftch[DPU_MAX_PLANES];
119	int top_ftch[DPU_MAX_PLANES];
120	int btm_ftch[DPU_MAX_PLANES];
121
122	/*
123	 * Number of pixels needs to be repeated in left, right, top and
124	 * bottom directions for scaling.
125	 */
126	int left_rpt[DPU_MAX_PLANES];
127	int right_rpt[DPU_MAX_PLANES];
128	int top_rpt[DPU_MAX_PLANES];
129	int btm_rpt[DPU_MAX_PLANES];
130
131	uint32_t roi_w[DPU_MAX_PLANES];
132	uint32_t roi_h[DPU_MAX_PLANES];
133
134	/*
135	 * Filter type to be used for scaling in horizontal and vertical
136	 * directions
137	 */
138	enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
139	enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
140
141};
142
143/**
144 * struct dpu_sw_pipe_cfg : software pipe configuration
145 * @src_rect:  src ROI, caller takes into account the different operations
146 *             such as decimation, flip etc to program this field
147 * @dst_rect: destination ROI.
148 * @rotation: simplified drm rotation hint
149 */
150struct dpu_sw_pipe_cfg {
151	struct drm_rect src_rect;
152	struct drm_rect dst_rect;
153	unsigned int rotation;
154};
155
156/**
157 * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
158 * @size: size to prefill in bytes, or zero to disable
159 * @time: time to prefill in usec, or zero to disable
160 */
161struct dpu_hw_pipe_ts_cfg {
162	u64 size;
163	u64 time;
164};
165
166/**
167 * struct dpu_sw_pipe - software pipe description
168 * @sspp:      backing SSPP pipe
169 * @multirect_index:     index of the rectangle of SSPP
170 * @multirect_mode:      parallel or time multiplex multirect mode
171 */
172struct dpu_sw_pipe {
173	struct dpu_hw_sspp *sspp;
174	enum dpu_sspp_multirect_index multirect_index;
175	enum dpu_sspp_multirect_mode multirect_mode;
176};
177
178/**
179 * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
180 * Caller must call the init function to get the pipe context for each pipe
181 * Assumption is these functions will be called after clocks are enabled
182 */
183struct dpu_hw_sspp_ops {
184	/**
185	 * @setup_format: setup pixel format cropping rectangle, flip
186	 * @pipe: Pointer to software pipe context
187	 * @cfg: Pointer to pipe config structure
188	 * @flags: Extra flags for format config
189	 */
190	void (*setup_format)(struct dpu_sw_pipe *pipe,
191			     const struct msm_format *fmt, u32 flags);
192
193	/**
194	 * @setup_rects: setup pipe ROI rectangles
195	 * @pipe: Pointer to software pipe context
196	 * @cfg: Pointer to pipe config structure
197	 */
198	void (*setup_rects)(struct dpu_sw_pipe *pipe,
199			    struct dpu_sw_pipe_cfg *cfg);
200
201	/**
202	 * @setup_pe: setup pipe pixel extension
203	 * @ctx: Pointer to pipe context
204	 * @pe_ext: Pointer to pixel ext settings
205	 */
206	void (*setup_pe)(struct dpu_hw_sspp *ctx,
207			struct dpu_hw_pixel_ext *pe_ext);
208
209	/**
210	 * @setup_sourceaddress: setup pipe source addresses
211	 * @pipe: Pointer to software pipe context
212	 * @layout: format layout information for programming buffer to hardware
213	 */
214	void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx,
215				    struct dpu_hw_fmt_layout *layout);
216
217	/**
218	 * @setup_csc: setup color space coversion
219	 * @ctx: Pointer to pipe context
220	 * @data: Pointer to config structure
221	 */
222	void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data);
223
224	/**
225	 * @setup_solidfill: enable/disable colorfill
226	 * @pipe: Pointer to software pipe context
227	 * @const_color: Fill color value
228	 * @flags: Pipe flags
229	 */
230	void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color);
231
232	/**
233	 * @setup_multirect: setup multirect configuration
234	 * @pipe: Pointer to software pipe context
235	 */
236
237	void (*setup_multirect)(struct dpu_sw_pipe *pipe);
238
239	/**
240	 * @setup_sharpening: setup sharpening
241	 * @ctx: Pointer to pipe context
242	 * @cfg: Pointer to config structure
243	 */
244	void (*setup_sharpening)(struct dpu_hw_sspp *ctx,
245			struct dpu_hw_sharp_cfg *cfg);
246
247	/**
248	 * @setup_qos_lut: setup QoS LUTs
249	 * @ctx: Pointer to pipe context
250	 * @cfg: LUT configuration
251	 */
252	void (*setup_qos_lut)(struct dpu_hw_sspp *ctx,
253			struct dpu_hw_qos_cfg *cfg);
254
255	/**
256	 * @setup_qos_ctrl: setup QoS control
257	 * @ctx: Pointer to pipe context
258	 * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT
259	 */
260	void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx,
261			       bool danger_safe_en);
262
263	/**
264	 * @setup_clk_force_ctrl: setup clock force control
265	 * @ctx: Pointer to pipe context
266	 * @enable: enable clock force if true
267	 */
268	bool (*setup_clk_force_ctrl)(struct dpu_hw_sspp *ctx,
269				     bool enable);
270
271	/**
272	 * @setup_histogram: setup histograms
273	 * @ctx: Pointer to pipe context
274	 * @cfg: Pointer to histogram configuration
275	 */
276	void (*setup_histogram)(struct dpu_hw_sspp *ctx,
277			void *cfg);
278
279	/**
280	 * @setup_scaler: setup scaler
281	 * @scaler3_cfg: Pointer to scaler configuration
282	 * @format: pixel format parameters
283	 */
284	void (*setup_scaler)(struct dpu_hw_sspp *ctx,
285		struct dpu_hw_scaler3_cfg *scaler3_cfg,
286		const struct msm_format *format);
287
288	/**
289	 * @setup_cdp: setup client driven prefetch
290	 * @pipe: Pointer to software pipe context
291	 * @fmt: format used by the sw pipe
292	 * @enable: whether the CDP should be enabled for this pipe
293	 */
294	void (*setup_cdp)(struct dpu_sw_pipe *pipe,
295			  const struct msm_format *fmt,
296			  bool enable);
297};
298
299/**
300 * struct dpu_hw_sspp - pipe description
301 * @base: hardware block base structure
302 * @hw: block hardware details
303 * @ubwc: UBWC configuration data
304 * @idx: pipe index
305 * @cap: pointer to layer_cfg
306 * @mdss_ver: MDSS version info to use for feature checks
307 * @ops: pointer to operations possible for this pipe
308 */
309struct dpu_hw_sspp {
310	struct dpu_hw_blk base;
311	struct dpu_hw_blk_reg_map hw;
312	const struct qcom_ubwc_cfg_data *ubwc;
313
314	/* Pipe */
315	enum dpu_sspp idx;
316	const struct dpu_sspp_cfg *cap;
317
318	const struct dpu_mdss_version *mdss_ver;
319
320	/* Ops */
321	struct dpu_hw_sspp_ops ops;
322};
323
324struct dpu_kms;
325
326struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
327				     const struct dpu_sspp_cfg *cfg,
328				     void __iomem *addr,
329				     const struct qcom_ubwc_cfg_data *mdss_data,
330				     const struct dpu_mdss_version *mdss_rev);
331
332int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
333			      struct dentry *entry);
334
335#endif /*_DPU_HW_SSPP_H */
336