dpu_hw_dsc.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (c) 2020-2022, Linaro Limited
 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved
 5 */
 6
 7#ifndef _DPU_HW_DSC_H
 8#define _DPU_HW_DSC_H
 9
10#include <drm/display/drm_dsc.h>
11
12#define DSC_MODE_SPLIT_PANEL            BIT(0)
13#define DSC_MODE_MULTIPLEX              BIT(1)
14#define DSC_MODE_VIDEO                  BIT(2)
15
16struct dpu_hw_dsc;
17
18/**
19 * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
20 * Assumption is these functions will be called after clocks are enabled
21 */
22struct dpu_hw_dsc_ops {
23	/**
24	 * @dsc_disable: disable dsc
25	 * @hw_dsc: Pointer to dsc context
26	 */
27	void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
28
29	/**
30	 * @dsc_config: configures dsc encoder
31	 * @hw_dsc: Pointer to dsc context
32	 * @dsc: panel dsc parameters
33	 * @mode: dsc topology mode to be set
34	 * @initial_lines: amount of initial lines to be used
35	 */
36	void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
37			   struct drm_dsc_config *dsc,
38			   u32 mode,
39			   u32 initial_lines);
40
41	/**
42	 * @dsc_config_thresh: programs panel thresholds
43	 * @hw_dsc: Pointer to dsc context
44	 * @dsc: panel dsc parameters
45	 */
46	void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
47				  struct drm_dsc_config *dsc);
48
49	/**
50	 * @dsc_bind_pingpong_blk: binds pixel output from a DSC block
51	 * to a pingpong block
52	 */
53	void (*dsc_bind_pingpong_blk)(struct dpu_hw_dsc *hw_dsc,
54				  enum dpu_pingpong pp);
55};
56
57struct dpu_hw_dsc {
58	struct dpu_hw_blk base;
59	struct dpu_hw_blk_reg_map hw;
60
61	/* dsc */
62	enum dpu_dsc idx;
63	const struct dpu_dsc_cfg *caps;
64
65	/* ops */
66	struct dpu_hw_dsc_ops ops;
67};
68
69struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
70				   const struct dpu_dsc_cfg *cfg,
71				   void __iomem *addr,
72				   const struct dpu_mdss_version *mdss_ver);
73
74struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
75				       const struct dpu_dsc_cfg *cfg,
76				       void __iomem *addr);
77
78static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
79{
80	return container_of(hw, struct dpu_hw_dsc, base);
81}
82
83#endif /* _DPU_HW_DSC_H */