dpu_hw_ctl.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef _DPU_HW_CTL_H
  7#define _DPU_HW_CTL_H
  8
  9#include "dpu_hw_mdss.h"
 10#include "dpu_hw_util.h"
 11#include "dpu_hw_catalog.h"
 12#include "dpu_hw_sspp.h"
 13
 14/**
 15 * enum dpu_ctl_mode_sel: Interface mode selection
 16 * @DPU_CTL_MODE_SEL_VID:    Video mode interface
 17 * @DPU_CTL_MODE_SEL_CMD:    Command mode interface
 18 */
 19enum dpu_ctl_mode_sel {
 20	DPU_CTL_MODE_SEL_VID = 0,
 21	DPU_CTL_MODE_SEL_CMD
 22};
 23
 24struct dpu_hw_ctl;
 25/**
 26 * struct dpu_hw_stage_cfg - blending stage cfg
 27 * @stage : SSPP_ID at each stage
 28 * @multirect_index: index of the rectangle of SSPP.
 29 */
 30struct dpu_hw_stage_cfg {
 31	enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
 32	enum dpu_sspp_multirect_index multirect_index
 33					[DPU_STAGE_MAX][PIPES_PER_STAGE];
 34};
 35
 36/**
 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
 38 * @intf :                 Interface id
 39 * @intf_master:           Master interface id in the dual pipe topology
 40 * @wb:                    Writeback mode
 41 * @mode_3d:               3d mux configuration
 42 * @merge_3d:              3d merge block used
 43 * @intf_mode_sel:         Interface mode, cmd / vid
 44 * @cdm:                   CDM block used
 45 * @stream_sel:            Stream selection for multi-stream interfaces
 46 * @dsc:                   DSC BIT masks used
 47 * @cwb:                   CWB BIT masks used
 48 */
 49struct dpu_hw_intf_cfg {
 50	enum dpu_intf intf;
 51	enum dpu_intf intf_master;
 52	enum dpu_wb wb;
 53	enum dpu_3d_blend_mode mode_3d;
 54	enum dpu_merge_3d merge_3d;
 55	enum dpu_ctl_mode_sel intf_mode_sel;
 56	enum dpu_cdm cdm;
 57	int stream_sel;
 58	unsigned int cwb;
 59	unsigned int dsc;
 60};
 61
 62/**
 63 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
 64 * Assumption is these functions will be called after clocks are enabled
 65 */
 66struct dpu_hw_ctl_ops {
 67	/**
 68	 * @trigger_start: kickoff hw operation for Sw controlled interfaces
 69	 * DSI cmd mode and WB interface are SW controlled
 70	 * @ctx       : ctl path ctx pointer
 71	 */
 72	void (*trigger_start)(struct dpu_hw_ctl *ctx);
 73
 74	/**
 75	 * @is_started: check if the ctl is started
 76	 * @ctx       : ctl path ctx pointer
 77	 * @Return: true if started, false if stopped
 78	 */
 79	bool (*is_started)(struct dpu_hw_ctl *ctx);
 80
 81	/**
 82	 * @trigger_pending: kickoff prepare is in progress hw operation for sw
 83	 * controlled interfaces: DSI cmd mode and WB interface
 84	 * are SW controlled
 85	 * @ctx       : ctl path ctx pointer
 86	 */
 87	void (*trigger_pending)(struct dpu_hw_ctl *ctx);
 88
 89	/**
 90	 * @clear_pending_flush: Clear the value of the cached pending_flush_mask
 91	 * No effect on hardware.
 92	 * Required to be implemented.
 93	 * @ctx       : ctl path ctx pointer
 94	 */
 95	void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
 96
 97	/**
 98	 * @get_pending_flush: Query the value of the cached pending_flush_mask
 99	 * No effect on hardware
100	 * @ctx       : ctl path ctx pointer
101	 */
102	u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
103
104	/**
105	 * @update_pending_flush: OR in the given flushbits to the cached
106	 * pending_flush_mask.
107	 * No effect on hardware
108	 * @ctx       : ctl path ctx pointer
109	 * @flushbits : module flushmask
110	 */
111	void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
112		u32 flushbits);
113
114	/**
115	 * @update_pending_flush_wb: OR in the given flushbits to the
116	 * cached pending_(wb_)flush_mask.
117	 * No effect on hardware
118	 * @ctx       : ctl path ctx pointer
119	 * @blk       : writeback block index
120	 */
121	void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx,
122		enum dpu_wb blk);
123
124	/**
125	 * @update_pending_flush_cwb: OR in the given flushbits to the
126	 * cached pending_(cwb_)flush_mask.
127	 * No effect on hardware
128	 * @ctx       : ctl path ctx pointer
129	 * @blk       : concurrent writeback block index
130	 */
131	void (*update_pending_flush_cwb)(struct dpu_hw_ctl *ctx,
132		enum dpu_cwb blk);
133
134	/**
135	 * @update_pending_flush_intf: OR in the given flushbits to the
136	 * cached pending_(intf_)flush_mask.
137	 * No effect on hardware
138	 * @ctx       : ctl path ctx pointer
139	 * @blk       : interface block index
140	 */
141	void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
142		enum dpu_intf blk);
143
144	/**
145	 * @update_pending_flush_periph: OR in the given flushbits to the
146	 * cached pending_(periph_)flush_mask.
147	 * No effect on hardware
148	 * @ctx       : ctl path ctx pointer
149	 * @blk       : interface block index
150	 */
151	void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx,
152					    enum dpu_intf blk);
153
154	/**
155	 * @update_pending_flush_merge_3d: OR in the given flushbits to the
156	 * cached pending_(merge_3d_)flush_mask.
157	 * No effect on hardware
158	 * @ctx       : ctl path ctx pointer
159	 * @blk       : interface block index
160	 */
161	void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
162		enum dpu_merge_3d blk);
163
164	/**
165	 * @update_pending_flush_sspp: OR in the given flushbits to the
166	 * cached pending_flush_mask.
167	 * No effect on hardware
168	 * @ctx       : ctl path ctx pointer
169	 * @blk       : SSPP block index
170	 */
171	void (*update_pending_flush_sspp)(struct dpu_hw_ctl *ctx,
172		enum dpu_sspp blk);
173
174	/**
175	 * @update_pending_flush_mixer: OR in the given flushbits to the
176	 * cached pending_flush_mask.
177	 * No effect on hardware
178	 * @ctx       : ctl path ctx pointer
179	 * @blk       : LM block index
180	 */
181	void (*update_pending_flush_mixer)(struct dpu_hw_ctl *ctx,
182		enum dpu_lm blk);
183
184	/**
185	 * @update_pending_flush_dspp: OR in the given flushbits to the
186	 * cached pending_flush_mask.
187	 * No effect on hardware
188	 * @ctx       : ctl path ctx pointer
189	 * @blk       : DSPP block index
190	 * @dspp_sub_blk : DSPP sub-block index
191	 */
192	void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx,
193		enum dpu_dspp blk, u32 dspp_sub_blk);
194
195	/**
196	 * @update_pending_flush_dsc: OR in the given flushbits to the
197	 * cached pending_(dsc_)flush_mask.
198	 * No effect on hardware
199	 * @ctx: ctl path ctx pointer
200	 * @blk: interface block index
201	 */
202	void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,
203					 enum dpu_dsc blk);
204
205	/**
206	 * @update_pending_flush_cdm: OR in the given flushbits to the
207	 * cached pending_(cdm_)flush_mask.
208	 * No effect on hardware
209	 * @ctx: ctl path ctx pointer
210	 * @cdm_num: idx of cdm to be flushed
211	 */
212	void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);
213
214	/**
215	 * @trigger_flush: Write the value of the pending_flush_mask to hardware
216	 * @ctx       : ctl path ctx pointer
217	 */
218	void (*trigger_flush)(struct dpu_hw_ctl *ctx);
219
220	/**
221	 * @get_flush_register: Read the value of the flush register
222	 * @ctx       : ctl path ctx pointer
223	 * @Return: value of the ctl flush register.
224	 */
225	u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
226
227	/**
228	 * @setup_intf_cfg: Setup ctl_path interface config
229	 * @ctx
230	 * @cfg    : interface config structure pointer
231	 */
232	void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
233		struct dpu_hw_intf_cfg *cfg);
234
235	/**
236	 * @reset_intf_cfg: reset ctl_path interface config
237	 * @ctx    : ctl path ctx pointer
238	 * @cfg    : interface config structure pointer
239	 */
240	void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
241			struct dpu_hw_intf_cfg *cfg);
242
243	/**
244	 * @reset: reset function for this ctl type
245	 */
246	int (*reset)(struct dpu_hw_ctl *c);
247
248	/**
249	 * @wait_reset_status: checks ctl reset status
250	 * @ctx       : ctl path ctx pointer
251	 *
252	 * This function checks the ctl reset status bit.
253	 * If the reset bit is set, it keeps polling the status till the hw
254	 * reset is complete.
255	 * Returns: 0 on success or -error if reset incomplete within interval
256	 */
257	int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
258
259	/**
260	 * @clear_all_blendstages: Set all blend stages to disabled
261	 * @ctx       : ctl path ctx pointer
262	 */
263	void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
264
265	/**
266	 * @setup_blendstage: Configure layer mixer to pipe configuration
267	 * @ctx       : ctl path ctx pointer
268	 * @lm        : layer mixer enumeration
269	 * @cfg       : blend stage configuration
270	 */
271	void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
272		enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
273
274	/**
275	 * @set_active_fetch_pipes: Set active pipes attached to this CTL
276	 * @ctx: ctl path ctx pointer
277	 * @active_pipes: bitmap of enum dpu_sspp
278	 */
279	void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx,
280		unsigned long *fetch_active);
281
282	/**
283	 * @set_active_pipes: Set active pipes attached to this CTL
284	 * @ctx: ctl path ctx pointer
285	 * @active_pipes: bitmap of enum dpu_sspp
286	 */
287	void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
288				 unsigned long *active_pipes);
289
290	/**
291	 * @set_active_lms: Set active layer mixers attached to this CTL
292	 * @ctx: ctl path ctx pointer
293	 * @active_lms: bitmap of enum dpu_lm
294	 */
295	void (*set_active_lms)(struct dpu_hw_ctl *ctx,
296			       unsigned long *active_lms);
297};
298
299/**
300 * struct dpu_hw_ctl : CTL PATH driver object
301 * @base: hardware block base structure
302 * @hw: block register map object
303 * @idx: control path index
304 * @caps: control path capabilities
305 * @mixer_count: number of mixers
306 * @mixer_hw_caps: mixer hardware capabilities
307 * @pending_flush_mask: storage for pending ctl_flush managed via ops
308 * @pending_intf_flush_mask: pending INTF flush
309 * @pending_wb_flush_mask: pending WB flush
310 * @pending_cwb_flush_mask: pending CWB flush
311 * @pending_periph_flush_mask: pending PERIPH flush
312 * @pending_merge_3d_flush_mask: pending MERGE 3D flush
313 * @pending_dspp_flush_mask: pending DSPP flush
314 * @pending_dsc_flush_mask: pending DSC flush
315 * @pending_cdm_flush_mask: pending CDM flush
316 * @mdss_ver: MDSS revision information
317 * @ops: operation list
318 */
319struct dpu_hw_ctl {
320	struct dpu_hw_blk base;
321	struct dpu_hw_blk_reg_map hw;
322
323	/* ctl path */
324	int idx;
325	const struct dpu_ctl_cfg *caps;
326	int mixer_count;
327	const struct dpu_lm_cfg *mixer_hw_caps;
328	u32 pending_flush_mask;
329	u32 pending_intf_flush_mask;
330	u32 pending_wb_flush_mask;
331	u32 pending_cwb_flush_mask;
332	u32 pending_periph_flush_mask;
333	u32 pending_merge_3d_flush_mask;
334	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];
335	u32 pending_dsc_flush_mask;
336	u32 pending_cdm_flush_mask;
337
338	const struct dpu_mdss_version *mdss_ver;
339
340	/* ops */
341	struct dpu_hw_ctl_ops ops;
342};
343
344/**
345 * to_dpu_hw_ctl - convert base object dpu_hw_base to container
346 * @hw: Pointer to base hardware block
347 * return: Pointer to hardware block container
348 */
349static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
350{
351	return container_of(hw, struct dpu_hw_ctl, base);
352}
353
354struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
355				   const struct dpu_ctl_cfg *cfg,
356				   void __iomem *addr,
357				   const struct dpu_mdss_version *mdss_ver,
358				   u32 mixer_count,
359				   const struct dpu_lm_cfg *mixer);
360
361#endif /*_DPU_HW_CTL_H */