dpu_encoder_phys_wb.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
  7
  8#include <linux/debugfs.h>
  9
 10#include <drm/drm_framebuffer.h>
 11#include <drm/drm_managed.h>
 12
 13#include "dpu_encoder_phys.h"
 14#include "dpu_formats.h"
 15#include "dpu_hw_top.h"
 16#include "dpu_hw_wb.h"
 17#include "dpu_hw_lm.h"
 18#include "dpu_hw_merge3d.h"
 19#include "dpu_hw_interrupts.h"
 20#include "dpu_core_irq.h"
 21#include "dpu_vbif.h"
 22#include "dpu_crtc.h"
 23#include "disp/msm_disp_snapshot.h"
 24
 25#define to_dpu_encoder_phys_wb(x) \
 26	container_of(x, struct dpu_encoder_phys_wb, base)
 27
 28/**
 29 * dpu_encoder_phys_wb_is_master - report wb always as master encoder
 30 * @phys_enc:	Pointer to physical encoder
 31 */
 32static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
 33{
 34	/* there is only one physical enc for dpu_writeback */
 35	return true;
 36}
 37
 38static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,
 39						struct dpu_hw_mdp *mdp,
 40						bool enable, bool *forced_on)
 41{
 42	if (wb->ops.setup_clk_force_ctrl) {
 43		*forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);
 44		return true;
 45	}
 46
 47	if (mdp->ops.setup_clk_force_ctrl) {
 48		*forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);
 49		return true;
 50	}
 51
 52	return false;
 53}
 54
 55/**
 56 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
 57 * @phys_enc:	Pointer to physical encoder
 58 */
 59static void dpu_encoder_phys_wb_set_ot_limit(
 60		struct dpu_encoder_phys *phys_enc)
 61{
 62	struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
 63	struct dpu_vbif_set_ot_params ot_params;
 64	bool forced_on = false;
 65
 66	memset(&ot_params, 0, sizeof(ot_params));
 67	ot_params.xin_id = hw_wb->caps->xin_id;
 68	ot_params.num = hw_wb->idx - WB_0;
 69	ot_params.width = phys_enc->cached_mode.hdisplay;
 70	ot_params.height = phys_enc->cached_mode.vdisplay;
 71	ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc);
 72	ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
 73	ot_params.vbif_idx = hw_wb->caps->vbif_idx;
 74	ot_params.rd = false;
 75
 76	if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
 77						 true, &forced_on))
 78		return;
 79
 80	dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
 81
 82	if (forced_on)
 83		_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
 84						    false, &forced_on);
 85}
 86
 87/**
 88 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
 89 * @phys_enc:	Pointer to physical encoder
 90 */
 91static void dpu_encoder_phys_wb_set_qos_remap(
 92		struct dpu_encoder_phys *phys_enc)
 93{
 94	struct dpu_hw_wb *hw_wb;
 95	struct dpu_vbif_set_qos_params qos_params;
 96	bool forced_on = false;
 97
 98	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
 99		DPU_ERROR("invalid arguments\n");
100		return;
101	}
102
103	if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
104		DPU_ERROR("invalid writeback hardware\n");
105		return;
106	}
107
108	hw_wb = phys_enc->hw_wb;
109
110	memset(&qos_params, 0, sizeof(qos_params));
111	qos_params.vbif_idx = hw_wb->caps->vbif_idx;
112	qos_params.xin_id = hw_wb->caps->xin_id;
113	qos_params.num = hw_wb->idx - WB_0;
114	qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc);
115
116	DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
117			qos_params.num,
118			qos_params.vbif_idx,
119			qos_params.xin_id, qos_params.is_rt);
120
121	if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
122						 true, &forced_on))
123		return;
124
125	dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
126
127	if (forced_on)
128		_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
129						    false, &forced_on);
130}
131
132/**
133 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
134 * @phys_enc:	Pointer to physical encoder
135 */
136static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
137{
138	struct dpu_hw_wb *hw_wb;
139	struct dpu_hw_qos_cfg qos_cfg;
140	const struct dpu_mdss_cfg *catalog;
141	const struct dpu_qos_lut_tbl *qos_lut_tb;
142
143	if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
144		DPU_ERROR("invalid parameter(s)\n");
145		return;
146	}
147
148	catalog = phys_enc->dpu_kms->catalog;
149
150	hw_wb = phys_enc->hw_wb;
151
152	memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));
153	qos_cfg.danger_safe_en = true;
154	qos_cfg.danger_lut =
155		catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
156
157	qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
158
159	qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
160	qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
161
162	if (hw_wb->ops.setup_qos_lut)
163		hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
164}
165
166/**
167 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
168 * @phys_enc:	Pointer to physical encoder
169 * @format: Format of the framebuffer
170 */
171static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
172					 const struct msm_format *format)
173{
174	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
175	struct dpu_hw_wb *hw_wb;
176	struct dpu_hw_wb_cfg *wb_cfg;
177	u32 cdp_usage;
178
179	if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
180		DPU_ERROR("invalid encoder\n");
181		return;
182	}
183
184	hw_wb = phys_enc->hw_wb;
185	wb_cfg = &wb_enc->wb_cfg;
186	if (dpu_encoder_helper_get_cwb_mask(phys_enc))
187		cdp_usage = DPU_PERF_CDP_USAGE_RT;
188	else
189		cdp_usage = DPU_PERF_CDP_USAGE_NRT;
190
191	wb_cfg->intf_mode = phys_enc->intf_mode;
192	wb_cfg->roi.x1 = 0;
193	wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
194	wb_cfg->roi.y1 = 0;
195	wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
196
197	if (hw_wb->ops.setup_roi)
198		hw_wb->ops.setup_roi(hw_wb, wb_cfg);
199
200	if (hw_wb->ops.setup_outformat)
201		hw_wb->ops.setup_outformat(hw_wb, wb_cfg, format);
202
203	if (hw_wb->ops.setup_cdp) {
204		const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
205
206		hw_wb->ops.setup_cdp(hw_wb, format,
207				     perf->cdp_cfg[cdp_usage].wr_enable);
208	}
209
210	if (hw_wb->ops.setup_outaddress)
211		hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
212}
213
214/**
215 * dpu_encoder_phys_wb_setup_ctl - setup wb pipeline for ctl path
216 * @phys_enc:Pointer to physical encoder
217 */
218static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
219{
220	struct dpu_hw_wb *hw_wb;
221	struct dpu_hw_cdm *hw_cdm;
222
223	if (!phys_enc) {
224		DPU_ERROR("invalid encoder\n");
225		return;
226	}
227
228	hw_wb = phys_enc->hw_wb;
229	hw_cdm = phys_enc->hw_cdm;
230
231	if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&
232		(phys_enc->hw_ctl &&
233		 phys_enc->hw_ctl->ops.setup_intf_cfg)) {
234		struct dpu_hw_intf_cfg intf_cfg = {0};
235		struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
236		enum dpu_3d_blend_mode mode_3d;
237
238		mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
239
240		intf_cfg.intf = DPU_NONE;
241		intf_cfg.wb = hw_wb->idx;
242		intf_cfg.cwb = dpu_encoder_helper_get_cwb_mask(phys_enc);
243
244		if (mode_3d && hw_pp && hw_pp->merge_3d)
245			intf_cfg.merge_3d = hw_pp->merge_3d->idx;
246
247		if (hw_cdm)
248			intf_cfg.cdm = hw_cdm->idx;
249
250		if (hw_pp && hw_pp->merge_3d && hw_pp->merge_3d->ops.setup_3d_mode)
251			hw_pp->merge_3d->ops.setup_3d_mode(hw_pp->merge_3d, mode_3d);
252
253		/* setup which pp blk will connect to this wb */
254		if (hw_pp && hw_wb->ops.bind_pingpong_blk)
255			hw_wb->ops.bind_pingpong_blk(hw_wb, hw_pp->idx);
256
257		phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
258	} else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
259		struct dpu_hw_intf_cfg intf_cfg = {0};
260
261		intf_cfg.intf = DPU_NONE;
262		intf_cfg.wb = hw_wb->idx;
263		intf_cfg.mode_3d =
264			dpu_encoder_helper_get_3d_blend_mode(phys_enc);
265		phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
266	}
267}
268
269/**
270 * _dpu_encoder_phys_wb_update_flush - flush hardware update
271 * @phys_enc:	Pointer to physical encoder
272 */
273static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
274{
275	struct dpu_hw_wb *hw_wb;
276	struct dpu_hw_ctl *hw_ctl;
277	struct dpu_hw_pingpong *hw_pp;
278	struct dpu_hw_cdm *hw_cdm;
279	u32 pending_flush = 0;
280	u32 mode_3d;
281
282	if (!phys_enc)
283		return;
284
285	hw_wb = phys_enc->hw_wb;
286	hw_pp = phys_enc->hw_pp;
287	hw_ctl = phys_enc->hw_ctl;
288	hw_cdm = phys_enc->hw_cdm;
289	mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
290
291	DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
292
293	if (!hw_ctl) {
294		DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
295		return;
296	}
297
298	if (hw_ctl->ops.update_pending_flush_wb)
299		hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
300
301	if (mode_3d && hw_ctl->ops.update_pending_flush_merge_3d &&
302	    hw_pp && hw_pp->merge_3d)
303		hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
304				hw_pp->merge_3d->idx);
305
306	if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm)
307		hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx);
308
309	if (hw_ctl->ops.get_pending_flush)
310		pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
311
312	DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
313			hw_ctl->idx - CTL_0, pending_flush,
314			hw_wb->idx - WB_0);
315}
316
317/**
318 * dpu_encoder_phys_wb_setup - setup writeback encoder
319 * @phys_enc:	Pointer to physical encoder
320 */
321static void dpu_encoder_phys_wb_setup(
322		struct dpu_encoder_phys *phys_enc)
323{
324	struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
325	struct drm_display_mode mode = phys_enc->cached_mode;
326	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
327	const struct msm_format *format;
328
329	format = msm_framebuffer_format(wb_enc->wb_job->fb);
330
331	DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
332			hw_wb->idx - WB_0, mode.name,
333			mode.hdisplay, mode.vdisplay);
334
335	dpu_encoder_phys_wb_set_ot_limit(phys_enc);
336
337	dpu_encoder_phys_wb_set_qos_remap(phys_enc);
338
339	dpu_encoder_phys_wb_set_qos(phys_enc);
340
341	dpu_encoder_phys_wb_setup_fb(phys_enc, format);
342
343	dpu_encoder_helper_phys_setup_cdm(phys_enc, format, CDM_CDWN_OUTPUT_WB);
344
345	dpu_encoder_helper_phys_setup_cwb(phys_enc, true);
346
347	dpu_encoder_phys_wb_setup_ctl(phys_enc);
348}
349
350/**
351 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
352 * @arg:	Pointer to writeback encoder
353 */
354static void dpu_encoder_phys_wb_done_irq(void *arg)
355{
356	struct dpu_encoder_phys *phys_enc = arg;
357	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
358
359	struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
360	unsigned long lock_flags;
361	u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
362
363	DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
364
365	dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);
366
367	dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
368
369	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
370	atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
371	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
372
373	if (wb_enc->wb_conn)
374		drm_writeback_signal_completion(wb_enc->wb_conn, 0);
375
376	/* Signal any waiting atomic commit thread */
377	wake_up_all(&phys_enc->pending_kickoff_wq);
378}
379
380/**
381 * dpu_encoder_phys_wb_irq_enable - irq control of WB
382 * @phys:	Pointer to physical encoder
383 */
384static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys)
385{
386
387	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
388
389	if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
390		dpu_core_irq_register_callback(phys->dpu_kms,
391					       phys->irq[INTR_IDX_WB_DONE],
392					       dpu_encoder_phys_wb_done_irq,
393					       phys);
394}
395
396/**
397 * dpu_encoder_phys_wb_irq_disable - irq control of WB
398 * @phys:	Pointer to physical encoder
399 */
400static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys)
401{
402
403	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
404
405	if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
406		dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
407}
408
409static void dpu_encoder_phys_wb_atomic_mode_set(
410		struct dpu_encoder_phys *phys_enc,
411		struct drm_crtc_state *crtc_state,
412		struct drm_connector_state *conn_state)
413{
414
415	phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
416}
417
418static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
419		struct dpu_encoder_phys *phys_enc)
420{
421	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
422	u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
423
424	wb_enc->wb_done_timeout_cnt++;
425
426	if (wb_enc->wb_done_timeout_cnt == 1)
427		msm_disp_snapshot_state(phys_enc->parent->dev);
428
429	atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
430
431	/* request a ctl reset before the next kickoff */
432	phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
433
434	if (wb_enc->wb_conn)
435		drm_writeback_signal_completion(wb_enc->wb_conn, 0);
436
437	dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);
438}
439
440/**
441 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
442 * @phys_enc:	Pointer to physical encoder
443 */
444static int dpu_encoder_phys_wb_wait_for_commit_done(
445		struct dpu_encoder_phys *phys_enc)
446{
447	int ret;
448	struct dpu_encoder_wait_info wait_info;
449	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
450
451	wait_info.wq = &phys_enc->pending_kickoff_wq;
452	wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
453	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
454
455	ret = dpu_encoder_helper_wait_for_irq(phys_enc,
456			phys_enc->irq[INTR_IDX_WB_DONE],
457			dpu_encoder_phys_wb_done_irq, &wait_info);
458	if (ret == -ETIMEDOUT)
459		_dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
460	else if (!ret)
461		wb_enc->wb_done_timeout_cnt = 0;
462
463	return ret;
464}
465
466/**
467 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
468 * @phys_enc:	Pointer to physical encoder
469 * Returns:	Zero on success
470 */
471static void dpu_encoder_phys_wb_prepare_for_kickoff(
472		struct dpu_encoder_phys *phys_enc)
473{
474	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
475	struct drm_connector *drm_conn;
476	struct drm_connector_state *state;
477
478	DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
479
480	if (!wb_enc->wb_conn || !wb_enc->wb_job) {
481		DPU_ERROR("invalid wb_conn or wb_job\n");
482		return;
483	}
484
485	drm_conn = &wb_enc->wb_conn->base;
486	state = drm_conn->state;
487
488	if (wb_enc->wb_conn && wb_enc->wb_job)
489		drm_writeback_queue_job(wb_enc->wb_conn, state);
490
491	dpu_encoder_phys_wb_setup(phys_enc);
492
493	_dpu_encoder_phys_wb_update_flush(phys_enc);
494}
495
496/**
497 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
498 * @phys_enc:	Pointer to physical encoder
499 */
500static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
501{
502	DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
503	return false;
504}
505
506/**
507 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
508 * @phys_enc:	Pointer to physical encoder
509 */
510static void dpu_encoder_phys_wb_handle_post_kickoff(
511		struct dpu_encoder_phys *phys_enc)
512{
513	DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
514
515}
516
517/**
518 * dpu_encoder_phys_wb_enable - enable writeback encoder
519 * @phys_enc:	Pointer to physical encoder
520 */
521static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
522{
523	DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
524	phys_enc->enable_state = DPU_ENC_ENABLED;
525}
526/**
527 * dpu_encoder_phys_wb_disable - disable writeback encoder
528 * @phys_enc:	Pointer to physical encoder
529 */
530static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
531{
532	struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
533
534	DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
535
536	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
537		DPU_ERROR("encoder is already disabled\n");
538		return;
539	}
540
541	/* reset h/w before final flush */
542	phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
543
544	/*
545	 * New CTL reset sequence from 5.0 MDP onwards.
546	 * If has_3d_merge_reset is not set, legacy reset
547	 * sequence is executed.
548	 *
549	 * Legacy reset sequence has not been implemented yet.
550	 * Any target earlier than SM8150 will need it and when
551	 * WB support is added to those targets will need to add
552	 * the legacy teardown sequence as well.
553	 */
554	if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
555		dpu_encoder_helper_phys_cleanup(phys_enc);
556
557	phys_enc->enable_state = DPU_ENC_DISABLED;
558}
559
560static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
561		struct drm_writeback_job *job)
562{
563	const struct msm_format *format;
564	struct dpu_hw_wb_cfg *wb_cfg;
565	int ret;
566	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
567
568	if (!job->fb)
569		return;
570
571	wb_enc->wb_job = job;
572	wb_enc->wb_conn = job->connector;
573
574	wb_cfg = &wb_enc->wb_cfg;
575
576	memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
577
578	ret = msm_framebuffer_prepare(job->fb, false);
579	if (ret) {
580		DPU_ERROR("prep fb failed, %d\n", ret);
581		return;
582	}
583
584	format = msm_framebuffer_format(job->fb);
585
586	ret = dpu_format_populate_plane_sizes(job->fb, &wb_cfg->dest);
587	if (ret) {
588		DPU_DEBUG("failed to populate plane sizes%d\n", ret);
589		return;
590	}
591
592	dpu_format_populate_addrs(job->fb, &wb_cfg->dest);
593
594	wb_cfg->dest.width = job->fb->width;
595	wb_cfg->dest.height = job->fb->height;
596	wb_cfg->dest.num_planes = format->num_planes;
597
598	if ((format->fetch_type == MDP_PLANE_PLANAR) &&
599	    (format->element[0] == C1_B_Cb))
600		swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
601
602	DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
603			wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
604			wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
605
606	DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
607			wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
608			wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
609}
610
611static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
612		struct drm_writeback_job *job)
613{
614	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
615
616	if (!job->fb)
617		return;
618
619	msm_framebuffer_cleanup(job->fb, false);
620	wb_enc->wb_job = NULL;
621	wb_enc->wb_conn = NULL;
622}
623
624static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
625{
626	struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
627
628	if (wb_enc->wb_job)
629		return true;
630	else
631		return false;
632}
633
634/**
635 * dpu_encoder_phys_wb_init_ops - initialize writeback operations
636 * @ops:	Pointer to encoder operation table
637 */
638static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
639{
640	ops->is_master = dpu_encoder_phys_wb_is_master;
641	ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
642	ops->enable = dpu_encoder_phys_wb_enable;
643	ops->disable = dpu_encoder_phys_wb_disable;
644	ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
645	ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
646	ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
647	ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
648	ops->trigger_start = dpu_encoder_helper_trigger_start;
649	ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
650	ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
651	ops->irq_enable = dpu_encoder_phys_wb_irq_enable;
652	ops->irq_disable = dpu_encoder_phys_wb_irq_disable;
653	ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
654
655}
656
657/**
658 * dpu_encoder_phys_wb_init - initialize writeback encoder
659 * @dev:  Corresponding device for devres management
660 * @p:	Pointer to init info structure with initialization params
661 */
662struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
663		struct dpu_enc_phys_init_params *p)
664{
665	struct dpu_encoder_phys *phys_enc = NULL;
666	struct dpu_encoder_phys_wb *wb_enc = NULL;
667
668	DPU_DEBUG("\n");
669
670	if (!p || !p->parent) {
671		DPU_ERROR("invalid params\n");
672		return ERR_PTR(-EINVAL);
673	}
674
675	wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);
676	if (!wb_enc) {
677		DPU_ERROR("failed to allocate wb phys_enc enc\n");
678		return ERR_PTR(-ENOMEM);
679	}
680
681	phys_enc = &wb_enc->base;
682
683	dpu_encoder_phys_init(phys_enc, p);
684
685	dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
686	phys_enc->intf_mode = INTF_MODE_WB_LINE;
687
688	atomic_set(&wb_enc->wbirq_refcount, 0);
689
690	wb_enc->wb_done_timeout_cnt = 0;
691
692	DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);
693
694	return phys_enc;
695}