dpu_encoder_phys_vid.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
  3 */
  4
  5#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
  6#include "dpu_encoder_phys.h"
  7#include "dpu_hw_interrupts.h"
  8#include "dpu_hw_merge3d.h"
  9#include "dpu_core_irq.h"
 10#include "dpu_formats.h"
 11#include "dpu_trace.h"
 12#include "disp/msm_disp_snapshot.h"
 13
 14#include <drm/display/drm_dsc_helper.h>
 15#include <drm/drm_managed.h>
 16
 17#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
 18		(e) && (e)->parent ? \
 19		(e)->parent->base.id : -1, \
 20		(e) && (e)->hw_intf ? \
 21		(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
 22
 23#define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
 24		(e) && (e)->parent ? \
 25		(e)->parent->base.id : -1, \
 26		(e) && (e)->hw_intf ? \
 27		(e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
 28
 29#define to_dpu_encoder_phys_vid(x) \
 30	container_of(x, struct dpu_encoder_phys_vid, base)
 31
 32static bool dpu_encoder_phys_vid_is_master(
 33		struct dpu_encoder_phys *phys_enc)
 34{
 35	bool ret = false;
 36
 37	if (phys_enc->split_role != ENC_ROLE_SLAVE)
 38		ret = true;
 39
 40	return ret;
 41}
 42
 43static void drm_mode_to_intf_timing_params(
 44		const struct dpu_encoder_phys *phys_enc,
 45		const struct drm_display_mode *mode,
 46		struct dpu_hw_intf_timing_params *timing)
 47{
 48	memset(timing, 0, sizeof(*timing));
 49
 50	if ((mode->htotal < mode->hsync_end)
 51			|| (mode->hsync_start < mode->hdisplay)
 52			|| (mode->vtotal < mode->vsync_end)
 53			|| (mode->vsync_start < mode->vdisplay)
 54			|| (mode->hsync_end < mode->hsync_start)
 55			|| (mode->vsync_end < mode->vsync_start)) {
 56		DPU_ERROR(
 57		    "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n",
 58				mode->hsync_start, mode->hsync_end,
 59				mode->htotal, mode->hdisplay);
 60		DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n",
 61				mode->vsync_start, mode->vsync_end,
 62				mode->vtotal, mode->vdisplay);
 63		return;
 64	}
 65
 66	/*
 67	 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html
 68	 *  Active Region      Front Porch   Sync   Back Porch
 69	 * <-----------------><------------><-----><----------->
 70	 * <- [hv]display --->
 71	 * <--------- [hv]sync_start ------>
 72	 * <----------------- [hv]sync_end ------->
 73	 * <---------------------------- [hv]total ------------->
 74	 */
 75	timing->width = mode->hdisplay;	/* active width */
 76	timing->height = mode->vdisplay;	/* active height */
 77	timing->xres = timing->width;
 78	timing->yres = timing->height;
 79	timing->h_back_porch = mode->htotal - mode->hsync_end;
 80	timing->h_front_porch = mode->hsync_start - mode->hdisplay;
 81	timing->v_back_porch = mode->vtotal - mode->vsync_end;
 82	timing->v_front_porch = mode->vsync_start - mode->vdisplay;
 83	timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
 84	timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
 85	timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
 86	timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
 87	timing->border_clr = 0;
 88	timing->underflow_clr = 0xff;
 89	timing->hsync_skew = mode->hskew;
 90
 91	/* DSI controller cannot handle active-low sync signals. */
 92	if (phys_enc->hw_intf->cap->type == INTF_DSI) {
 93		timing->hsync_polarity = 0;
 94		timing->vsync_polarity = 0;
 95	}
 96
 97	timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
 98	timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
 99
100	/*
101	 *  For DP/EDP, Shift timings to align it to bottom right.
102	 *  wide_bus_en is set for everything excluding SDM845 &
103	 *  porch changes cause DisplayPort failure and HDMI tearing.
104	 */
105	if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
106		timing->h_back_porch += timing->h_front_porch;
107		timing->h_front_porch = 0;
108		timing->v_back_porch += timing->v_front_porch;
109		timing->v_front_porch = 0;
110	}
111
112	/*
113	 * for DP, divide the horizonal parameters by 2 when
114	 * widebus is enabled
115	 */
116	if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
117		timing->width = timing->width >> 1;
118		timing->xres = timing->xres >> 1;
119		timing->h_back_porch = timing->h_back_porch >> 1;
120		timing->h_front_porch = timing->h_front_porch >> 1;
121		timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
122	}
123
124	/*
125	 * for DSI, if compression is enabled, then divide the horizonal active
126	 * timing parameters by compression ratio. bits of 3 components(R/G/B)
127	 * is compressed into bits of 1 pixel.
128	 */
129	if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
130		struct drm_dsc_config *dsc =
131		       dpu_encoder_get_dsc_config(phys_enc->parent);
132		/*
133		 * TODO: replace drm_dsc_get_bpp_int with logic to handle
134		 * fractional part if there is fraction
135		 */
136		timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
137				(dsc->bits_per_component * 3);
138		timing->xres = timing->width;
139	}
140}
141
142static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
143{
144	u32 active = timing->xres;
145	u32 inactive =
146	    timing->h_back_porch + timing->h_front_porch +
147	    timing->hsync_pulse_width;
148	return active + inactive;
149}
150
151static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing)
152{
153	u32 active = timing->yres;
154	u32 inactive =
155	    timing->v_back_porch + timing->v_front_porch +
156	    timing->vsync_pulse_width;
157	return active + inactive;
158}
159
160/*
161 * programmable_fetch_get_num_lines:
162 *	Number of fetch lines in vertical front porch
163 * @timing: Pointer to the intf timing information for the requested mode
164 *
165 * Returns the number of fetch lines in vertical front porch at which mdp
166 * can start fetching the next frame.
167 *
168 * Number of needed prefetch lines is anything that cannot be absorbed in the
169 * start of frame time (back porch + vsync pulse width).
170 *
171 * Some panels have very large VFP, however we only need a total number of
172 * lines based on the chip worst case latencies.
173 */
174static u32 programmable_fetch_get_num_lines(
175		struct dpu_encoder_phys *phys_enc,
176		const struct dpu_hw_intf_timing_params *timing)
177{
178	u32 worst_case_needed_lines =
179	    phys_enc->hw_intf->cap->prog_fetch_lines_worst_case;
180	u32 start_of_frame_lines =
181	    timing->v_back_porch + timing->vsync_pulse_width;
182	u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines;
183	u32 actual_vfp_lines = 0;
184
185	/* Fetch must be outside active lines, otherwise undefined. */
186	if (start_of_frame_lines >= worst_case_needed_lines) {
187		DPU_DEBUG_VIDENC(phys_enc,
188				"prog fetch is not needed, large vbp+vsw\n");
189		actual_vfp_lines = 0;
190	} else if (timing->v_front_porch < needed_vfp_lines) {
191		/* Warn fetch needed, but not enough porch in panel config */
192		pr_warn_once
193			("low vbp+vfp may lead to perf issues in some cases\n");
194		DPU_DEBUG_VIDENC(phys_enc,
195				"less vfp than fetch req, using entire vfp\n");
196		actual_vfp_lines = timing->v_front_porch;
197	} else {
198		DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n");
199		actual_vfp_lines = needed_vfp_lines;
200	}
201
202	DPU_DEBUG_VIDENC(phys_enc,
203		"v_front_porch %u v_back_porch %u vsync_pulse_width %u\n",
204		timing->v_front_porch, timing->v_back_porch,
205		timing->vsync_pulse_width);
206	DPU_DEBUG_VIDENC(phys_enc,
207		"wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n",
208		worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines);
209
210	return actual_vfp_lines;
211}
212
213/*
214 * programmable_fetch_config: Programs HW to prefetch lines by offsetting
215 *	the start of fetch into the vertical front porch for cases where the
216 *	vsync pulse width and vertical back porch time is insufficient
217 *
218 *	Gets # of lines to pre-fetch, then calculate VSYNC counter value.
219 *	HW layer requires VSYNC counter of first pixel of tgt VFP line.
220 *
221 * @timing: Pointer to the intf timing information for the requested mode
222 */
223static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
224				      const struct dpu_hw_intf_timing_params *timing)
225{
226	struct dpu_hw_intf_prog_fetch f = { 0 };
227	u32 vfp_fetch_lines = 0;
228	u32 horiz_total = 0;
229	u32 vert_total = 0;
230	u32 vfp_fetch_start_vsync_counter = 0;
231	unsigned long lock_flags;
232
233	if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))
234		return;
235
236	vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing);
237	if (vfp_fetch_lines) {
238		vert_total = get_vertical_total(timing);
239		horiz_total = get_horizontal_total(timing);
240		vfp_fetch_start_vsync_counter =
241		    (vert_total - vfp_fetch_lines) * horiz_total + 1;
242		f.enable = 1;
243		f.fetch_start = vfp_fetch_start_vsync_counter;
244	}
245
246	DPU_DEBUG_VIDENC(phys_enc,
247		"vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n",
248		vfp_fetch_lines, vfp_fetch_start_vsync_counter);
249
250	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
251	phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f);
252	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
253}
254
255static void dpu_encoder_phys_vid_setup_timing_engine(
256		struct dpu_encoder_phys *phys_enc)
257{
258	struct drm_display_mode mode;
259	struct dpu_hw_intf_timing_params timing_params = { 0 };
260	const struct msm_format *fmt = NULL;
261	u32 fmt_fourcc;
262	unsigned long lock_flags;
263	struct dpu_hw_intf_cfg intf_cfg = { 0 };
264
265	drm_mode_init(&mode, &phys_enc->cached_mode);
266
267	if (!phys_enc->hw_ctl->ops.setup_intf_cfg) {
268		DPU_ERROR("invalid encoder %d\n", phys_enc != NULL);
269		return;
270	}
271
272	if (!phys_enc->hw_intf->ops.setup_timing_gen) {
273		DPU_ERROR("timing engine setup is not supported\n");
274		return;
275	}
276
277	DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
278	drm_mode_debug_printmodeline(&mode);
279
280	fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
281
282	if (phys_enc->split_role != ENC_ROLE_SOLO || fmt_fourcc == DRM_FORMAT_YUV420) {
283		mode.hdisplay >>= 1;
284		mode.htotal >>= 1;
285		mode.hsync_start >>= 1;
286		mode.hsync_end >>= 1;
287		mode.hskew >>= 1;
288
289		DPU_DEBUG_VIDENC(phys_enc,
290			"split_role %d, halve horizontal %d %d %d %d %d\n",
291			phys_enc->split_role,
292			mode.hdisplay, mode.htotal,
293			mode.hsync_start, mode.hsync_end,
294			mode.hskew);
295	}
296
297	drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
298
299	fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
300	DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
301
302	if (phys_enc->hw_cdm)
303		intf_cfg.cdm = phys_enc->hw_cdm->idx;
304	intf_cfg.intf = phys_enc->hw_intf->idx;
305	if (phys_enc->split_role == ENC_ROLE_MASTER)
306		intf_cfg.intf_master = phys_enc->hw_intf->idx;
307	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
308	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
309	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
310	intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
311	if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d)
312		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
313
314	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
315	phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
316			&timing_params, fmt);
317	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
318
319	/* setup which pp blk will connect to this intf */
320	if (phys_enc->hw_intf->ops.bind_pingpong_blk)
321		phys_enc->hw_intf->ops.bind_pingpong_blk(
322				phys_enc->hw_intf,
323				phys_enc->hw_pp->idx);
324
325	if (phys_enc->hw_pp->merge_3d)
326		phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d);
327
328	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
329
330	programmable_fetch_config(phys_enc, &timing_params);
331}
332
333static void dpu_encoder_phys_vid_vblank_irq(void *arg)
334{
335	struct dpu_encoder_phys *phys_enc = arg;
336	struct dpu_hw_ctl *hw_ctl;
337	unsigned long lock_flags;
338	u32 flush_register = 0;
339
340	hw_ctl = phys_enc->hw_ctl;
341
342	DPU_ATRACE_BEGIN("vblank_irq");
343
344	dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
345
346	atomic_read(&phys_enc->pending_kickoff_cnt);
347
348	/*
349	 * only decrement the pending flush count if we've actually flushed
350	 * hardware. due to sw irq latency, vblank may have already happened
351	 * so we need to double-check with hw that it accepted the flush bits
352	 */
353	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
354	if (hw_ctl->ops.get_flush_register)
355		flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
356
357	if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
358		atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
359	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
360
361	/* Signal any waiting atomic commit thread */
362	wake_up_all(&phys_enc->pending_kickoff_wq);
363
364	dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
365			DPU_ENCODER_FRAME_EVENT_DONE);
366
367	DPU_ATRACE_END("vblank_irq");
368}
369
370static void dpu_encoder_phys_vid_underrun_irq(void *arg)
371{
372	struct dpu_encoder_phys *phys_enc = arg;
373
374	dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
375}
376
377static bool dpu_encoder_phys_vid_needs_single_flush(
378		struct dpu_encoder_phys *phys_enc)
379{
380	return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) &&
381		phys_enc->split_role != ENC_ROLE_SOLO;
382}
383
384static void dpu_encoder_phys_vid_atomic_mode_set(
385		struct dpu_encoder_phys *phys_enc,
386		struct drm_crtc_state *crtc_state,
387		struct drm_connector_state *conn_state)
388{
389	phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
390
391	phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
392}
393
394static int dpu_encoder_phys_vid_control_vblank_irq(
395		struct dpu_encoder_phys *phys_enc,
396		bool enable)
397{
398	int ret = 0;
399	int refcount;
400
401	mutex_lock(&phys_enc->vblank_ctl_lock);
402	refcount = phys_enc->vblank_refcount;
403
404	/* Slave encoders don't report vblank */
405	if (!dpu_encoder_phys_vid_is_master(phys_enc))
406		goto end;
407
408	/* protect against negative */
409	if (!enable && refcount == 0) {
410		ret = -EINVAL;
411		goto end;
412	}
413
414	DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
415		      refcount);
416
417	if (enable) {
418		if (phys_enc->vblank_refcount == 0)
419			ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,
420					phys_enc->irq[INTR_IDX_VSYNC],
421					dpu_encoder_phys_vid_vblank_irq,
422					phys_enc);
423		if (!ret)
424			phys_enc->vblank_refcount++;
425	} else if (!enable) {
426		if (phys_enc->vblank_refcount == 1)
427			ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
428					phys_enc->irq[INTR_IDX_VSYNC]);
429		if (!ret)
430			phys_enc->vblank_refcount--;
431	}
432
433end:
434	mutex_unlock(&phys_enc->vblank_ctl_lock);
435	if (ret) {
436		DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
437			  DRMID(phys_enc->parent),
438			  phys_enc->hw_intf->idx - INTF_0, ret, enable,
439			  refcount);
440	}
441	return ret;
442}
443
444static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
445{
446	struct dpu_hw_ctl *ctl;
447	const struct msm_format *fmt;
448	u32 fmt_fourcc;
449	u32 mode_3d;
450
451	ctl = phys_enc->hw_ctl;
452	fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
453	fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
454	mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
455
456	DPU_DEBUG_VIDENC(phys_enc, "\n");
457
458	if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
459		return;
460
461	dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
462
463	dpu_encoder_helper_phys_setup_cdm(phys_enc, fmt, CDM_CDWN_OUTPUT_HDMI);
464
465	dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
466
467	/*
468	 * For single flush cases (dual-ctl or pp-split), skip setting the
469	 * flush bit for the slave intf, since both intfs use same ctl
470	 * and HW will only flush the master.
471	 */
472	if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) &&
473		!dpu_encoder_phys_vid_is_master(phys_enc))
474		goto skip_flush;
475
476	ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
477	if (mode_3d && ctl->ops.update_pending_flush_merge_3d &&
478	    phys_enc->hw_pp->merge_3d)
479		ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);
480
481	if (ctl->ops.update_pending_flush_cdm && phys_enc->hw_cdm)
482		ctl->ops.update_pending_flush_cdm(ctl, phys_enc->hw_cdm->idx);
483
484	/*
485	 * Peripheral flush must be updated whenever flushing SDP packets is needed.
486	 * SDP packets are required for any YUV format (YUV420, YUV422, YUV444).
487	 */
488	if (ctl->ops.update_pending_flush_periph && dpu_encoder_needs_periph_flush(phys_enc))
489		ctl->ops.update_pending_flush_periph(ctl, phys_enc->hw_intf->idx);
490
491skip_flush:
492	DPU_DEBUG_VIDENC(phys_enc,
493		"update pending flush ctl %d intf %d\n",
494		ctl->idx - CTL_0, phys_enc->hw_intf->idx);
495
496	atomic_set(&phys_enc->underrun_cnt, 0);
497
498	/* ctl_flush & timing engine enable will be triggered by framework */
499	if (phys_enc->enable_state == DPU_ENC_DISABLED)
500		phys_enc->enable_state = DPU_ENC_ENABLING;
501}
502
503static int dpu_encoder_phys_vid_wait_for_tx_complete(
504		struct dpu_encoder_phys *phys_enc)
505{
506	struct dpu_encoder_wait_info wait_info;
507	int ret;
508
509	wait_info.wq = &phys_enc->pending_kickoff_wq;
510	wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
511	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
512
513	if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
514		return 0;
515	}
516
517	/* Wait for kickoff to complete */
518	ret = dpu_encoder_helper_wait_for_irq(phys_enc,
519			phys_enc->irq[INTR_IDX_VSYNC],
520			dpu_encoder_phys_vid_vblank_irq,
521			&wait_info);
522
523	if (ret == -ETIMEDOUT) {
524		dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC);
525	}
526
527	return ret;
528}
529
530static int dpu_encoder_phys_vid_wait_for_commit_done(
531		struct dpu_encoder_phys *phys_enc)
532{
533	struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
534	int ret;
535
536	if (!hw_ctl)
537		return 0;
538
539	ret = wait_event_timeout(phys_enc->pending_kickoff_wq,
540		(hw_ctl->ops.get_flush_register(hw_ctl) == 0),
541		msecs_to_jiffies(50));
542	if (ret <= 0) {
543		DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl));
544		return -ETIMEDOUT;
545	}
546
547	return 0;
548}
549
550static void dpu_encoder_phys_vid_prepare_for_kickoff(
551		struct dpu_encoder_phys *phys_enc)
552{
553	struct dpu_hw_ctl *ctl;
554	int rc;
555	struct drm_encoder *drm_enc;
556
557	drm_enc = phys_enc->parent;
558
559	ctl = phys_enc->hw_ctl;
560	if (!ctl->ops.wait_reset_status)
561		return;
562
563	/*
564	 * hw supports hardware initiated ctl reset, so before we kickoff a new
565	 * frame, need to check and wait for hw initiated ctl reset completion
566	 */
567	rc = ctl->ops.wait_reset_status(ctl);
568	if (rc) {
569		DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n",
570				ctl->idx, rc);
571		msm_disp_snapshot_state(drm_enc->dev);
572		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
573				phys_enc->irq[INTR_IDX_VSYNC]);
574	}
575}
576
577static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
578{
579	unsigned long lock_flags;
580	int ret;
581	struct dpu_hw_intf_status intf_status = {0};
582
583	if (!phys_enc->parent || !phys_enc->parent->dev) {
584		DPU_ERROR("invalid encoder/device\n");
585		return;
586	}
587
588	if (!phys_enc->hw_intf) {
589		DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
590				phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL);
591		return;
592	}
593
594	if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
595		return;
596
597	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
598		DPU_ERROR("already disabled\n");
599		return;
600	}
601
602	spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
603	phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0);
604	if (dpu_encoder_phys_vid_is_master(phys_enc))
605		dpu_encoder_phys_inc_pending(phys_enc);
606	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
607
608	/*
609	 * Wait for a vsync so we know the ENABLE=0 latched before
610	 * the (connector) source of the vsync's gets disabled,
611	 * otherwise we end up in a funny state if we re-enable
612	 * before the disable latches, which results that some of
613	 * the settings changes for the new modeset (like new
614	 * scanout buffer) don't latch properly..
615	 */
616	if (dpu_encoder_phys_vid_is_master(phys_enc)) {
617		ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
618		if (ret) {
619			atomic_set(&phys_enc->pending_kickoff_cnt, 0);
620			DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
621				  DRMID(phys_enc->parent),
622				  phys_enc->hw_intf->idx - INTF_0, ret);
623		}
624	}
625
626	if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status)
627		phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status);
628
629	/*
630	 * Wait for a vsync if timing en status is on after timing engine
631	 * is disabled.
632	 */
633	if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) {
634		spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
635		dpu_encoder_phys_inc_pending(phys_enc);
636		spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
637		ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
638		if (ret) {
639			atomic_set(&phys_enc->pending_kickoff_cnt, 0);
640			DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
641				  DRMID(phys_enc->parent),
642				  phys_enc->hw_intf->idx - INTF_0, ret);
643		}
644	}
645
646	dpu_encoder_helper_phys_cleanup(phys_enc);
647	phys_enc->enable_state = DPU_ENC_DISABLED;
648}
649
650static void dpu_encoder_phys_vid_handle_post_kickoff(
651		struct dpu_encoder_phys *phys_enc)
652{
653	unsigned long lock_flags;
654
655	/*
656	 * Video mode must flush CTL before enabling timing engine
657	 * Video encoders need to turn on their interfaces now
658	 */
659	if (phys_enc->enable_state == DPU_ENC_ENABLING) {
660		trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
661				    phys_enc->hw_intf->idx - INTF_0);
662		spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
663		phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1);
664		spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
665		phys_enc->enable_state = DPU_ENC_ENABLED;
666	}
667}
668
669static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc)
670{
671	int ret;
672
673	trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent),
674					  phys_enc->hw_intf->idx - INTF_0,
675					  phys_enc->vblank_refcount);
676
677	ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
678	if (WARN_ON(ret))
679		return;
680
681	dpu_core_irq_register_callback(phys_enc->dpu_kms,
682				       phys_enc->irq[INTR_IDX_UNDERRUN],
683				       dpu_encoder_phys_vid_underrun_irq,
684				       phys_enc);
685}
686
687static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc)
688{
689	trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent),
690					   phys_enc->hw_intf->idx - INTF_0,
691					   phys_enc->vblank_refcount);
692
693	dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false);
694	dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
695					 phys_enc->irq[INTR_IDX_UNDERRUN]);
696}
697
698static int dpu_encoder_phys_vid_get_line_count(
699		struct dpu_encoder_phys *phys_enc)
700{
701	if (!dpu_encoder_phys_vid_is_master(phys_enc))
702		return -EINVAL;
703
704	if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
705		return -EINVAL;
706
707	return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
708}
709
710static int dpu_encoder_phys_vid_get_frame_count(
711		struct dpu_encoder_phys *phys_enc)
712{
713	struct dpu_hw_intf_status s = {0};
714	u32 fetch_start = 0;
715	struct drm_display_mode mode;
716
717	drm_mode_init(&mode, &phys_enc->cached_mode);
718
719	if (!dpu_encoder_phys_vid_is_master(phys_enc))
720		return -EINVAL;
721
722	if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status)
723		return -EINVAL;
724
725	phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s);
726
727	if (s.is_prog_fetch_en && s.is_en) {
728		fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay);
729		if ((s.line_count > fetch_start) &&
730			(s.line_count <= mode.vtotal))
731			return s.frame_count + 1;
732	}
733
734	return s.frame_count;
735}
736
737static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
738{
739	ops->is_master = dpu_encoder_phys_vid_is_master;
740	ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
741	ops->enable = dpu_encoder_phys_vid_enable;
742	ops->disable = dpu_encoder_phys_vid_disable;
743	ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
744	ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
745	ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;
746	ops->irq_enable = dpu_encoder_phys_vid_irq_enable;
747	ops->irq_disable = dpu_encoder_phys_vid_irq_disable;
748	ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
749	ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
750	ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
751	ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
752	ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count;
753}
754
755/**
756 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
757 * @dev:  Corresponding device for devres management
758 * @p:	Pointer to init params structure
759 * Return: Error code or newly allocated encoder
760 */
761struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
762		struct dpu_enc_phys_init_params *p)
763{
764	struct dpu_encoder_phys *phys_enc = NULL;
765
766	if (!p) {
767		DPU_ERROR("failed to create encoder due to invalid parameter\n");
768		return ERR_PTR(-EINVAL);
769	}
770
771	phys_enc = drmm_kzalloc(dev, sizeof(*phys_enc), GFP_KERNEL);
772	if (!phys_enc) {
773		DPU_ERROR("failed to create encoder due to memory allocation error\n");
774		return ERR_PTR(-ENOMEM);
775	}
776
777	DPU_DEBUG_VIDENC(phys_enc, "\n");
778
779	dpu_encoder_phys_init(phys_enc, p);
780	mutex_init(&phys_enc->vblank_ctl_lock);
781	phys_enc->vblank_refcount = 0;
782
783	dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
784	phys_enc->intf_mode = INTF_MODE_VIDEO;
785
786	DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);
787
788	return phys_enc;
789}