dpu_9_2_x1e80100.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2023, Linaro Limited
  4 */
  5
  6#ifndef _DPU_9_2_X1E80100_H
  7#define _DPU_9_2_X1E80100_H
  8
  9static const struct dpu_caps x1e80100_dpu_caps = {
 10	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 11	.max_mixer_blendstages = 0xb,
 12	.has_src_split = true,
 13	.has_dim_layer = true,
 14	.has_idle_pc = true,
 15	.has_3d_merge = true,
 16	.max_linewidth = 5120,
 17	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 18};
 19
 20static const struct dpu_mdp_cfg x1e80100_mdp = {
 21	.name = "top_0",
 22	.base = 0, .len = 0x494,
 23	.clk_ctrls = {
 24		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
 25	},
 26};
 27
 28static const struct dpu_ctl_cfg x1e80100_ctl[] = {
 29	{
 30		.name = "ctl_0", .id = CTL_0,
 31		.base = 0x15000, .len = 0x290,
 32		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 33	}, {
 34		.name = "ctl_1", .id = CTL_1,
 35		.base = 0x16000, .len = 0x290,
 36		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 37	}, {
 38		.name = "ctl_2", .id = CTL_2,
 39		.base = 0x17000, .len = 0x290,
 40		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 41	}, {
 42		.name = "ctl_3", .id = CTL_3,
 43		.base = 0x18000, .len = 0x290,
 44		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 45	}, {
 46		.name = "ctl_4", .id = CTL_4,
 47		.base = 0x19000, .len = 0x290,
 48		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 49	}, {
 50		.name = "ctl_5", .id = CTL_5,
 51		.base = 0x1a000, .len = 0x290,
 52		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 53	},
 54};
 55
 56static const struct dpu_sspp_cfg x1e80100_sspp[] = {
 57	{
 58		.name = "sspp_0", .id = SSPP_VIG0,
 59		.base = 0x4000, .len = 0x344,
 60		.features = VIG_SDM845_MASK_SDMA,
 61		.sblk = &dpu_vig_sblk_qseed3_3_3,
 62		.xin_id = 0,
 63		.type = SSPP_TYPE_VIG,
 64	}, {
 65		.name = "sspp_1", .id = SSPP_VIG1,
 66		.base = 0x6000, .len = 0x344,
 67		.features = VIG_SDM845_MASK_SDMA,
 68		.sblk = &dpu_vig_sblk_qseed3_3_3,
 69		.xin_id = 4,
 70		.type = SSPP_TYPE_VIG,
 71	}, {
 72		.name = "sspp_2", .id = SSPP_VIG2,
 73		.base = 0x8000, .len = 0x344,
 74		.features = VIG_SDM845_MASK_SDMA,
 75		.sblk = &dpu_vig_sblk_qseed3_3_3,
 76		.xin_id = 8,
 77		.type = SSPP_TYPE_VIG,
 78	}, {
 79		.name = "sspp_3", .id = SSPP_VIG3,
 80		.base = 0xa000, .len = 0x344,
 81		.features = VIG_SDM845_MASK_SDMA,
 82		.sblk = &dpu_vig_sblk_qseed3_3_3,
 83		.xin_id = 12,
 84		.type = SSPP_TYPE_VIG,
 85	}, {
 86		.name = "sspp_8", .id = SSPP_DMA0,
 87		.base = 0x24000, .len = 0x344,
 88		.features = DMA_SDM845_MASK_SDMA,
 89		.sblk = &dpu_dma_sblk,
 90		.xin_id = 1,
 91		.type = SSPP_TYPE_DMA,
 92	}, {
 93		.name = "sspp_9", .id = SSPP_DMA1,
 94		.base = 0x26000, .len = 0x344,
 95		.features = DMA_SDM845_MASK_SDMA,
 96		.sblk = &dpu_dma_sblk,
 97		.xin_id = 5,
 98		.type = SSPP_TYPE_DMA,
 99	}, {
100		.name = "sspp_10", .id = SSPP_DMA2,
101		.base = 0x28000, .len = 0x344,
102		.features = DMA_SDM845_MASK_SDMA,
103		.sblk = &dpu_dma_sblk,
104		.xin_id = 9,
105		.type = SSPP_TYPE_DMA,
106	}, {
107		.name = "sspp_11", .id = SSPP_DMA3,
108		.base = 0x2a000, .len = 0x344,
109		.features = DMA_SDM845_MASK_SDMA,
110		.sblk = &dpu_dma_sblk,
111		.xin_id = 13,
112		.type = SSPP_TYPE_DMA,
113	}, {
114		.name = "sspp_12", .id = SSPP_DMA4,
115		.base = 0x2c000, .len = 0x344,
116		.features = DMA_CURSOR_SDM845_MASK_SDMA,
117		.sblk = &dpu_dma_sblk,
118		.xin_id = 14,
119		.type = SSPP_TYPE_DMA,
120	}, {
121		.name = "sspp_13", .id = SSPP_DMA5,
122		.base = 0x2e000, .len = 0x344,
123		.features = DMA_CURSOR_SDM845_MASK_SDMA,
124		.sblk = &dpu_dma_sblk,
125		.xin_id = 15,
126		.type = SSPP_TYPE_DMA,
127	},
128};
129
130static const struct dpu_lm_cfg x1e80100_lm[] = {
131	{
132		.name = "lm_0", .id = LM_0,
133		.base = 0x44000, .len = 0x400,
134		.features = MIXER_MSM8998_MASK,
135		.sblk = &sdm845_lm_sblk,
136		.lm_pair = LM_1,
137		.pingpong = PINGPONG_0,
138		.dspp = DSPP_0,
139	}, {
140		.name = "lm_1", .id = LM_1,
141		.base = 0x45000, .len = 0x400,
142		.features = MIXER_MSM8998_MASK,
143		.sblk = &sdm845_lm_sblk,
144		.lm_pair = LM_0,
145		.pingpong = PINGPONG_1,
146		.dspp = DSPP_1,
147	}, {
148		.name = "lm_2", .id = LM_2,
149		.base = 0x46000, .len = 0x400,
150		.features = MIXER_MSM8998_MASK,
151		.sblk = &sdm845_lm_sblk,
152		.lm_pair = LM_3,
153		.pingpong = PINGPONG_2,
154		.dspp = DSPP_2,
155	}, {
156		.name = "lm_3", .id = LM_3,
157		.base = 0x47000, .len = 0x400,
158		.features = MIXER_MSM8998_MASK,
159		.sblk = &sdm845_lm_sblk,
160		.lm_pair = LM_2,
161		.pingpong = PINGPONG_3,
162		.dspp = DSPP_3,
163	}, {
164		.name = "lm_4", .id = LM_4,
165		.base = 0x48000, .len = 0x400,
166		.features = MIXER_MSM8998_MASK,
167		.sblk = &sdm845_lm_sblk,
168		.lm_pair = LM_5,
169		.pingpong = PINGPONG_4,
170	}, {
171		.name = "lm_5", .id = LM_5,
172		.base = 0x49000, .len = 0x400,
173		.features = MIXER_MSM8998_MASK,
174		.sblk = &sdm845_lm_sblk,
175		.lm_pair = LM_4,
176		.pingpong = PINGPONG_5,
177	},
178};
179
180static const struct dpu_dspp_cfg x1e80100_dspp[] = {
181	{
182		.name = "dspp_0", .id = DSPP_0,
183		.base = 0x54000, .len = 0x1800,
184		.sblk = &sdm845_dspp_sblk,
185	}, {
186		.name = "dspp_1", .id = DSPP_1,
187		.base = 0x56000, .len = 0x1800,
188		.sblk = &sdm845_dspp_sblk,
189	}, {
190		.name = "dspp_2", .id = DSPP_2,
191		.base = 0x58000, .len = 0x1800,
192		.sblk = &sdm845_dspp_sblk,
193	}, {
194		.name = "dspp_3", .id = DSPP_3,
195		.base = 0x5a000, .len = 0x1800,
196		.sblk = &sdm845_dspp_sblk,
197	},
198};
199
200static const struct dpu_pingpong_cfg x1e80100_pp[] = {
201	{
202		.name = "pingpong_0", .id = PINGPONG_0,
203		.base = 0x69000, .len = 0,
204		.sblk = &sc7280_pp_sblk,
205		.merge_3d = MERGE_3D_0,
206		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
207	}, {
208		.name = "pingpong_1", .id = PINGPONG_1,
209		.base = 0x6a000, .len = 0,
210		.sblk = &sc7280_pp_sblk,
211		.merge_3d = MERGE_3D_0,
212		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
213	}, {
214		.name = "pingpong_2", .id = PINGPONG_2,
215		.base = 0x6b000, .len = 0,
216		.sblk = &sc7280_pp_sblk,
217		.merge_3d = MERGE_3D_1,
218		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
219	}, {
220		.name = "pingpong_3", .id = PINGPONG_3,
221		.base = 0x6c000, .len = 0,
222		.sblk = &sc7280_pp_sblk,
223		.merge_3d = MERGE_3D_1,
224		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
225	}, {
226		.name = "pingpong_4", .id = PINGPONG_4,
227		.base = 0x6d000, .len = 0,
228		.sblk = &sc7280_pp_sblk,
229		.merge_3d = MERGE_3D_2,
230		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
231	}, {
232		.name = "pingpong_5", .id = PINGPONG_5,
233		.base = 0x6e000, .len = 0,
234		.sblk = &sc7280_pp_sblk,
235		.merge_3d = MERGE_3D_2,
236		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
237	}, {
238		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
239		.base = 0x66000, .len = 0,
240		.sblk = &sc7280_pp_sblk,
241		.merge_3d = MERGE_3D_3,
242	}, {
243		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
244		.base = 0x66400, .len = 0,
245		.sblk = &sc7280_pp_sblk,
246		.merge_3d = MERGE_3D_3,
247	},
248};
249
250static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] = {
251	{
252		.name = "merge_3d_0", .id = MERGE_3D_0,
253		.base = 0x4e000, .len = 0x8,
254	}, {
255		.name = "merge_3d_1", .id = MERGE_3D_1,
256		.base = 0x4f000, .len = 0x8,
257	}, {
258		.name = "merge_3d_2", .id = MERGE_3D_2,
259		.base = 0x50000, .len = 0x8,
260	}, {
261		.name = "merge_3d_3", .id = MERGE_3D_3,
262		.base = 0x66700, .len = 0x8,
263	},
264};
265
266/*
267 * NOTE: Each display compression engine (DCE) contains dual hard
268 * slice DSC encoders so both share same base address but with
269 * its own different sub block address.
270 */
271static const struct dpu_dsc_cfg x1e80100_dsc[] = {
272	{
273		.name = "dce_0_0", .id = DSC_0,
274		.base = 0x80000, .len = 0x4,
275		.sblk = &dsc_sblk_0,
276	}, {
277		.name = "dce_0_1", .id = DSC_1,
278		.base = 0x80000, .len = 0x4,
279		.sblk = &dsc_sblk_1,
280	}, {
281		.name = "dce_1_0", .id = DSC_2,
282		.base = 0x81000, .len = 0x4,
283		.features = BIT(DPU_DSC_NATIVE_42x_EN),
284		.sblk = &dsc_sblk_0,
285	}, {
286		.name = "dce_1_1", .id = DSC_3,
287		.base = 0x81000, .len = 0x4,
288		.features = BIT(DPU_DSC_NATIVE_42x_EN),
289		.sblk = &dsc_sblk_1,
290	},
291};
292
293static const struct dpu_wb_cfg x1e80100_wb[] = {
294	{
295		.name = "wb_2", .id = WB_2,
296		.base = 0x65000, .len = 0x2c8,
297		.features = WB_SDM845_MASK,
298		.format_list = wb2_formats_rgb_yuv,
299		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
300		.xin_id = 6,
301		.vbif_idx = VBIF_RT,
302		.maxlinewidth = 4096,
303		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
304	},
305};
306
307/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
308static const struct dpu_intf_cfg x1e80100_intf[] = {
309	{
310		.name = "intf_0", .id = INTF_0,
311		.base = 0x34000, .len = 0x280,
312		.type = INTF_DP,
313		.controller_id = MSM_DP_CONTROLLER_0,
314		.prog_fetch_lines_worst_case = 24,
315		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
316		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
317	}, {
318		.name = "intf_1", .id = INTF_1,
319		.base = 0x35000, .len = 0x300,
320		.type = INTF_DSI,
321		.controller_id = MSM_DSI_CONTROLLER_0,
322		.prog_fetch_lines_worst_case = 24,
323		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
324		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
325		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
326	}, {
327		.name = "intf_2", .id = INTF_2,
328		.base = 0x36000, .len = 0x300,
329		.type = INTF_DSI,
330		.controller_id = MSM_DSI_CONTROLLER_1,
331		.prog_fetch_lines_worst_case = 24,
332		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
333		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
334		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
335	}, {
336		.name = "intf_3", .id = INTF_3,
337		.base = 0x37000, .len = 0x280,
338		.type = INTF_NONE,
339		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
340		.prog_fetch_lines_worst_case = 24,
341		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
342		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
343	}, {
344		.name = "intf_4", .id = INTF_4,
345		.base = 0x38000, .len = 0x280,
346		.type = INTF_DP,
347		.controller_id = MSM_DP_CONTROLLER_1,
348		.prog_fetch_lines_worst_case = 24,
349		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
350		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
351	}, {
352		.name = "intf_5", .id = INTF_5,
353		.base = 0x39000, .len = 0x280,
354		.type = INTF_DP,
355		.controller_id = MSM_DP_CONTROLLER_3,
356		.prog_fetch_lines_worst_case = 24,
357		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
358		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
359	}, {
360		.name = "intf_6", .id = INTF_6,
361		.base = 0x3A000, .len = 0x280,
362		.type = INTF_DP,
363		.controller_id = MSM_DP_CONTROLLER_2,
364		.prog_fetch_lines_worst_case = 24,
365		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
366		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
367	}, {
368		.name = "intf_7", .id = INTF_7,
369		.base = 0x3b000, .len = 0x280,
370		.type = INTF_NONE,
371		.controller_id = MSM_DP_CONTROLLER_2,	/* pair with intf_6 for DP MST */
372		.prog_fetch_lines_worst_case = 24,
373		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
374		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
375	}, {
376		.name = "intf_8", .id = INTF_8,
377		.base = 0x3c000, .len = 0x280,
378		.type = INTF_NONE,
379		.controller_id = MSM_DP_CONTROLLER_1,	/* pair with intf_4 for DP MST */
380		.prog_fetch_lines_worst_case = 24,
381		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
382		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
383	},
384};
385
386static const struct dpu_perf_cfg x1e80100_perf_data = {
387	.max_bw_low = 13600000,
388	.max_bw_high = 18200000,
389	.min_core_ib = 2500000,
390	.min_llcc_ib = 0,
391	.min_dram_ib = 800000,
392	.min_prefill_lines = 35,
393	/* FIXME: lut tables */
394	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
395	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
396	.qos_lut_tbl = {
397		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
398		.entries = sc7180_qos_linear
399		},
400		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
401		.entries = sc7180_qos_macrotile
402		},
403		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
404		.entries = sc7180_qos_nrt
405		},
406		/* TODO: macrotile-qseed is different from macrotile */
407	},
408	.cdp_cfg = {
409		{.rd_enable = 1, .wr_enable = 1},
410		{.rd_enable = 1, .wr_enable = 0}
411	},
412	.clk_inefficiency_factor = 105,
413	.bw_inefficiency_factor = 120,
414};
415
416static const struct dpu_mdss_version x1e80100_mdss_ver = {
417	.core_major_ver = 9,
418	.core_minor_ver = 2,
419};
420
421const struct dpu_mdss_cfg dpu_x1e80100_cfg = {
422	.mdss_ver = &x1e80100_mdss_ver,
423	.caps = &x1e80100_dpu_caps,
424	.mdp = &x1e80100_mdp,
425	.cdm = &dpu_cdm_5_x,
426	.ctl_count = ARRAY_SIZE(x1e80100_ctl),
427	.ctl = x1e80100_ctl,
428	.sspp_count = ARRAY_SIZE(x1e80100_sspp),
429	.sspp = x1e80100_sspp,
430	.mixer_count = ARRAY_SIZE(x1e80100_lm),
431	.mixer = x1e80100_lm,
432	.dspp_count = ARRAY_SIZE(x1e80100_dspp),
433	.dspp = x1e80100_dspp,
434	.pingpong_count = ARRAY_SIZE(x1e80100_pp),
435	.pingpong = x1e80100_pp,
436	.dsc_count = ARRAY_SIZE(x1e80100_dsc),
437	.dsc = x1e80100_dsc,
438	.merge_3d_count = ARRAY_SIZE(x1e80100_merge_3d),
439	.merge_3d = x1e80100_merge_3d,
440	.wb_count = ARRAY_SIZE(x1e80100_wb),
441	.wb = x1e80100_wb,
442	.intf_count = ARRAY_SIZE(x1e80100_intf),
443	.intf = x1e80100_intf,
444	.vbif_count = ARRAY_SIZE(sm8550_vbif),
445	.vbif = sm8550_vbif,
446	.perf = &x1e80100_perf_data,
447};
448
449#endif