dpu_9_0_sm8550.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_9_0_SM8550_H
  8#define _DPU_9_0_SM8550_H
  9
 10static const struct dpu_caps sm8550_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0xb,
 13	.has_src_split = true,
 14	.has_dim_layer = true,
 15	.has_idle_pc = true,
 16	.has_3d_merge = true,
 17	.max_linewidth = 5120,
 18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 19};
 20
 21static const struct dpu_mdp_cfg sm8550_mdp = {
 22	.name = "top_0",
 23	.base = 0, .len = 0x494,
 24	.clk_ctrls = {
 25		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
 26	},
 27};
 28
 29static const struct dpu_ctl_cfg sm8550_ctl[] = {
 30	{
 31		.name = "ctl_0", .id = CTL_0,
 32		.base = 0x15000, .len = 0x290,
 33		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 34	}, {
 35		.name = "ctl_1", .id = CTL_1,
 36		.base = 0x16000, .len = 0x290,
 37		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 38	}, {
 39		.name = "ctl_2", .id = CTL_2,
 40		.base = 0x17000, .len = 0x290,
 41		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 42	}, {
 43		.name = "ctl_3", .id = CTL_3,
 44		.base = 0x18000, .len = 0x290,
 45		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 46	}, {
 47		.name = "ctl_4", .id = CTL_4,
 48		.base = 0x19000, .len = 0x290,
 49		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 50	}, {
 51		.name = "ctl_5", .id = CTL_5,
 52		.base = 0x1a000, .len = 0x290,
 53		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 54	},
 55};
 56
 57static const struct dpu_sspp_cfg sm8550_sspp[] = {
 58	{
 59		.name = "sspp_0", .id = SSPP_VIG0,
 60		.base = 0x4000, .len = 0x344,
 61		.features = VIG_SDM845_MASK_SDMA,
 62		.sblk = &dpu_vig_sblk_qseed3_3_2,
 63		.xin_id = 0,
 64		.type = SSPP_TYPE_VIG,
 65	}, {
 66		.name = "sspp_1", .id = SSPP_VIG1,
 67		.base = 0x6000, .len = 0x344,
 68		.features = VIG_SDM845_MASK_SDMA,
 69		.sblk = &dpu_vig_sblk_qseed3_3_2,
 70		.xin_id = 4,
 71		.type = SSPP_TYPE_VIG,
 72	}, {
 73		.name = "sspp_2", .id = SSPP_VIG2,
 74		.base = 0x8000, .len = 0x344,
 75		.features = VIG_SDM845_MASK_SDMA,
 76		.sblk = &dpu_vig_sblk_qseed3_3_2,
 77		.xin_id = 8,
 78		.type = SSPP_TYPE_VIG,
 79	}, {
 80		.name = "sspp_3", .id = SSPP_VIG3,
 81		.base = 0xa000, .len = 0x344,
 82		.features = VIG_SDM845_MASK_SDMA,
 83		.sblk = &dpu_vig_sblk_qseed3_3_2,
 84		.xin_id = 12,
 85		.type = SSPP_TYPE_VIG,
 86	}, {
 87		.name = "sspp_8", .id = SSPP_DMA0,
 88		.base = 0x24000, .len = 0x344,
 89		.features = DMA_SDM845_MASK_SDMA,
 90		.sblk = &dpu_dma_sblk,
 91		.xin_id = 1,
 92		.type = SSPP_TYPE_DMA,
 93	}, {
 94		.name = "sspp_9", .id = SSPP_DMA1,
 95		.base = 0x26000, .len = 0x344,
 96		.features = DMA_SDM845_MASK_SDMA,
 97		.sblk = &dpu_dma_sblk,
 98		.xin_id = 5,
 99		.type = SSPP_TYPE_DMA,
100	}, {
101		.name = "sspp_10", .id = SSPP_DMA2,
102		.base = 0x28000, .len = 0x344,
103		.features = DMA_SDM845_MASK_SDMA,
104		.sblk = &dpu_dma_sblk,
105		.xin_id = 9,
106		.type = SSPP_TYPE_DMA,
107	}, {
108		.name = "sspp_11", .id = SSPP_DMA3,
109		.base = 0x2a000, .len = 0x344,
110		.features = DMA_SDM845_MASK_SDMA,
111		.sblk = &dpu_dma_sblk,
112		.xin_id = 13,
113		.type = SSPP_TYPE_DMA,
114	}, {
115		.name = "sspp_12", .id = SSPP_DMA4,
116		.base = 0x2c000, .len = 0x344,
117		.features = DMA_CURSOR_SDM845_MASK_SDMA,
118		.sblk = &dpu_dma_sblk,
119		.xin_id = 14,
120		.type = SSPP_TYPE_DMA,
121	}, {
122		.name = "sspp_13", .id = SSPP_DMA5,
123		.base = 0x2e000, .len = 0x344,
124		.features = DMA_CURSOR_SDM845_MASK_SDMA,
125		.sblk = &dpu_dma_sblk,
126		.xin_id = 15,
127		.type = SSPP_TYPE_DMA,
128	},
129};
130
131static const struct dpu_lm_cfg sm8550_lm[] = {
132	{
133		.name = "lm_0", .id = LM_0,
134		.base = 0x44000, .len = 0x400,
135		.features = MIXER_MSM8998_MASK,
136		.sblk = &sdm845_lm_sblk,
137		.lm_pair = LM_1,
138		.pingpong = PINGPONG_0,
139		.dspp = DSPP_0,
140	}, {
141		.name = "lm_1", .id = LM_1,
142		.base = 0x45000, .len = 0x400,
143		.features = MIXER_MSM8998_MASK,
144		.sblk = &sdm845_lm_sblk,
145		.lm_pair = LM_0,
146		.pingpong = PINGPONG_1,
147		.dspp = DSPP_1,
148	}, {
149		.name = "lm_2", .id = LM_2,
150		.base = 0x46000, .len = 0x400,
151		.features = MIXER_MSM8998_MASK,
152		.sblk = &sdm845_lm_sblk,
153		.lm_pair = LM_3,
154		.pingpong = PINGPONG_2,
155		.dspp = DSPP_2,
156	}, {
157		.name = "lm_3", .id = LM_3,
158		.base = 0x47000, .len = 0x400,
159		.features = MIXER_MSM8998_MASK,
160		.sblk = &sdm845_lm_sblk,
161		.lm_pair = LM_2,
162		.pingpong = PINGPONG_3,
163		.dspp = DSPP_3,
164	}, {
165		.name = "lm_4", .id = LM_4,
166		.base = 0x48000, .len = 0x400,
167		.features = MIXER_MSM8998_MASK,
168		.sblk = &sdm845_lm_sblk,
169		.lm_pair = LM_5,
170		.pingpong = PINGPONG_4,
171	}, {
172		.name = "lm_5", .id = LM_5,
173		.base = 0x49000, .len = 0x400,
174		.features = MIXER_MSM8998_MASK,
175		.sblk = &sdm845_lm_sblk,
176		.lm_pair = LM_4,
177		.pingpong = PINGPONG_5,
178	},
179};
180
181static const struct dpu_dspp_cfg sm8550_dspp[] = {
182	{
183		.name = "dspp_0", .id = DSPP_0,
184		.base = 0x54000, .len = 0x1800,
185		.sblk = &sdm845_dspp_sblk,
186	}, {
187		.name = "dspp_1", .id = DSPP_1,
188		.base = 0x56000, .len = 0x1800,
189		.sblk = &sdm845_dspp_sblk,
190	}, {
191		.name = "dspp_2", .id = DSPP_2,
192		.base = 0x58000, .len = 0x1800,
193		.sblk = &sdm845_dspp_sblk,
194	}, {
195		.name = "dspp_3", .id = DSPP_3,
196		.base = 0x5a000, .len = 0x1800,
197		.sblk = &sdm845_dspp_sblk,
198	},
199};
200static const struct dpu_pingpong_cfg sm8550_pp[] = {
201	{
202		.name = "pingpong_0", .id = PINGPONG_0,
203		.base = 0x69000, .len = 0,
204		.sblk = &sc7280_pp_sblk,
205		.merge_3d = MERGE_3D_0,
206		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
207	}, {
208		.name = "pingpong_1", .id = PINGPONG_1,
209		.base = 0x6a000, .len = 0,
210		.sblk = &sc7280_pp_sblk,
211		.merge_3d = MERGE_3D_0,
212		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
213	}, {
214		.name = "pingpong_2", .id = PINGPONG_2,
215		.base = 0x6b000, .len = 0,
216		.sblk = &sc7280_pp_sblk,
217		.merge_3d = MERGE_3D_1,
218		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
219	}, {
220		.name = "pingpong_3", .id = PINGPONG_3,
221		.base = 0x6c000, .len = 0,
222		.sblk = &sc7280_pp_sblk,
223		.merge_3d = MERGE_3D_1,
224		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
225	}, {
226		.name = "pingpong_4", .id = PINGPONG_4,
227		.base = 0x6d000, .len = 0,
228		.sblk = &sc7280_pp_sblk,
229		.merge_3d = MERGE_3D_2,
230		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
231	}, {
232		.name = "pingpong_5", .id = PINGPONG_5,
233		.base = 0x6e000, .len = 0,
234		.sblk = &sc7280_pp_sblk,
235		.merge_3d = MERGE_3D_2,
236		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
237	}, {
238		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
239		.base = 0x66000, .len = 0,
240		.sblk = &sc7280_pp_sblk,
241		.merge_3d = MERGE_3D_3,
242	}, {
243		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
244		.base = 0x66400, .len = 0,
245		.sblk = &sc7280_pp_sblk,
246		.merge_3d = MERGE_3D_3,
247	},
248};
249
250static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
251	{
252		.name = "merge_3d_0", .id = MERGE_3D_0,
253		.base = 0x4e000, .len = 0x8,
254	}, {
255		.name = "merge_3d_1", .id = MERGE_3D_1,
256		.base = 0x4f000, .len = 0x8,
257	}, {
258		.name = "merge_3d_2", .id = MERGE_3D_2,
259		.base = 0x50000, .len = 0x8,
260	}, {
261		.name = "merge_3d_3", .id = MERGE_3D_3,
262		.base = 0x66700, .len = 0x8,
263	},
264};
265
266/*
267 * NOTE: Each display compression engine (DCE) contains dual hard
268 * slice DSC encoders so both share same base address but with
269 * its own different sub block address.
270 */
271static const struct dpu_dsc_cfg sm8550_dsc[] = {
272	{
273		.name = "dce_0_0", .id = DSC_0,
274		.base = 0x80000, .len = 0x4,
275		.sblk = &dsc_sblk_0,
276	}, {
277		.name = "dce_0_1", .id = DSC_1,
278		.base = 0x80000, .len = 0x4,
279		.sblk = &dsc_sblk_1,
280	}, {
281		.name = "dce_1_0", .id = DSC_2,
282		.base = 0x81000, .len = 0x4,
283		.features = BIT(DPU_DSC_NATIVE_42x_EN),
284		.sblk = &dsc_sblk_0,
285	}, {
286		.name = "dce_1_1", .id = DSC_3,
287		.base = 0x81000, .len = 0x4,
288		.features = BIT(DPU_DSC_NATIVE_42x_EN),
289		.sblk = &dsc_sblk_1,
290	},
291};
292
293static const struct dpu_wb_cfg sm8550_wb[] = {
294	{
295		.name = "wb_2", .id = WB_2,
296		.base = 0x65000, .len = 0x2c8,
297		.features = WB_SDM845_MASK,
298		.format_list = wb2_formats_rgb_yuv,
299		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
300		.xin_id = 6,
301		.vbif_idx = VBIF_RT,
302		.maxlinewidth = 4096,
303		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
304	},
305};
306
307static const struct dpu_intf_cfg sm8550_intf[] = {
308	{
309		.name = "intf_0", .id = INTF_0,
310		.base = 0x34000, .len = 0x280,
311		.type = INTF_DP,
312		.controller_id = MSM_DP_CONTROLLER_0,
313		.prog_fetch_lines_worst_case = 24,
314		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
315		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
316	}, {
317		.name = "intf_1", .id = INTF_1,
318		.base = 0x35000, .len = 0x300,
319		.type = INTF_DSI,
320		.controller_id = MSM_DSI_CONTROLLER_0,
321		.prog_fetch_lines_worst_case = 24,
322		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
323		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
324		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
325	}, {
326		.name = "intf_2", .id = INTF_2,
327		.base = 0x36000, .len = 0x300,
328		.type = INTF_DSI,
329		.controller_id = MSM_DSI_CONTROLLER_1,
330		.prog_fetch_lines_worst_case = 24,
331		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
332		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
333		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
334	}, {
335		.name = "intf_3", .id = INTF_3,
336		.base = 0x37000, .len = 0x280,
337		.type = INTF_DP,
338		.controller_id = MSM_DP_CONTROLLER_1,
339		.prog_fetch_lines_worst_case = 24,
340		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
341		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
342	},
343};
344
345static const struct dpu_perf_cfg sm8550_perf_data = {
346	.max_bw_low = 13600000,
347	.max_bw_high = 18200000,
348	.min_core_ib = 2500000,
349	.min_llcc_ib = 0,
350	.min_dram_ib = 800000,
351	.min_prefill_lines = 35,
352	/* FIXME: lut tables */
353	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
354	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
355	.qos_lut_tbl = {
356		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
357		.entries = sc7180_qos_linear
358		},
359		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
360		.entries = sc7180_qos_macrotile
361		},
362		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
363		.entries = sc7180_qos_nrt
364		},
365		/* TODO: macrotile-qseed is different from macrotile */
366	},
367	.cdp_cfg = {
368		{.rd_enable = 1, .wr_enable = 1},
369		{.rd_enable = 1, .wr_enable = 0}
370	},
371	.clk_inefficiency_factor = 105,
372	.bw_inefficiency_factor = 120,
373};
374
375static const struct dpu_mdss_version sm8550_mdss_ver = {
376	.core_major_ver = 9,
377	.core_minor_ver = 0,
378};
379
380const struct dpu_mdss_cfg dpu_sm8550_cfg = {
381	.mdss_ver = &sm8550_mdss_ver,
382	.caps = &sm8550_dpu_caps,
383	.mdp = &sm8550_mdp,
384	.cdm = &dpu_cdm_5_x,
385	.ctl_count = ARRAY_SIZE(sm8550_ctl),
386	.ctl = sm8550_ctl,
387	.sspp_count = ARRAY_SIZE(sm8550_sspp),
388	.sspp = sm8550_sspp,
389	.mixer_count = ARRAY_SIZE(sm8550_lm),
390	.mixer = sm8550_lm,
391	.dspp_count = ARRAY_SIZE(sm8550_dspp),
392	.dspp = sm8550_dspp,
393	.pingpong_count = ARRAY_SIZE(sm8550_pp),
394	.pingpong = sm8550_pp,
395	.dsc_count = ARRAY_SIZE(sm8550_dsc),
396	.dsc = sm8550_dsc,
397	.merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),
398	.merge_3d = sm8550_merge_3d,
399	.wb_count = ARRAY_SIZE(sm8550_wb),
400	.wb = sm8550_wb,
401	.intf_count = ARRAY_SIZE(sm8550_intf),
402	.intf = sm8550_intf,
403	.vbif_count = ARRAY_SIZE(sm8550_vbif),
404	.vbif = sm8550_vbif,
405	.perf = &sm8550_perf_data,
406};
407
408#endif