dpu_8_4_sa8775p.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef _DPU_8_4_SA8775P_H
  7#define _DPU_8_4_SA8775P_H
  8
  9static const struct dpu_caps sa8775p_dpu_caps = {
 10	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 11	.max_mixer_blendstages = 0xb,
 12	.has_src_split = true,
 13	.has_dim_layer = true,
 14	.has_idle_pc = true,
 15	.has_3d_merge = true,
 16	.max_linewidth = 5120,
 17	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 18};
 19
 20static const struct dpu_mdp_cfg sa8775p_mdp = {
 21	.name = "top_0",
 22	.base = 0x0, .len = 0x494,
 23	.clk_ctrls = {
 24		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 25		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 26		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
 27		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
 28		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 29		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 30		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
 31		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
 32		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
 33		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
 34	},
 35};
 36
 37static const struct dpu_ctl_cfg sa8775p_ctl[] = {
 38	{
 39		.name = "ctl_0", .id = CTL_0,
 40		.base = 0x15000, .len = 0x204,
 41		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 42	}, {
 43		.name = "ctl_1", .id = CTL_1,
 44		.base = 0x16000, .len = 0x204,
 45		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 46	}, {
 47		.name = "ctl_2", .id = CTL_2,
 48		.base = 0x17000, .len = 0x204,
 49		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 50	}, {
 51		.name = "ctl_3", .id = CTL_3,
 52		.base = 0x18000, .len = 0x204,
 53		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 54	}, {
 55		.name = "ctl_4", .id = CTL_4,
 56		.base = 0x19000, .len = 0x204,
 57		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 58	}, {
 59		.name = "ctl_5", .id = CTL_5,
 60		.base = 0x1a000, .len = 0x204,
 61		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 62	},
 63};
 64
 65static const struct dpu_sspp_cfg sa8775p_sspp[] = {
 66	{
 67		.name = "sspp_0", .id = SSPP_VIG0,
 68		.base = 0x4000, .len = 0x32c,
 69		.features = VIG_SDM845_MASK_SDMA,
 70		.sblk = &dpu_vig_sblk_qseed3_3_1,
 71		.xin_id = 0,
 72		.type = SSPP_TYPE_VIG,
 73		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 74	}, {
 75		.name = "sspp_1", .id = SSPP_VIG1,
 76		.base = 0x6000, .len = 0x32c,
 77		.features = VIG_SDM845_MASK_SDMA,
 78		.sblk = &dpu_vig_sblk_qseed3_3_1,
 79		.xin_id = 4,
 80		.type = SSPP_TYPE_VIG,
 81		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 82	}, {
 83		.name = "sspp_2", .id = SSPP_VIG2,
 84		.base = 0x8000, .len = 0x32c,
 85		.features = VIG_SDM845_MASK_SDMA,
 86		.sblk = &dpu_vig_sblk_qseed3_3_1,
 87		.xin_id = 8,
 88		.type = SSPP_TYPE_VIG,
 89		.clk_ctrl = DPU_CLK_CTRL_VIG2,
 90	}, {
 91		.name = "sspp_3", .id = SSPP_VIG3,
 92		.base = 0xa000, .len = 0x32c,
 93		.features = VIG_SDM845_MASK_SDMA,
 94		.sblk = &dpu_vig_sblk_qseed3_3_1,
 95		.xin_id = 12,
 96		.type = SSPP_TYPE_VIG,
 97		.clk_ctrl = DPU_CLK_CTRL_VIG3,
 98	}, {
 99		.name = "sspp_8", .id = SSPP_DMA0,
100		.base = 0x24000, .len = 0x32c,
101		.features = DMA_SDM845_MASK_SDMA,
102		.sblk = &dpu_dma_sblk,
103		.xin_id = 1,
104		.type = SSPP_TYPE_DMA,
105		.clk_ctrl = DPU_CLK_CTRL_DMA0,
106	}, {
107		.name = "sspp_9", .id = SSPP_DMA1,
108		.base = 0x26000, .len = 0x32c,
109		.features = DMA_SDM845_MASK_SDMA,
110		.sblk = &dpu_dma_sblk,
111		.xin_id = 5,
112		.type = SSPP_TYPE_DMA,
113		.clk_ctrl = DPU_CLK_CTRL_DMA1,
114	}, {
115		.name = "sspp_10", .id = SSPP_DMA2,
116		.base = 0x28000, .len = 0x32c,
117		.features = DMA_CURSOR_SDM845_MASK_SDMA,
118		.sblk = &dpu_dma_sblk,
119		.xin_id = 9,
120		.type = SSPP_TYPE_DMA,
121		.clk_ctrl = DPU_CLK_CTRL_DMA2,
122	}, {
123		.name = "sspp_11", .id = SSPP_DMA3,
124		.base = 0x2a000, .len = 0x32c,
125		.features = DMA_CURSOR_SDM845_MASK_SDMA,
126		.sblk = &dpu_dma_sblk,
127		.xin_id = 13,
128		.type = SSPP_TYPE_DMA,
129		.clk_ctrl = DPU_CLK_CTRL_DMA3,
130	},
131};
132
133static const struct dpu_lm_cfg sa8775p_lm[] = {
134	{
135		.name = "lm_0", .id = LM_0,
136		.base = 0x44000, .len = 0x400,
137		.features = MIXER_MSM8998_MASK,
138		.sblk = &sdm845_lm_sblk,
139		.lm_pair = LM_1,
140		.pingpong = PINGPONG_0,
141		.dspp = DSPP_0,
142	}, {
143		.name = "lm_1", .id = LM_1,
144		.base = 0x45000, .len = 0x400,
145		.features = MIXER_MSM8998_MASK,
146		.sblk = &sdm845_lm_sblk,
147		.lm_pair = LM_0,
148		.pingpong = PINGPONG_1,
149		.dspp = DSPP_1,
150	}, {
151		.name = "lm_2", .id = LM_2,
152		.base = 0x46000, .len = 0x400,
153		.features = MIXER_MSM8998_MASK,
154		.sblk = &sdm845_lm_sblk,
155		.lm_pair = LM_3,
156		.pingpong = PINGPONG_2,
157		.dspp = DSPP_2,
158	}, {
159		.name = "lm_3", .id = LM_3,
160		.base = 0x47000, .len = 0x400,
161		.features = MIXER_MSM8998_MASK,
162		.sblk = &sdm845_lm_sblk,
163		.lm_pair = LM_2,
164		.pingpong = PINGPONG_3,
165		.dspp = DSPP_3,
166	}, {
167		.name = "lm_4", .id = LM_4,
168		.base = 0x48000, .len = 0x400,
169		.features = MIXER_MSM8998_MASK,
170		.sblk = &sdm845_lm_sblk,
171		.lm_pair = LM_5,
172		.pingpong = PINGPONG_4,
173	}, {
174		.name = "lm_5", .id = LM_5,
175		.base = 0x49000, .len = 0x400,
176		.features = MIXER_MSM8998_MASK,
177		.sblk = &sdm845_lm_sblk,
178		.lm_pair = LM_4,
179		.pingpong = PINGPONG_5,
180	},
181};
182
183static const struct dpu_dspp_cfg sa8775p_dspp[] = {
184	{
185		.name = "dspp_0", .id = DSPP_0,
186		.base = 0x54000, .len = 0x1800,
187		.sblk = &sdm845_dspp_sblk,
188	}, {
189		.name = "dspp_1", .id = DSPP_1,
190		.base = 0x56000, .len = 0x1800,
191		.sblk = &sdm845_dspp_sblk,
192	}, {
193		.name = "dspp_2", .id = DSPP_2,
194		.base = 0x58000, .len = 0x1800,
195		.sblk = &sdm845_dspp_sblk,
196	}, {
197		.name = "dspp_3", .id = DSPP_3,
198		.base = 0x5a000, .len = 0x1800,
199		.sblk = &sdm845_dspp_sblk,
200	},
201};
202
203static const struct dpu_pingpong_cfg sa8775p_pp[] = {
204	{
205		.name = "pingpong_0", .id = PINGPONG_0,
206		.base = 0x69000, .len = 0,
207		.sblk = &sc7280_pp_sblk,
208		.merge_3d = MERGE_3D_0,
209		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
210	}, {
211		.name = "pingpong_1", .id = PINGPONG_1,
212		.base = 0x6a000, .len = 0,
213		.sblk = &sc7280_pp_sblk,
214		.merge_3d = MERGE_3D_0,
215		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
216	}, {
217		.name = "pingpong_2", .id = PINGPONG_2,
218		.base = 0x6b000, .len = 0,
219		.sblk = &sc7280_pp_sblk,
220		.merge_3d = MERGE_3D_1,
221		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
222	}, {
223		.name = "pingpong_3", .id = PINGPONG_3,
224		.base = 0x6c000, .len = 0,
225		.sblk = &sc7280_pp_sblk,
226		.merge_3d = MERGE_3D_1,
227		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
228	}, {
229		.name = "pingpong_4", .id = PINGPONG_4,
230		.base = 0x6d000, .len = 0,
231		.sblk = &sc7280_pp_sblk,
232		.merge_3d = MERGE_3D_2,
233		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
234	}, {
235		.name = "pingpong_5", .id = PINGPONG_5,
236		.base = 0x6e000, .len = 0,
237		.sblk = &sc7280_pp_sblk,
238		.merge_3d = MERGE_3D_2,
239		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
240	}, {
241		.name = "pingpong_6", .id = PINGPONG_CWB_0,
242		.base = 0x65800, .len = 0,
243		.sblk = &sc7280_pp_sblk,
244		.merge_3d = MERGE_3D_3,
245	}, {
246		.name = "pingpong_7", .id = PINGPONG_CWB_1,
247		.base = 0x65c00, .len = 0,
248		.sblk = &sc7280_pp_sblk,
249		.merge_3d = MERGE_3D_3,
250	},
251};
252
253static const struct dpu_merge_3d_cfg sa8775p_merge_3d[] = {
254	{
255		.name = "merge_3d_0", .id = MERGE_3D_0,
256		.base = 0x4e000, .len = 0x8,
257	}, {
258		.name = "merge_3d_1", .id = MERGE_3D_1,
259		.base = 0x4f000, .len = 0x8,
260	}, {
261		.name = "merge_3d_2", .id = MERGE_3D_2,
262		.base = 0x50000, .len = 0x8,
263	}, {
264		.name = "merge_3d_3", .id = MERGE_3D_3,
265		.base = 0x65f00, .len = 0x8,
266	},
267};
268
269/*
270 * NOTE: Each display compression engine (DCE) contains dual hard
271 * slice DSC encoders so both share same base address but with
272 * its own different sub block address.
273 */
274static const struct dpu_dsc_cfg sa8775p_dsc[] = {
275	{
276		.name = "dce_0_0", .id = DSC_0,
277		.base = 0x80000, .len = 0x4,
278		.sblk = &dsc_sblk_0,
279	}, {
280		.name = "dce_0_1", .id = DSC_1,
281		.base = 0x80000, .len = 0x4,
282		.sblk = &dsc_sblk_1,
283	}, {
284		.name = "dce_1_0", .id = DSC_2,
285		.base = 0x81000, .len = 0x4,
286		.features = BIT(DPU_DSC_NATIVE_42x_EN),
287		.sblk = &dsc_sblk_0,
288	}, {
289		.name = "dce_1_1", .id = DSC_3,
290		.base = 0x81000, .len = 0x4,
291		.features = BIT(DPU_DSC_NATIVE_42x_EN),
292		.sblk = &dsc_sblk_1,
293	}, {
294		.name = "dce_2_0", .id = DSC_4,
295		.base = 0x82000, .len = 0x4,
296		.sblk = &dsc_sblk_0,
297	}, {
298		.name = "dce_2_1", .id = DSC_5,
299		.base = 0x82000, .len = 0x4,
300		.sblk = &dsc_sblk_1,
301	},
302};
303
304static const struct dpu_wb_cfg sa8775p_wb[] = {
305	{
306		.name = "wb_2", .id = WB_2,
307		.base = 0x65000, .len = 0x2c8,
308		.features = WB_SDM845_MASK,
309		.format_list = wb2_formats_rgb_yuv,
310		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
311		.clk_ctrl = DPU_CLK_CTRL_WB2,
312		.xin_id = 6,
313		.vbif_idx = VBIF_RT,
314		.maxlinewidth = 4096,
315		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
316	},
317};
318
319/* TODO: INTF 3, 6, 7 and 8 are used for MST, marked as INTF_NONE for now */
320static const struct dpu_intf_cfg sa8775p_intf[] = {
321	{
322		.name = "intf_0", .id = INTF_0,
323		.base = 0x34000, .len = 0x280,
324		.type = INTF_DP,
325		.controller_id = MSM_DP_CONTROLLER_0,
326		.prog_fetch_lines_worst_case = 24,
327		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
328		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
329	}, {
330		.name = "intf_1", .id = INTF_1,
331		.base = 0x35000, .len = 0x300,
332		.type = INTF_DSI,
333		.controller_id = MSM_DSI_CONTROLLER_0,
334		.prog_fetch_lines_worst_case = 24,
335		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
336		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
337		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
338	}, {
339		.name = "intf_2", .id = INTF_2,
340		.base = 0x36000, .len = 0x300,
341		.type = INTF_DSI,
342		.controller_id = MSM_DSI_CONTROLLER_1,
343		.prog_fetch_lines_worst_case = 24,
344		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
345		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
346		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
347	}, {
348		.name = "intf_3", .id = INTF_3,
349		.base = 0x37000, .len = 0x280,
350		.type = INTF_NONE,
351		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
352		.prog_fetch_lines_worst_case = 24,
353		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
354		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
355	}, {
356		.name = "intf_4", .id = INTF_4,
357		.base = 0x38000, .len = 0x280,
358		.type = INTF_DP,
359		.controller_id = MSM_DP_CONTROLLER_1,
360		.prog_fetch_lines_worst_case = 24,
361		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
362		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
363	}, {
364		.name = "intf_6", .id = INTF_6,
365		.base = 0x3A000, .len = 0x280,
366		.type = INTF_NONE,
367		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
368		.prog_fetch_lines_worst_case = 24,
369		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
370		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
371	}, {
372		.name = "intf_7", .id = INTF_7,
373		.base = 0x3b000, .len = 0x280,
374		.type = INTF_NONE,
375		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
376		.prog_fetch_lines_worst_case = 24,
377		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
378		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
379	}, {
380		.name = "intf_8", .id = INTF_8,
381		.base = 0x3c000, .len = 0x280,
382		.type = INTF_NONE,
383		.controller_id = MSM_DP_CONTROLLER_1,	/* pair with intf_4 for DP MST */
384		.prog_fetch_lines_worst_case = 24,
385		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
386		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
387	},
388};
389
390static const struct dpu_perf_cfg sa8775p_perf_data = {
391	.max_bw_low = 13600000,
392	.max_bw_high = 18200000,
393	.min_core_ib = 2500000,
394	.min_llcc_ib = 0,
395	.min_dram_ib = 800000,
396	.min_prefill_lines = 35,
397	/* FIXME: lut tables */
398	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
399	.safe_lut_tbl = {0xfff0, 0xfff0, 0x1},
400	.qos_lut_tbl = {
401		{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
402		.entries = sm6350_qos_linear_macrotile
403		},
404		{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
405		.entries = sm6350_qos_linear_macrotile
406		},
407		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
408		.entries = sc7180_qos_nrt
409		},
410		/* TODO: macrotile-qseed is different from macrotile */
411	},
412	.cdp_cfg = {
413		{.rd_enable = 1, .wr_enable = 1},
414		{.rd_enable = 1, .wr_enable = 0}
415	},
416	.clk_inefficiency_factor = 105,
417	.bw_inefficiency_factor = 120,
418};
419
420static const struct dpu_mdss_version sa8775p_mdss_ver = {
421	.core_major_ver = 8,
422	.core_minor_ver = 4,
423};
424
425const struct dpu_mdss_cfg dpu_sa8775p_cfg = {
426	.mdss_ver = &sa8775p_mdss_ver,
427	.caps = &sa8775p_dpu_caps,
428	.mdp = &sa8775p_mdp,
429	.cdm = &dpu_cdm_5_x,
430	.ctl_count = ARRAY_SIZE(sa8775p_ctl),
431	.ctl = sa8775p_ctl,
432	.sspp_count = ARRAY_SIZE(sa8775p_sspp),
433	.sspp = sa8775p_sspp,
434	.mixer_count = ARRAY_SIZE(sa8775p_lm),
435	.mixer = sa8775p_lm,
436	.dspp_count = ARRAY_SIZE(sa8775p_dspp),
437	.dspp = sa8775p_dspp,
438	.pingpong_count = ARRAY_SIZE(sa8775p_pp),
439	.pingpong = sa8775p_pp,
440	.dsc_count = ARRAY_SIZE(sa8775p_dsc),
441	.dsc = sa8775p_dsc,
442	.merge_3d_count = ARRAY_SIZE(sa8775p_merge_3d),
443	.merge_3d = sa8775p_merge_3d,
444	.wb_count = ARRAY_SIZE(sa8775p_wb),
445	.wb = sa8775p_wb,
446	.intf_count = ARRAY_SIZE(sa8775p_intf),
447	.intf = sa8775p_intf,
448	.vbif_count = ARRAY_SIZE(sdm845_vbif),
449	.vbif = sdm845_vbif,
450	.perf = &sa8775p_perf_data,
451};
452
453#endif