dpu_7_2_sc7280.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_7_2_SC7280_H
  8#define _DPU_7_2_SC7280_H
  9
 10static const struct dpu_caps sc7280_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0x7,
 13	.has_dim_layer = true,
 14	.has_idle_pc = true,
 15	.max_linewidth = 2400,
 16	.has_3d_merge = true,
 17	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 18};
 19
 20static const struct dpu_mdp_cfg sc7280_mdp = {
 21	.name = "top_0",
 22	.base = 0x0, .len = 0x2014,
 23	.clk_ctrls = {
 24		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 25		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 26		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 27		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
 28		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
 29	},
 30};
 31
 32static const struct dpu_ctl_cfg sc7280_ctl[] = {
 33	{
 34		.name = "ctl_0", .id = CTL_0,
 35		.base = 0x15000, .len = 0x1e8,
 36		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 37	}, {
 38		.name = "ctl_1", .id = CTL_1,
 39		.base = 0x16000, .len = 0x1e8,
 40		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 41	}, {
 42		.name = "ctl_2", .id = CTL_2,
 43		.base = 0x17000, .len = 0x1e8,
 44		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 45	}, {
 46		.name = "ctl_3", .id = CTL_3,
 47		.base = 0x18000, .len = 0x1e8,
 48		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 49	},
 50};
 51
 52static const struct dpu_sspp_cfg sc7280_sspp[] = {
 53	{
 54		.name = "sspp_0", .id = SSPP_VIG0,
 55		.base = 0x4000, .len = 0x1f8,
 56		.features = VIG_SC7280_MASK_SDMA,
 57		.sblk = &dpu_vig_sblk_qseed3_3_0_rot_v2,
 58		.xin_id = 0,
 59		.type = SSPP_TYPE_VIG,
 60		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 61	}, {
 62		.name = "sspp_8", .id = SSPP_DMA0,
 63		.base = 0x24000, .len = 0x1f8,
 64		.features = DMA_SDM845_MASK_SDMA,
 65		.sblk = &dpu_dma_sblk,
 66		.xin_id = 1,
 67		.type = SSPP_TYPE_DMA,
 68		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 69	}, {
 70		.name = "sspp_9", .id = SSPP_DMA1,
 71		.base = 0x26000, .len = 0x1f8,
 72		.features = DMA_CURSOR_SDM845_MASK_SDMA,
 73		.sblk = &dpu_dma_sblk,
 74		.xin_id = 5,
 75		.type = SSPP_TYPE_DMA,
 76		.clk_ctrl = DPU_CLK_CTRL_DMA1,
 77	}, {
 78		.name = "sspp_10", .id = SSPP_DMA2,
 79		.base = 0x28000, .len = 0x1f8,
 80		.features = DMA_CURSOR_SDM845_MASK_SDMA,
 81		.sblk = &dpu_dma_sblk,
 82		.xin_id = 9,
 83		.type = SSPP_TYPE_DMA,
 84		.clk_ctrl = DPU_CLK_CTRL_DMA2,
 85	},
 86};
 87
 88static const struct dpu_lm_cfg sc7280_lm[] = {
 89	{
 90		.name = "lm_0", .id = LM_0,
 91		.base = 0x44000, .len = 0x320,
 92		.features = MIXER_MSM8998_MASK,
 93		.sblk = &sc7180_lm_sblk,
 94		.pingpong = PINGPONG_0,
 95		.dspp = DSPP_0,
 96	}, {
 97		.name = "lm_2", .id = LM_2,
 98		.base = 0x46000, .len = 0x320,
 99		.features = MIXER_MSM8998_MASK,
100		.sblk = &sc7180_lm_sblk,
101		.lm_pair = LM_3,
102		.pingpong = PINGPONG_2,
103	}, {
104		.name = "lm_3", .id = LM_3,
105		.base = 0x47000, .len = 0x320,
106		.features = MIXER_MSM8998_MASK,
107		.sblk = &sc7180_lm_sblk,
108		.lm_pair = LM_2,
109		.pingpong = PINGPONG_3,
110	},
111};
112
113static const struct dpu_dspp_cfg sc7280_dspp[] = {
114	{
115		.name = "dspp_0", .id = DSPP_0,
116		.base = 0x54000, .len = 0x1800,
117		.sblk = &sdm845_dspp_sblk,
118	},
119};
120
121static const struct dpu_pingpong_cfg sc7280_pp[] = {
122	{
123		.name = "pingpong_0", .id = PINGPONG_0,
124		.base = 0x69000, .len = 0,
125		.sblk = &sc7280_pp_sblk,
126		.merge_3d = 0,
127		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
128	}, {
129		.name = "pingpong_1", .id = PINGPONG_1,
130		.base = 0x6a000, .len = 0,
131		.sblk = &sc7280_pp_sblk,
132		.merge_3d = 0,
133		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
134	}, {
135		.name = "pingpong_2", .id = PINGPONG_2,
136		.base = 0x6b000, .len = 0,
137		.sblk = &sc7280_pp_sblk,
138		.merge_3d = MERGE_3D_1,
139		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
140	}, {
141		.name = "pingpong_3", .id = PINGPONG_3,
142		.base = 0x6c000, .len = 0,
143		.sblk = &sc7280_pp_sblk,
144		.merge_3d = MERGE_3D_1,
145		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
146	},
147};
148
149static const struct dpu_merge_3d_cfg sc7280_merge_3d[] = {
150	{
151		.name = "merge_3d_1", .id = MERGE_3D_1,
152		.base = 0x4f000, .len = 0x8,
153	},
154};
155
156/* NOTE: sc7280 only has one DSC hard slice encoder */
157static const struct dpu_dsc_cfg sc7280_dsc[] = {
158	{
159		.name = "dce_0_0", .id = DSC_0,
160		.base = 0x80000, .len = 0x4,
161		.features = BIT(DPU_DSC_NATIVE_42x_EN),
162		.sblk = &dsc_sblk_0,
163	},
164};
165
166static const struct dpu_wb_cfg sc7280_wb[] = {
167	{
168		.name = "wb_2", .id = WB_2,
169		.base = 0x65000, .len = 0x2c8,
170		.features = WB_SDM845_MASK,
171		.format_list = wb2_formats_rgb_yuv,
172		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
173		.clk_ctrl = DPU_CLK_CTRL_WB2,
174		.xin_id = 6,
175		.vbif_idx = VBIF_RT,
176		.maxlinewidth = 4096,
177		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
178	},
179};
180
181static const struct dpu_intf_cfg sc7280_intf[] = {
182	{
183		.name = "intf_0", .id = INTF_0,
184		.base = 0x34000, .len = 0x280,
185		.type = INTF_DP,
186		.controller_id = MSM_DP_CONTROLLER_0,
187		.prog_fetch_lines_worst_case = 24,
188		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
189		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
190	}, {
191		.name = "intf_1", .id = INTF_1,
192		.base = 0x35000, .len = 0x2c4,
193		.type = INTF_DSI,
194		.controller_id = MSM_DSI_CONTROLLER_0,
195		.prog_fetch_lines_worst_case = 24,
196		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
197		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
198		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
199	}, {
200		.name = "intf_5", .id = INTF_5,
201		.base = 0x39000, .len = 0x280,
202		.type = INTF_DP,
203		.controller_id = MSM_DP_CONTROLLER_1,
204		.prog_fetch_lines_worst_case = 24,
205		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
206		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
207	},
208};
209
210static const struct dpu_perf_cfg sc7280_perf_data = {
211	.max_bw_low = 4700000,
212	.max_bw_high = 8800000,
213	.min_core_ib = 2500000,
214	.min_llcc_ib = 0,
215	.min_dram_ib = 1600000,
216	.min_prefill_lines = 24,
217	.danger_lut_tbl = {0xffff, 0xffff, 0x0},
218	.safe_lut_tbl = {0xff00, 0xff00, 0xffff},
219	.qos_lut_tbl = {
220		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
221		.entries = sc7180_qos_macrotile
222		},
223		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
224		.entries = sc7180_qos_macrotile
225		},
226		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
227		.entries = sc7180_qos_nrt
228		},
229	},
230	.cdp_cfg = {
231		{.rd_enable = 1, .wr_enable = 1},
232		{.rd_enable = 1, .wr_enable = 0}
233	},
234	.clk_inefficiency_factor = 105,
235	.bw_inefficiency_factor = 120,
236};
237
238static const struct dpu_mdss_version sc7280_mdss_ver = {
239	.core_major_ver = 7,
240	.core_minor_ver = 2,
241};
242
243const struct dpu_mdss_cfg dpu_sc7280_cfg = {
244	.mdss_ver = &sc7280_mdss_ver,
245	.caps = &sc7280_dpu_caps,
246	.mdp = &sc7280_mdp,
247	.cdm = &dpu_cdm_5_x,
248	.ctl_count = ARRAY_SIZE(sc7280_ctl),
249	.ctl = sc7280_ctl,
250	.sspp_count = ARRAY_SIZE(sc7280_sspp),
251	.sspp = sc7280_sspp,
252	.dspp_count = ARRAY_SIZE(sc7280_dspp),
253	.dspp = sc7280_dspp,
254	.mixer_count = ARRAY_SIZE(sc7280_lm),
255	.mixer = sc7280_lm,
256	.pingpong_count = ARRAY_SIZE(sc7280_pp),
257	.pingpong = sc7280_pp,
258	.merge_3d_count = ARRAY_SIZE(sc7280_merge_3d),
259	.merge_3d = sc7280_merge_3d,
260	.dsc_count = ARRAY_SIZE(sc7280_dsc),
261	.dsc = sc7280_dsc,
262	.wb_count = ARRAY_SIZE(sc7280_wb),
263	.wb = sc7280_wb,
264	.intf_count = ARRAY_SIZE(sc7280_intf),
265	.intf = sc7280_intf,
266	.vbif_count = ARRAY_SIZE(sdm845_vbif),
267	.vbif = sdm845_vbif,
268	.perf = &sc7280_perf_data,
269};
270
271#endif