dpu_6_9_sm6375.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 * Copyright (c) 2023, Linaro Limited
  6 */
  7
  8#ifndef _DPU_6_9_SM6375_H
  9#define _DPU_6_9_SM6375_H
 10
 11static const struct dpu_caps sm6375_dpu_caps = {
 12	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
 13	.max_mixer_blendstages = 0x4,
 14	.has_dim_layer = true,
 15	.has_idle_pc = true,
 16	.max_linewidth = 2160,
 17	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 18};
 19
 20static const struct dpu_mdp_cfg sm6375_mdp = {
 21	.name = "top_0",
 22	.base = 0x0, .len = 0x494,
 23	.clk_ctrls = {
 24		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 25		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 26	},
 27};
 28
 29static const struct dpu_ctl_cfg sm6375_ctl[] = {
 30	{
 31		.name = "ctl_0", .id = CTL_0,
 32		.base = 0x1000, .len = 0x1dc,
 33		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 34	},
 35};
 36
 37static const struct dpu_sspp_cfg sm6375_sspp[] = {
 38	{
 39		.name = "sspp_0", .id = SSPP_VIG0,
 40		.base = 0x4000, .len = 0x1f8,
 41		.features = VIG_SDM845_MASK_NO_SDMA,
 42		.sblk = &dpu_vig_sblk_qseed3_3_0,
 43		.xin_id = 0,
 44		.type = SSPP_TYPE_VIG,
 45		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 46	}, {
 47		.name = "sspp_8", .id = SSPP_DMA0,
 48		.base = 0x24000, .len = 0x1f8,
 49		.features = DMA_SDM845_MASK_NO_SDMA,
 50		.sblk = &dpu_dma_sblk,
 51		.xin_id = 1,
 52		.type = SSPP_TYPE_DMA,
 53		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 54	},
 55};
 56
 57static const struct dpu_lm_cfg sm6375_lm[] = {
 58	{
 59		.name = "lm_0", .id = LM_0,
 60		.base = 0x44000, .len = 0x320,
 61		.sblk = &qcm2290_lm_sblk,
 62		.lm_pair = 0,
 63		.pingpong = PINGPONG_0,
 64		.dspp = DSPP_0,
 65	},
 66};
 67
 68static const struct dpu_dspp_cfg sm6375_dspp[] = {
 69	{
 70		.name = "dspp_0", .id = DSPP_0,
 71		.base = 0x54000, .len = 0x1800,
 72		.sblk = &sdm845_dspp_sblk,
 73	},
 74};
 75
 76static const struct dpu_pingpong_cfg sm6375_pp[] = {
 77	{
 78		.name = "pingpong_0", .id = PINGPONG_0,
 79		.base = 0x70000, .len = 0xd4,
 80		.sblk = &sdm845_pp_sblk,
 81		.merge_3d = 0,
 82		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 83	},
 84};
 85
 86static const struct dpu_dsc_cfg sm6375_dsc[] = {
 87	{
 88		.name = "dsc_0", .id = DSC_0,
 89		.base = 0x80000, .len = 0x140,
 90	},
 91};
 92
 93static const struct dpu_intf_cfg sm6375_intf[] = {
 94	{
 95		.name = "intf_1", .id = INTF_1,
 96		.base = 0x6a800, .len = 0x2c0,
 97		.type = INTF_DSI,
 98		.controller_id = MSM_DSI_CONTROLLER_0,
 99		.prog_fetch_lines_worst_case = 24,
100		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
101		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
102		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
103	},
104};
105
106static const struct dpu_perf_cfg sm6375_perf_data = {
107	.max_bw_low = 5200000,
108	.max_bw_high = 6200000,
109	.min_core_ib = 2500000,
110	.min_llcc_ib = 0, /* No LLCC on this SoC */
111	.min_dram_ib = 1600000,
112	.min_prefill_lines = 24,
113	/* TODO: confirm danger_lut_tbl */
114	.danger_lut_tbl = {0xffff, 0xffff, 0x0},
115	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
116	.qos_lut_tbl = {
117		{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
118		.entries = sm6350_qos_linear_macrotile
119		},
120		{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
121		.entries = sm6350_qos_linear_macrotile
122		},
123		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
124		.entries = sc7180_qos_nrt
125		},
126	},
127	.cdp_cfg = {
128		{.rd_enable = 1, .wr_enable = 1},
129		{.rd_enable = 1, .wr_enable = 0}
130	},
131	.clk_inefficiency_factor = 105,
132	.bw_inefficiency_factor = 120,
133};
134
135static const struct dpu_mdss_version sm6375_mdss_ver = {
136	.core_major_ver = 6,
137	.core_minor_ver = 9,
138};
139
140const struct dpu_mdss_cfg dpu_sm6375_cfg = {
141	.mdss_ver = &sm6375_mdss_ver,
142	.caps = &sm6375_dpu_caps,
143	.mdp = &sm6375_mdp,
144	.ctl_count = ARRAY_SIZE(sm6375_ctl),
145	.ctl = sm6375_ctl,
146	.sspp_count = ARRAY_SIZE(sm6375_sspp),
147	.sspp = sm6375_sspp,
148	.mixer_count = ARRAY_SIZE(sm6375_lm),
149	.mixer = sm6375_lm,
150	.dspp_count = ARRAY_SIZE(sm6375_dspp),
151	.dspp = sm6375_dspp,
152	.dsc_count = ARRAY_SIZE(sm6375_dsc),
153	.dsc = sm6375_dsc,
154	.pingpong_count = ARRAY_SIZE(sm6375_pp),
155	.pingpong = sm6375_pp,
156	.intf_count = ARRAY_SIZE(sm6375_intf),
157	.intf = sm6375_intf,
158	.vbif_count = ARRAY_SIZE(sdm845_vbif),
159	.vbif = sdm845_vbif,
160	.perf = &sm6375_perf_data,
161};
162
163#endif