dpu_6_2_sc7180.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_6_2_SC7180_H
  8#define _DPU_6_2_SC7180_H
  9
 10static const struct dpu_caps sc7180_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0x9,
 13	.has_dim_layer = true,
 14	.has_idle_pc = true,
 15	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 16	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 17};
 18
 19static const struct dpu_mdp_cfg sc7180_mdp = {
 20	.name = "top_0",
 21	.base = 0x0, .len = 0x494,
 22	.clk_ctrls = {
 23		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 24		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 25		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 26		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
 27		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
 28	},
 29};
 30
 31static const struct dpu_ctl_cfg sc7180_ctl[] = {
 32	{
 33		.name = "ctl_0", .id = CTL_0,
 34		.base = 0x1000, .len = 0x1dc,
 35		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 36	}, {
 37		.name = "ctl_1", .id = CTL_1,
 38		.base = 0x1200, .len = 0x1dc,
 39		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 40	}, {
 41		.name = "ctl_2", .id = CTL_2,
 42		.base = 0x1400, .len = 0x1dc,
 43		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 44	},
 45};
 46
 47static const struct dpu_sspp_cfg sc7180_sspp[] = {
 48	{
 49		.name = "sspp_0", .id = SSPP_VIG0,
 50		.base = 0x4000, .len = 0x1f8,
 51		.features = VIG_SDM845_MASK_NO_SDMA,
 52		.sblk = &dpu_vig_sblk_qseed3_3_0,
 53		.xin_id = 0,
 54		.type = SSPP_TYPE_VIG,
 55		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 56	}, {
 57		.name = "sspp_8", .id = SSPP_DMA0,
 58		.base = 0x24000, .len = 0x1f8,
 59		.features = DMA_SDM845_MASK_NO_SDMA,
 60		.sblk = &dpu_dma_sblk,
 61		.xin_id = 1,
 62		.type = SSPP_TYPE_DMA,
 63		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 64	}, {
 65		.name = "sspp_9", .id = SSPP_DMA1,
 66		.base = 0x26000, .len = 0x1f8,
 67		.features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
 68		.sblk = &dpu_dma_sblk,
 69		.xin_id = 5,
 70		.type = SSPP_TYPE_DMA,
 71		.clk_ctrl = DPU_CLK_CTRL_DMA1,
 72	}, {
 73		.name = "sspp_10", .id = SSPP_DMA2,
 74		.base = 0x28000, .len = 0x1f8,
 75		.features = DMA_CURSOR_SDM845_MASK_NO_SDMA,
 76		.sblk = &dpu_dma_sblk,
 77		.xin_id = 9,
 78		.type = SSPP_TYPE_DMA,
 79		.clk_ctrl = DPU_CLK_CTRL_DMA2,
 80	},
 81};
 82
 83static const struct dpu_lm_cfg sc7180_lm[] = {
 84	{
 85		.name = "lm_0", .id = LM_0,
 86		.base = 0x44000, .len = 0x320,
 87		.features = MIXER_MSM8998_MASK,
 88		.sblk = &sc7180_lm_sblk,
 89		.lm_pair = LM_1,
 90		.pingpong = PINGPONG_0,
 91		.dspp = DSPP_0,
 92	}, {
 93		.name = "lm_1", .id = LM_1,
 94		.base = 0x45000, .len = 0x320,
 95		.features = MIXER_MSM8998_MASK,
 96		.sblk = &sc7180_lm_sblk,
 97		.lm_pair = LM_0,
 98		.pingpong = PINGPONG_1,
 99	},
100};
101
102static const struct dpu_dspp_cfg sc7180_dspp[] = {
103	{
104		.name = "dspp_0", .id = DSPP_0,
105		.base = 0x54000, .len = 0x1800,
106		.sblk = &sdm845_dspp_sblk,
107	},
108};
109
110static const struct dpu_pingpong_cfg sc7180_pp[] = {
111	{
112		.name = "pingpong_0", .id = PINGPONG_0,
113		.base = 0x70000, .len = 0xd4,
114		.sblk = &sdm845_pp_sblk,
115		.merge_3d = 0,
116		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
117	}, {
118		.name = "pingpong_1", .id = PINGPONG_1,
119		.base = 0x70800, .len = 0xd4,
120		.sblk = &sdm845_pp_sblk,
121		.merge_3d = 0,
122		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
123	},
124};
125
126static const struct dpu_intf_cfg sc7180_intf[] = {
127	{
128		.name = "intf_0", .id = INTF_0,
129		.base = 0x6a000, .len = 0x280,
130		.type = INTF_DP,
131		.controller_id = MSM_DP_CONTROLLER_0,
132		.prog_fetch_lines_worst_case = 24,
133		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
134		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
135	}, {
136		.name = "intf_1", .id = INTF_1,
137		.base = 0x6a800, .len = 0x2c0,
138		.type = INTF_DSI,
139		.controller_id = MSM_DSI_CONTROLLER_0,
140		.prog_fetch_lines_worst_case = 24,
141		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
142		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
143		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
144	},
145};
146
147static const struct dpu_wb_cfg sc7180_wb[] = {
148	{
149		.name = "wb_2", .id = WB_2,
150		.base = 0x65000, .len = 0x2c8,
151		.features = WB_SDM845_MASK,
152		.format_list = wb2_formats_rgb_yuv,
153		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
154		.clk_ctrl = DPU_CLK_CTRL_WB2,
155		.xin_id = 6,
156		.vbif_idx = VBIF_RT,
157		.maxlinewidth = 4096,
158		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
159	},
160};
161
162static const struct dpu_perf_cfg sc7180_perf_data = {
163	.max_bw_low = 6800000,
164	.max_bw_high = 6800000,
165	.min_core_ib = 2400000,
166	.min_llcc_ib = 800000,
167	.min_dram_ib = 1600000,
168	.min_prefill_lines = 24,
169	.danger_lut_tbl = {0xff, 0xffff, 0x0},
170	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
171	.qos_lut_tbl = {
172		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
173		.entries = sc7180_qos_linear
174		},
175		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
176		.entries = sc7180_qos_macrotile
177		},
178		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
179		.entries = sc7180_qos_nrt
180		},
181	},
182	.cdp_cfg = {
183		{.rd_enable = 1, .wr_enable = 1},
184		{.rd_enable = 1, .wr_enable = 0}
185	},
186	.clk_inefficiency_factor = 105,
187	.bw_inefficiency_factor = 120,
188};
189
190static const struct dpu_mdss_version sc7180_mdss_ver = {
191	.core_major_ver = 6,
192	.core_minor_ver = 2,
193};
194
195const struct dpu_mdss_cfg dpu_sc7180_cfg = {
196	.mdss_ver = &sc7180_mdss_ver,
197	.caps = &sc7180_dpu_caps,
198	.mdp = &sc7180_mdp,
199	.cdm = &dpu_cdm_5_x,
200	.ctl_count = ARRAY_SIZE(sc7180_ctl),
201	.ctl = sc7180_ctl,
202	.sspp_count = ARRAY_SIZE(sc7180_sspp),
203	.sspp = sc7180_sspp,
204	.mixer_count = ARRAY_SIZE(sc7180_lm),
205	.mixer = sc7180_lm,
206	.dspp_count = ARRAY_SIZE(sc7180_dspp),
207	.dspp = sc7180_dspp,
208	.pingpong_count = ARRAY_SIZE(sc7180_pp),
209	.pingpong = sc7180_pp,
210	.intf_count = ARRAY_SIZE(sc7180_intf),
211	.intf = sc7180_intf,
212	.wb_count = ARRAY_SIZE(sc7180_wb),
213	.wb = sc7180_wb,
214	.vbif_count = ARRAY_SIZE(sdm845_vbif),
215	.vbif = sdm845_vbif,
216	.perf = &sc7180_perf_data,
217};
218
219#endif