dpu_6_0_sm8250.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_6_0_SM8250_H
  8#define _DPU_6_0_SM8250_H
  9
 10static const struct dpu_caps sm8250_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0xb,
 13	.has_src_split = true,
 14	.has_dim_layer = true,
 15	.has_idle_pc = true,
 16	.has_3d_merge = true,
 17	.max_linewidth = 4096,
 18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 19};
 20
 21static const struct dpu_mdp_cfg sm8250_mdp = {
 22	.name = "top_0",
 23	.base = 0x0, .len = 0x494,
 24	.clk_ctrls = {
 25		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 26		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 27		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
 28		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
 29		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 30		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 31		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
 32		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
 33		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
 34		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
 35	},
 36};
 37
 38static const struct dpu_ctl_cfg sm8250_ctl[] = {
 39	{
 40		.name = "ctl_0", .id = CTL_0,
 41		.base = 0x1000, .len = 0x1e0,
 42		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 43	}, {
 44		.name = "ctl_1", .id = CTL_1,
 45		.base = 0x1200, .len = 0x1e0,
 46		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 47	}, {
 48		.name = "ctl_2", .id = CTL_2,
 49		.base = 0x1400, .len = 0x1e0,
 50		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 51	}, {
 52		.name = "ctl_3", .id = CTL_3,
 53		.base = 0x1600, .len = 0x1e0,
 54		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 55	}, {
 56		.name = "ctl_4", .id = CTL_4,
 57		.base = 0x1800, .len = 0x1e0,
 58		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 59	}, {
 60		.name = "ctl_5", .id = CTL_5,
 61		.base = 0x1a00, .len = 0x1e0,
 62		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 63	},
 64};
 65
 66static const struct dpu_sspp_cfg sm8250_sspp[] = {
 67	{
 68		.name = "sspp_0", .id = SSPP_VIG0,
 69		.base = 0x4000, .len = 0x1f8,
 70		.features = VIG_SDM845_MASK_SDMA,
 71		.sblk = &dpu_vig_sblk_qseed3_3_0,
 72		.xin_id = 0,
 73		.type = SSPP_TYPE_VIG,
 74		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 75	}, {
 76		.name = "sspp_1", .id = SSPP_VIG1,
 77		.base = 0x6000, .len = 0x1f8,
 78		.features = VIG_SDM845_MASK_SDMA,
 79		.sblk = &dpu_vig_sblk_qseed3_3_0,
 80		.xin_id = 4,
 81		.type = SSPP_TYPE_VIG,
 82		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 83	}, {
 84		.name = "sspp_2", .id = SSPP_VIG2,
 85		.base = 0x8000, .len = 0x1f8,
 86		.features = VIG_SDM845_MASK_SDMA,
 87		.sblk = &dpu_vig_sblk_qseed3_3_0,
 88		.xin_id = 8,
 89		.type = SSPP_TYPE_VIG,
 90		.clk_ctrl = DPU_CLK_CTRL_VIG2,
 91	}, {
 92		.name = "sspp_3", .id = SSPP_VIG3,
 93		.base = 0xa000, .len = 0x1f8,
 94		.features = VIG_SDM845_MASK_SDMA,
 95		.sblk = &dpu_vig_sblk_qseed3_3_0,
 96		.xin_id = 12,
 97		.type = SSPP_TYPE_VIG,
 98		.clk_ctrl = DPU_CLK_CTRL_VIG3,
 99	}, {
100		.name = "sspp_8", .id = SSPP_DMA0,
101		.base = 0x24000, .len = 0x1f8,
102		.features = DMA_SDM845_MASK_SDMA,
103		.sblk = &dpu_dma_sblk,
104		.xin_id = 1,
105		.type = SSPP_TYPE_DMA,
106		.clk_ctrl = DPU_CLK_CTRL_DMA0,
107	}, {
108		.name = "sspp_9", .id = SSPP_DMA1,
109		.base = 0x26000, .len = 0x1f8,
110		.features = DMA_SDM845_MASK_SDMA,
111		.sblk = &dpu_dma_sblk,
112		.xin_id = 5,
113		.type = SSPP_TYPE_DMA,
114		.clk_ctrl = DPU_CLK_CTRL_DMA1,
115	}, {
116		.name = "sspp_10", .id = SSPP_DMA2,
117		.base = 0x28000, .len = 0x1f8,
118		.features = DMA_CURSOR_SDM845_MASK_SDMA,
119		.sblk = &dpu_dma_sblk,
120		.xin_id = 9,
121		.type = SSPP_TYPE_DMA,
122		.clk_ctrl = DPU_CLK_CTRL_DMA2,
123	}, {
124		.name = "sspp_11", .id = SSPP_DMA3,
125		.base = 0x2a000, .len = 0x1f8,
126		.features = DMA_CURSOR_SDM845_MASK_SDMA,
127		.sblk = &dpu_dma_sblk,
128		.xin_id = 13,
129		.type = SSPP_TYPE_DMA,
130		.clk_ctrl = DPU_CLK_CTRL_DMA3,
131	},
132};
133
134static const struct dpu_lm_cfg sm8250_lm[] = {
135	{
136		.name = "lm_0", .id = LM_0,
137		.base = 0x44000, .len = 0x320,
138		.features = MIXER_MSM8998_MASK,
139		.sblk = &sdm845_lm_sblk,
140		.lm_pair = LM_1,
141		.pingpong = PINGPONG_0,
142		.dspp = DSPP_0,
143	}, {
144		.name = "lm_1", .id = LM_1,
145		.base = 0x45000, .len = 0x320,
146		.features = MIXER_MSM8998_MASK,
147		.sblk = &sdm845_lm_sblk,
148		.lm_pair = LM_0,
149		.pingpong = PINGPONG_1,
150		.dspp = DSPP_1,
151	}, {
152		.name = "lm_2", .id = LM_2,
153		.base = 0x46000, .len = 0x320,
154		.features = MIXER_MSM8998_MASK,
155		.sblk = &sdm845_lm_sblk,
156		.lm_pair = LM_3,
157		.pingpong = PINGPONG_2,
158		.dspp = DSPP_2,
159	}, {
160		.name = "lm_3", .id = LM_3,
161		.base = 0x47000, .len = 0x320,
162		.features = MIXER_MSM8998_MASK,
163		.sblk = &sdm845_lm_sblk,
164		.lm_pair = LM_2,
165		.pingpong = PINGPONG_3,
166		.dspp = DSPP_3,
167	}, {
168		.name = "lm_4", .id = LM_4,
169		.base = 0x48000, .len = 0x320,
170		.features = MIXER_MSM8998_MASK,
171		.sblk = &sdm845_lm_sblk,
172		.lm_pair = LM_5,
173		.pingpong = PINGPONG_4,
174	}, {
175		.name = "lm_5", .id = LM_5,
176		.base = 0x49000, .len = 0x320,
177		.features = MIXER_MSM8998_MASK,
178		.sblk = &sdm845_lm_sblk,
179		.lm_pair = LM_4,
180		.pingpong = PINGPONG_5,
181	},
182};
183
184static const struct dpu_dspp_cfg sm8250_dspp[] = {
185	{
186		.name = "dspp_0", .id = DSPP_0,
187		.base = 0x54000, .len = 0x1800,
188		.sblk = &sdm845_dspp_sblk,
189	}, {
190		.name = "dspp_1", .id = DSPP_1,
191		.base = 0x56000, .len = 0x1800,
192		.sblk = &sdm845_dspp_sblk,
193	}, {
194		.name = "dspp_2", .id = DSPP_2,
195		.base = 0x58000, .len = 0x1800,
196		.sblk = &sdm845_dspp_sblk,
197	}, {
198		.name = "dspp_3", .id = DSPP_3,
199		.base = 0x5a000, .len = 0x1800,
200		.sblk = &sdm845_dspp_sblk,
201	},
202};
203
204static const struct dpu_pingpong_cfg sm8250_pp[] = {
205	{
206		.name = "pingpong_0", .id = PINGPONG_0,
207		.base = 0x70000, .len = 0xd4,
208		.sblk = &sdm845_pp_sblk,
209		.merge_3d = MERGE_3D_0,
210		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
211	}, {
212		.name = "pingpong_1", .id = PINGPONG_1,
213		.base = 0x70800, .len = 0xd4,
214		.sblk = &sdm845_pp_sblk,
215		.merge_3d = MERGE_3D_0,
216		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
217	}, {
218		.name = "pingpong_2", .id = PINGPONG_2,
219		.base = 0x71000, .len = 0xd4,
220		.sblk = &sdm845_pp_sblk,
221		.merge_3d = MERGE_3D_1,
222		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
223	}, {
224		.name = "pingpong_3", .id = PINGPONG_3,
225		.base = 0x71800, .len = 0xd4,
226		.sblk = &sdm845_pp_sblk,
227		.merge_3d = MERGE_3D_1,
228		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
229	}, {
230		.name = "pingpong_4", .id = PINGPONG_4,
231		.base = 0x72000, .len = 0xd4,
232		.sblk = &sdm845_pp_sblk,
233		.merge_3d = MERGE_3D_2,
234		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
235	}, {
236		.name = "pingpong_5", .id = PINGPONG_5,
237		.base = 0x72800, .len = 0xd4,
238		.sblk = &sdm845_pp_sblk,
239		.merge_3d = MERGE_3D_2,
240		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
241	},
242};
243
244static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = {
245	{
246		.name = "merge_3d_0", .id = MERGE_3D_0,
247		.base = 0x83000, .len = 0x8,
248	}, {
249		.name = "merge_3d_1", .id = MERGE_3D_1,
250		.base = 0x83100, .len = 0x8,
251	}, {
252		.name = "merge_3d_2", .id = MERGE_3D_2,
253		.base = 0x83200, .len = 0x8,
254	},
255};
256
257static const struct dpu_dsc_cfg sm8250_dsc[] = {
258	{
259		.name = "dsc_0", .id = DSC_0,
260		.base = 0x80000, .len = 0x140,
261	}, {
262		.name = "dsc_1", .id = DSC_1,
263		.base = 0x80400, .len = 0x140,
264	}, {
265		.name = "dsc_2", .id = DSC_2,
266		.base = 0x80800, .len = 0x140,
267	}, {
268		.name = "dsc_3", .id = DSC_3,
269		.base = 0x80c00, .len = 0x140,
270	},
271};
272
273static const struct dpu_intf_cfg sm8250_intf[] = {
274	{
275		.name = "intf_0", .id = INTF_0,
276		.base = 0x6a000, .len = 0x280,
277		.type = INTF_DP,
278		.controller_id = MSM_DP_CONTROLLER_0,
279		.prog_fetch_lines_worst_case = 24,
280		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
281		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
282	}, {
283		.name = "intf_1", .id = INTF_1,
284		.base = 0x6a800, .len = 0x2c0,
285		.type = INTF_DSI,
286		.controller_id = MSM_DSI_CONTROLLER_0,
287		.prog_fetch_lines_worst_case = 24,
288		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
289		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
290		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
291	}, {
292		.name = "intf_2", .id = INTF_2,
293		.base = 0x6b000, .len = 0x2c0,
294		.type = INTF_DSI,
295		.controller_id = MSM_DSI_CONTROLLER_1,
296		.prog_fetch_lines_worst_case = 24,
297		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
298		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
299		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
300	}, {
301		.name = "intf_3", .id = INTF_3,
302		.base = 0x6b800, .len = 0x280,
303		.type = INTF_DP,
304		.controller_id = MSM_DP_CONTROLLER_1,
305		.prog_fetch_lines_worst_case = 24,
306		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
307		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
308	},
309};
310
311static const struct dpu_wb_cfg sm8250_wb[] = {
312	{
313		.name = "wb_2", .id = WB_2,
314		.base = 0x65000, .len = 0x2c8,
315		.features = WB_SDM845_MASK,
316		.format_list = wb2_formats_rgb_yuv,
317		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
318		.clk_ctrl = DPU_CLK_CTRL_WB2,
319		.xin_id = 6,
320		.vbif_idx = VBIF_RT,
321		.maxlinewidth = 4096,
322		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
323	},
324};
325
326static const struct dpu_perf_cfg sm8250_perf_data = {
327	.max_bw_low = 13700000,
328	.max_bw_high = 16600000,
329	.min_core_ib = 4800000,
330	.min_llcc_ib = 0,
331	.min_dram_ib = 800000,
332	.min_prefill_lines = 35,
333	.danger_lut_tbl = {0xf, 0xffff, 0x0},
334	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
335	.qos_lut_tbl = {
336		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
337		.entries = sc7180_qos_linear
338		},
339		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
340		.entries = sc7180_qos_macrotile
341		},
342		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
343		.entries = sc7180_qos_nrt
344		},
345		/* TODO: macrotile-qseed is different from macrotile */
346	},
347	.cdp_cfg = {
348		{.rd_enable = 1, .wr_enable = 1},
349		{.rd_enable = 1, .wr_enable = 0}
350	},
351	.clk_inefficiency_factor = 105,
352	.bw_inefficiency_factor = 120,
353};
354
355static const struct dpu_mdss_version sm8250_mdss_ver = {
356	.core_major_ver = 6,
357	.core_minor_ver = 0,
358};
359
360const struct dpu_mdss_cfg dpu_sm8250_cfg = {
361	.mdss_ver = &sm8250_mdss_ver,
362	.caps = &sm8250_dpu_caps,
363	.mdp = &sm8250_mdp,
364	.cdm = &dpu_cdm_5_x,
365	.ctl_count = ARRAY_SIZE(sm8250_ctl),
366	.ctl = sm8250_ctl,
367	.sspp_count = ARRAY_SIZE(sm8250_sspp),
368	.sspp = sm8250_sspp,
369	.mixer_count = ARRAY_SIZE(sm8250_lm),
370	.mixer = sm8250_lm,
371	.dspp_count = ARRAY_SIZE(sm8250_dspp),
372	.dspp = sm8250_dspp,
373	.dsc_count = ARRAY_SIZE(sm8250_dsc),
374	.dsc = sm8250_dsc,
375	.pingpong_count = ARRAY_SIZE(sm8250_pp),
376	.pingpong = sm8250_pp,
377	.merge_3d_count = ARRAY_SIZE(sm8250_merge_3d),
378	.merge_3d = sm8250_merge_3d,
379	.intf_count = ARRAY_SIZE(sm8250_intf),
380	.intf = sm8250_intf,
381	.vbif_count = ARRAY_SIZE(sdm845_vbif),
382	.vbif = sdm845_vbif,
383	.wb_count = ARRAY_SIZE(sm8250_wb),
384	.wb = sm8250_wb,
385	.perf = &sm8250_perf_data,
386};
387
388#endif