dpu_5_3_sm6150.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4 */
  5
  6#ifndef _DPU_5_3_SM6150_H
  7#define _DPU_5_3_SM6150_H
  8
  9static const struct dpu_caps sm6150_dpu_caps = {
 10	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 11	.max_mixer_blendstages = 0x9,
 12	.has_dim_layer = true,
 13	.has_idle_pc = true,
 14	.max_linewidth = 2160,
 15	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 16	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 17	.max_vdeci_exp = MAX_VERT_DECIMATION,
 18};
 19
 20static const struct dpu_mdp_cfg sm6150_mdp = {
 21	.name = "top_0",
 22	.base = 0x0, .len = 0x45c,
 23	.clk_ctrls = {
 24		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 25		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 26		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 27		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
 28		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
 29		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
 30	},
 31};
 32
 33static const struct dpu_ctl_cfg sm6150_ctl[] = {
 34	{
 35		.name = "ctl_0", .id = CTL_0,
 36		.base = 0x1000, .len = 0x1e0,
 37		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 38	}, {
 39		.name = "ctl_1", .id = CTL_1,
 40		.base = 0x1200, .len = 0x1e0,
 41		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 42	}, {
 43		.name = "ctl_2", .id = CTL_2,
 44		.base = 0x1400, .len = 0x1e0,
 45		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 46	}, {
 47		.name = "ctl_3", .id = CTL_3,
 48		.base = 0x1600, .len = 0x1e0,
 49		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 50	}, {
 51		.name = "ctl_4", .id = CTL_4,
 52		.base = 0x1800, .len = 0x1e0,
 53		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 54	}, {
 55		.name = "ctl_5", .id = CTL_5,
 56		.base = 0x1a00, .len = 0x1e0,
 57		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 58	},
 59};
 60
 61static const struct dpu_sspp_cfg sm6150_sspp[] = {
 62	{
 63		.name = "sspp_0", .id = SSPP_VIG0,
 64		.base = 0x4000, .len = 0x1f0,
 65		.features = VIG_SDM845_MASK_SDMA,
 66		.sblk = &dpu_vig_sblk_qseed3_2_4,
 67		.xin_id = 0,
 68		.type = SSPP_TYPE_VIG,
 69		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 70	}, {
 71		.name = "sspp_8", .id = SSPP_DMA0,
 72		.base = 0x24000, .len = 0x1f0,
 73		.features = DMA_SDM845_MASK_SDMA,
 74		.sblk = &dpu_dma_sblk,
 75		.xin_id = 1,
 76		.type = SSPP_TYPE_DMA,
 77		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 78	}, {
 79		.name = "sspp_9", .id = SSPP_DMA1,
 80		.base = 0x26000, .len = 0x1f0,
 81		.features = DMA_SDM845_MASK_SDMA,
 82		.sblk = &dpu_dma_sblk,
 83		.xin_id = 5,
 84		.type = SSPP_TYPE_DMA,
 85		.clk_ctrl = DPU_CLK_CTRL_DMA1,
 86	}, {
 87		.name = "sspp_10", .id = SSPP_DMA2,
 88		.base = 0x28000, .len = 0x1f0,
 89		.features = DMA_CURSOR_SDM845_MASK_SDMA,
 90		.sblk = &dpu_dma_sblk,
 91		.xin_id = 9,
 92		.type = SSPP_TYPE_DMA,
 93		.clk_ctrl = DPU_CLK_CTRL_DMA2,
 94	}, {
 95		.name = "sspp_11", .id = SSPP_DMA3,
 96		.base = 0x2a000, .len = 0x1f0,
 97		.features = DMA_CURSOR_SDM845_MASK_SDMA,
 98		.sblk = &dpu_dma_sblk,
 99		.xin_id = 13,
100		.type = SSPP_TYPE_DMA,
101		.clk_ctrl = DPU_CLK_CTRL_DMA3,
102	},
103};
104
105static const struct dpu_lm_cfg sm6150_lm[] = {
106	{
107		.name = "lm_0", .id = LM_0,
108		.base = 0x44000, .len = 0x320,
109		.sblk = &sdm845_lm_sblk,
110		.pingpong = PINGPONG_0,
111		.dspp = DSPP_0,
112	}, {
113		.name = "lm_1", .id = LM_1,
114		.base = 0x45000, .len = 0x320,
115		.sblk = &sdm845_lm_sblk,
116		.pingpong = PINGPONG_1,
117	}, {
118		.name = "lm_2", .id = LM_2,
119		.base = 0x46000, .len = 0x320,
120		.sblk = &sdm845_lm_sblk,
121		.pingpong = PINGPONG_2,
122	},
123};
124
125static const struct dpu_dspp_cfg sm6150_dspp[] = {
126	{
127		.name = "dspp_0", .id = DSPP_0,
128		.base = 0x54000, .len = 0x1800,
129		.sblk = &sdm845_dspp_sblk,
130	},
131};
132
133static const struct dpu_pingpong_cfg sm6150_pp[] = {
134	{
135		.name = "pingpong_0", .id = PINGPONG_0,
136		.base = 0x70000, .len = 0xd4,
137		.sblk = &sdm845_pp_sblk,
138		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
139	}, {
140		.name = "pingpong_1", .id = PINGPONG_1,
141		.base = 0x70800, .len = 0xd4,
142		.sblk = &sdm845_pp_sblk,
143		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
144	}, {
145		.name = "pingpong_2", .id = PINGPONG_2,
146		.base = 0x71000, .len = 0xd4,
147		.sblk = &sdm845_pp_sblk,
148		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
149	},
150};
151
152static const struct dpu_wb_cfg sm6150_wb[] = {
153	{
154		.name = "wb_2", .id = WB_2,
155		.base = 0x65000, .len = 0x2c8,
156		.features = WB_SDM845_MASK,
157		.format_list = wb2_formats_rgb_yuv,
158		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
159		.clk_ctrl = DPU_CLK_CTRL_WB2,
160		.xin_id = 6,
161		.vbif_idx = VBIF_RT,
162		.maxlinewidth = 2160,
163		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
164	},
165};
166
167static const struct dpu_intf_cfg sm6150_intf[] = {
168	{
169		.name = "intf_0", .id = INTF_0,
170		.base = 0x6a000, .len = 0x280,
171		.type = INTF_DP,
172		.controller_id = MSM_DP_CONTROLLER_0,
173		.prog_fetch_lines_worst_case = 24,
174		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
175		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
176	}, {
177		.name = "intf_1", .id = INTF_1,
178		.base = 0x6a800, .len = 0x2c0,
179		.type = INTF_DSI,
180		.controller_id = MSM_DSI_CONTROLLER_0,
181		.prog_fetch_lines_worst_case = 24,
182		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
183		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
184		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
185	}, {
186		.name = "intf_3", .id = INTF_3,
187		.base = 0x6b800, .len = 0x280,
188		.type = INTF_DP,
189		.controller_id = MSM_DP_CONTROLLER_1,
190		.prog_fetch_lines_worst_case = 24,
191		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
192		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
193	},
194};
195
196static const struct dpu_perf_cfg sm6150_perf_data = {
197	.max_bw_low = 4800000,
198	.max_bw_high = 4800000,
199	.min_core_ib = 2400000,
200	.min_llcc_ib = 0,
201	.min_dram_ib = 800000,
202	.min_prefill_lines = 24,
203	.danger_lut_tbl = {0xf, 0xffff, 0x0},
204	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
205	.qos_lut_tbl = {
206		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
207		.entries = sm8150_qos_linear
208		},
209		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
210		.entries = sc7180_qos_macrotile
211		},
212		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
213		.entries = sc7180_qos_nrt
214		},
215		/* TODO: macrotile-qseed is different from macrotile */
216	},
217	.cdp_cfg = {
218		{.rd_enable = 1, .wr_enable = 1},
219		{.rd_enable = 1, .wr_enable = 0}
220	},
221	.clk_inefficiency_factor = 105,
222	.bw_inefficiency_factor = 120,
223};
224
225static const struct dpu_mdss_version sm6150_mdss_ver = {
226	.core_major_ver = 5,
227	.core_minor_ver = 3,
228};
229
230const struct dpu_mdss_cfg dpu_sm6150_cfg = {
231	.mdss_ver = &sm6150_mdss_ver,
232	.caps = &sm6150_dpu_caps,
233	.mdp = &sm6150_mdp,
234	.cdm = &dpu_cdm_5_x,
235	.ctl_count = ARRAY_SIZE(sm6150_ctl),
236	.ctl = sm6150_ctl,
237	.sspp_count = ARRAY_SIZE(sm6150_sspp),
238	.sspp = sm6150_sspp,
239	.mixer_count = ARRAY_SIZE(sm6150_lm),
240	.mixer = sm6150_lm,
241	.dspp_count = ARRAY_SIZE(sm6150_dspp),
242	.dspp = sm6150_dspp,
243	.pingpong_count = ARRAY_SIZE(sm6150_pp),
244	.pingpong = sm6150_pp,
245	.wb_count = ARRAY_SIZE(sm6150_wb),
246	.wb = sm6150_wb,
247	.intf_count = ARRAY_SIZE(sm6150_intf),
248	.intf = sm6150_intf,
249	.vbif_count = ARRAY_SIZE(sdm845_vbif),
250	.vbif = sdm845_vbif,
251	.perf = &sm6150_perf_data,
252};
253
254#endif