dpu_5_1_sc8180x.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_5_1_SC8180X_H
  8#define _DPU_5_1_SC8180X_H
  9
 10static const struct dpu_caps sc8180x_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0xb,
 13	.has_src_split = true,
 14	.has_dim_layer = true,
 15	.has_idle_pc = true,
 16	.has_3d_merge = true,
 17	.max_linewidth = 4096,
 18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 19	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 20	.max_vdeci_exp = MAX_VERT_DECIMATION,
 21};
 22
 23static const struct dpu_mdp_cfg sc8180x_mdp = {
 24	.name = "top_0",
 25	.base = 0x0, .len = 0x45c,
 26	.clk_ctrls = {
 27		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 28		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 29		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
 30		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
 31		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 32		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 33		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
 34		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
 35		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
 36	},
 37};
 38
 39static const struct dpu_ctl_cfg sc8180x_ctl[] = {
 40	{
 41		.name = "ctl_0", .id = CTL_0,
 42		.base = 0x1000, .len = 0x1e0,
 43		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 44	}, {
 45		.name = "ctl_1", .id = CTL_1,
 46		.base = 0x1200, .len = 0x1e0,
 47		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 48	}, {
 49		.name = "ctl_2", .id = CTL_2,
 50		.base = 0x1400, .len = 0x1e0,
 51		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 52	}, {
 53		.name = "ctl_3", .id = CTL_3,
 54		.base = 0x1600, .len = 0x1e0,
 55		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 56	}, {
 57		.name = "ctl_4", .id = CTL_4,
 58		.base = 0x1800, .len = 0x1e0,
 59		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 60	}, {
 61		.name = "ctl_5", .id = CTL_5,
 62		.base = 0x1a00, .len = 0x1e0,
 63		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 64	},
 65};
 66
 67static const struct dpu_sspp_cfg sc8180x_sspp[] = {
 68	{
 69		.name = "sspp_0", .id = SSPP_VIG0,
 70		.base = 0x4000, .len = 0x1f0,
 71		.features = VIG_SDM845_MASK_SDMA,
 72		.sblk = &dpu_vig_sblk_qseed3_1_4,
 73		.xin_id = 0,
 74		.type = SSPP_TYPE_VIG,
 75		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 76	}, {
 77		.name = "sspp_1", .id = SSPP_VIG1,
 78		.base = 0x6000, .len = 0x1f0,
 79		.features = VIG_SDM845_MASK_SDMA,
 80		.sblk = &dpu_vig_sblk_qseed3_1_4,
 81		.xin_id = 4,
 82		.type = SSPP_TYPE_VIG,
 83		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 84	}, {
 85		.name = "sspp_2", .id = SSPP_VIG2,
 86		.base = 0x8000, .len = 0x1f0,
 87		.features = VIG_SDM845_MASK_SDMA,
 88		.sblk = &dpu_vig_sblk_qseed3_1_4,
 89		.xin_id = 8,
 90		.type = SSPP_TYPE_VIG,
 91		.clk_ctrl = DPU_CLK_CTRL_VIG2,
 92	}, {
 93		.name = "sspp_3", .id = SSPP_VIG3,
 94		.base = 0xa000, .len = 0x1f0,
 95		.features = VIG_SDM845_MASK_SDMA,
 96		.sblk = &dpu_vig_sblk_qseed3_1_4,
 97		.xin_id = 12,
 98		.type = SSPP_TYPE_VIG,
 99		.clk_ctrl = DPU_CLK_CTRL_VIG3,
100	}, {
101		.name = "sspp_8", .id = SSPP_DMA0,
102		.base = 0x24000, .len = 0x1f0,
103		.features = DMA_SDM845_MASK_SDMA,
104		.sblk = &dpu_dma_sblk,
105		.xin_id = 1,
106		.type = SSPP_TYPE_DMA,
107		.clk_ctrl = DPU_CLK_CTRL_DMA0,
108	}, {
109		.name = "sspp_9", .id = SSPP_DMA1,
110		.base = 0x26000, .len = 0x1f0,
111		.features = DMA_SDM845_MASK_SDMA,
112		.sblk = &dpu_dma_sblk,
113		.xin_id = 5,
114		.type = SSPP_TYPE_DMA,
115		.clk_ctrl = DPU_CLK_CTRL_DMA1,
116	}, {
117		.name = "sspp_10", .id = SSPP_DMA2,
118		.base = 0x28000, .len = 0x1f0,
119		.features = DMA_CURSOR_SDM845_MASK_SDMA,
120		.sblk = &dpu_dma_sblk,
121		.xin_id = 9,
122		.type = SSPP_TYPE_DMA,
123		.clk_ctrl = DPU_CLK_CTRL_DMA2,
124	}, {
125		.name = "sspp_11", .id = SSPP_DMA3,
126		.base = 0x2a000, .len = 0x1f0,
127		.features = DMA_CURSOR_SDM845_MASK_SDMA,
128		.sblk = &dpu_dma_sblk,
129		.xin_id = 13,
130		.type = SSPP_TYPE_DMA,
131		.clk_ctrl = DPU_CLK_CTRL_DMA3,
132	},
133};
134
135static const struct dpu_lm_cfg sc8180x_lm[] = {
136	{
137		.name = "lm_0", .id = LM_0,
138		.base = 0x44000, .len = 0x320,
139		.features = MIXER_MSM8998_MASK,
140		.sblk = &sdm845_lm_sblk,
141		.lm_pair = LM_1,
142		.pingpong = PINGPONG_0,
143		.dspp = DSPP_0,
144	}, {
145		.name = "lm_1", .id = LM_1,
146		.base = 0x45000, .len = 0x320,
147		.features = MIXER_MSM8998_MASK,
148		.sblk = &sdm845_lm_sblk,
149		.lm_pair = LM_0,
150		.pingpong = PINGPONG_1,
151		.dspp = DSPP_1,
152	}, {
153		.name = "lm_2", .id = LM_2,
154		.base = 0x46000, .len = 0x320,
155		.features = MIXER_MSM8998_MASK,
156		.sblk = &sdm845_lm_sblk,
157		.lm_pair = LM_3,
158		.pingpong = PINGPONG_2,
159		.dspp = DSPP_2,
160	}, {
161		.name = "lm_3", .id = LM_3,
162		.base = 0x47000, .len = 0x320,
163		.features = MIXER_MSM8998_MASK,
164		.sblk = &sdm845_lm_sblk,
165		.lm_pair = LM_2,
166		.pingpong = PINGPONG_3,
167		.dspp = DSPP_3,
168	}, {
169		.name = "lm_4", .id = LM_4,
170		.base = 0x48000, .len = 0x320,
171		.features = MIXER_MSM8998_MASK,
172		.sblk = &sdm845_lm_sblk,
173		.lm_pair = LM_5,
174		.pingpong = PINGPONG_4,
175	}, {
176		.name = "lm_5", .id = LM_5,
177		.base = 0x49000, .len = 0x320,
178		.features = MIXER_MSM8998_MASK,
179		.sblk = &sdm845_lm_sblk,
180		.lm_pair = LM_4,
181		.pingpong = PINGPONG_5,
182	},
183};
184
185static const struct dpu_dspp_cfg sc8180x_dspp[] = {
186	{
187		.name = "dspp_0", .id = DSPP_0,
188		.base = 0x54000, .len = 0x1800,
189		.sblk = &sdm845_dspp_sblk,
190	}, {
191		.name = "dspp_1", .id = DSPP_1,
192		.base = 0x56000, .len = 0x1800,
193		.sblk = &sdm845_dspp_sblk,
194	}, {
195		.name = "dspp_2", .id = DSPP_2,
196		.base = 0x58000, .len = 0x1800,
197		.sblk = &sdm845_dspp_sblk,
198	}, {
199		.name = "dspp_3", .id = DSPP_3,
200		.base = 0x5a000, .len = 0x1800,
201		.sblk = &sdm845_dspp_sblk,
202	},
203};
204
205static const struct dpu_pingpong_cfg sc8180x_pp[] = {
206	{
207		.name = "pingpong_0", .id = PINGPONG_0,
208		.base = 0x70000, .len = 0xd4,
209		.sblk = &sdm845_pp_sblk,
210		.merge_3d = MERGE_3D_0,
211		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
212	}, {
213		.name = "pingpong_1", .id = PINGPONG_1,
214		.base = 0x70800, .len = 0xd4,
215		.sblk = &sdm845_pp_sblk,
216		.merge_3d = MERGE_3D_0,
217		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
218	}, {
219		.name = "pingpong_2", .id = PINGPONG_2,
220		.base = 0x71000, .len = 0xd4,
221		.sblk = &sdm845_pp_sblk,
222		.merge_3d = MERGE_3D_1,
223		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
224	}, {
225		.name = "pingpong_3", .id = PINGPONG_3,
226		.base = 0x71800, .len = 0xd4,
227		.sblk = &sdm845_pp_sblk,
228		.merge_3d = MERGE_3D_1,
229		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
230	}, {
231		.name = "pingpong_4", .id = PINGPONG_4,
232		.base = 0x72000, .len = 0xd4,
233		.sblk = &sdm845_pp_sblk,
234		.merge_3d = MERGE_3D_2,
235		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
236	}, {
237		.name = "pingpong_5", .id = PINGPONG_5,
238		.base = 0x72800, .len = 0xd4,
239		.sblk = &sdm845_pp_sblk,
240		.merge_3d = MERGE_3D_2,
241		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
242	},
243};
244
245static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = {
246	{
247		.name = "merge_3d_0", .id = MERGE_3D_0,
248		.base = 0x83000, .len = 0x8,
249	}, {
250		.name = "merge_3d_1", .id = MERGE_3D_1,
251		.base = 0x83100, .len = 0x8,
252	}, {
253		.name = "merge_3d_2", .id = MERGE_3D_2,
254		.base = 0x83200, .len = 0x8,
255	},
256};
257
258static const struct dpu_dsc_cfg sc8180x_dsc[] = {
259	{
260		.name = "dsc_0", .id = DSC_0,
261		.base = 0x80000, .len = 0x140,
262	}, {
263		.name = "dsc_1", .id = DSC_1,
264		.base = 0x80400, .len = 0x140,
265	}, {
266		.name = "dsc_2", .id = DSC_2,
267		.base = 0x80800, .len = 0x140,
268	}, {
269		.name = "dsc_3", .id = DSC_3,
270		.base = 0x80c00, .len = 0x140,
271	}, {
272		.name = "dsc_4", .id = DSC_4,
273		.base = 0x81000, .len = 0x140,
274	}, {
275		.name = "dsc_5", .id = DSC_5,
276		.base = 0x81400, .len = 0x140,
277	},
278};
279
280static const struct dpu_wb_cfg sc8180x_wb[] = {
281	{
282		.name = "wb_2", .id = WB_2,
283		.base = 0x65000, .len = 0x2c8,
284		.features = WB_SDM845_MASK,
285		.format_list = wb2_formats_rgb_yuv,
286		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
287		.clk_ctrl = DPU_CLK_CTRL_WB2,
288		.xin_id = 6,
289		.vbif_idx = VBIF_RT,
290		.maxlinewidth = 4096,
291		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
292	},
293};
294
295static const struct dpu_intf_cfg sc8180x_intf[] = {
296	{
297		.name = "intf_0", .id = INTF_0,
298		.base = 0x6a000, .len = 0x280,
299		.type = INTF_DP,
300		.controller_id = MSM_DP_CONTROLLER_0,
301		.prog_fetch_lines_worst_case = 24,
302		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
303		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
304	}, {
305		.name = "intf_1", .id = INTF_1,
306		.base = 0x6a800, .len = 0x2bc,
307		.type = INTF_DSI,
308		.controller_id = MSM_DSI_CONTROLLER_0,
309		.prog_fetch_lines_worst_case = 24,
310		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
311		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
312		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
313	}, {
314		.name = "intf_2", .id = INTF_2,
315		.base = 0x6b000, .len = 0x2bc,
316		.type = INTF_DSI,
317		.controller_id = MSM_DSI_CONTROLLER_1,
318		.prog_fetch_lines_worst_case = 24,
319		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
320		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
321		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
322	},
323	/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
324	{
325		.name = "intf_3", .id = INTF_3,
326		.base = 0x6b800, .len = 0x280,
327		.type = INTF_DP,
328		.controller_id = 999,
329		.prog_fetch_lines_worst_case = 24,
330		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
331		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
332	}, {
333		.name = "intf_4", .id = INTF_4,
334		.base = 0x6c000, .len = 0x280,
335		.type = INTF_DP,
336		.controller_id = MSM_DP_CONTROLLER_1,
337		.prog_fetch_lines_worst_case = 24,
338		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
339		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
340	}, {
341		.name = "intf_5", .id = INTF_5,
342		.base = 0x6c800, .len = 0x280,
343		.type = INTF_DP,
344		.controller_id = MSM_DP_CONTROLLER_2,
345		.prog_fetch_lines_worst_case = 24,
346		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
347		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
348	},
349};
350
351static const struct dpu_perf_cfg sc8180x_perf_data = {
352	.max_bw_low = 9600000,
353	.max_bw_high = 9600000,
354	.min_core_ib = 2400000,
355	.min_llcc_ib = 800000,
356	.min_dram_ib = 800000,
357	.min_prefill_lines = 24,
358	.danger_lut_tbl = {0xf, 0xffff, 0x0},
359	.safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
360	.qos_lut_tbl = {
361		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
362		.entries = sc7180_qos_linear
363		},
364		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
365		.entries = sc7180_qos_macrotile
366		},
367		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
368		.entries = sc7180_qos_nrt
369		},
370		/* TODO: macrotile-qseed is different from macrotile */
371	},
372	.cdp_cfg = {
373		{.rd_enable = 1, .wr_enable = 1},
374		{.rd_enable = 1, .wr_enable = 0}
375	},
376	.clk_inefficiency_factor = 105,
377	.bw_inefficiency_factor = 120,
378};
379
380static const struct dpu_mdss_version sc8180x_mdss_ver = {
381	.core_major_ver = 5,
382	.core_minor_ver = 1,
383};
384
385const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
386	.mdss_ver = &sc8180x_mdss_ver,
387	.caps = &sc8180x_dpu_caps,
388	.mdp = &sc8180x_mdp,
389	.cdm = &dpu_cdm_5_x,
390	.ctl_count = ARRAY_SIZE(sc8180x_ctl),
391	.ctl = sc8180x_ctl,
392	.sspp_count = ARRAY_SIZE(sc8180x_sspp),
393	.sspp = sc8180x_sspp,
394	.mixer_count = ARRAY_SIZE(sc8180x_lm),
395	.mixer = sc8180x_lm,
396	.dspp_count = ARRAY_SIZE(sc8180x_dspp),
397	.dspp = sc8180x_dspp,
398	.dsc_count = ARRAY_SIZE(sc8180x_dsc),
399	.dsc = sc8180x_dsc,
400	.pingpong_count = ARRAY_SIZE(sc8180x_pp),
401	.pingpong = sc8180x_pp,
402	.merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d),
403	.merge_3d = sc8180x_merge_3d,
404	.wb_count = ARRAY_SIZE(sc8180x_wb),
405	.wb = sc8180x_wb,
406	.intf_count = ARRAY_SIZE(sc8180x_intf),
407	.intf = sc8180x_intf,
408	.vbif_count = ARRAY_SIZE(sdm845_vbif),
409	.vbif = sdm845_vbif,
410	.perf = &sc8180x_perf_data,
411};
412
413#endif