dpu_4_0_sdm845.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_4_0_SDM845_H
  8#define _DPU_4_0_SDM845_H
  9
 10static const struct dpu_caps sdm845_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0xb,
 13	.has_src_split = true,
 14	.has_dim_layer = true,
 15	.has_idle_pc = true,
 16	.has_3d_merge = true,
 17	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 19	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 20	.max_vdeci_exp = MAX_VERT_DECIMATION,
 21};
 22
 23static const struct dpu_mdp_cfg sdm845_mdp = {
 24	.name = "top_0",
 25	.base = 0x0, .len = 0x45c,
 26	.clk_ctrls = {
 27		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 28		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 29		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
 30		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
 31		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 32		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 33		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
 34		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
 35	},
 36};
 37
 38static const struct dpu_ctl_cfg sdm845_ctl[] = {
 39	{
 40		.name = "ctl_0", .id = CTL_0,
 41		.base = 0x1000, .len = 0xe4,
 42		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
 43		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 44	}, {
 45		.name = "ctl_1", .id = CTL_1,
 46		.base = 0x1200, .len = 0xe4,
 47		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
 48		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 49	}, {
 50		.name = "ctl_2", .id = CTL_2,
 51		.base = 0x1400, .len = 0xe4,
 52		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 53	}, {
 54		.name = "ctl_3", .id = CTL_3,
 55		.base = 0x1600, .len = 0xe4,
 56		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 57	}, {
 58		.name = "ctl_4", .id = CTL_4,
 59		.base = 0x1800, .len = 0xe4,
 60		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 61	},
 62};
 63
 64static const struct dpu_sspp_cfg sdm845_sspp[] = {
 65	{
 66		.name = "sspp_0", .id = SSPP_VIG0,
 67		.base = 0x4000, .len = 0x1c8,
 68		.features = VIG_SDM845_MASK_SDMA,
 69		.sblk = &dpu_vig_sblk_qseed3_1_3,
 70		.xin_id = 0,
 71		.type = SSPP_TYPE_VIG,
 72		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 73	}, {
 74		.name = "sspp_1", .id = SSPP_VIG1,
 75		.base = 0x6000, .len = 0x1c8,
 76		.features = VIG_SDM845_MASK_SDMA,
 77		.sblk = &dpu_vig_sblk_qseed3_1_3,
 78		.xin_id = 4,
 79		.type = SSPP_TYPE_VIG,
 80		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 81	}, {
 82		.name = "sspp_2", .id = SSPP_VIG2,
 83		.base = 0x8000, .len = 0x1c8,
 84		.features = VIG_SDM845_MASK_SDMA,
 85		.sblk = &dpu_vig_sblk_qseed3_1_3,
 86		.xin_id = 8,
 87		.type = SSPP_TYPE_VIG,
 88		.clk_ctrl = DPU_CLK_CTRL_VIG2,
 89	}, {
 90		.name = "sspp_3", .id = SSPP_VIG3,
 91		.base = 0xa000, .len = 0x1c8,
 92		.features = VIG_SDM845_MASK_SDMA,
 93		.sblk = &dpu_vig_sblk_qseed3_1_3,
 94		.xin_id = 12,
 95		.type = SSPP_TYPE_VIG,
 96		.clk_ctrl = DPU_CLK_CTRL_VIG3,
 97	}, {
 98		.name = "sspp_8", .id = SSPP_DMA0,
 99		.base = 0x24000, .len = 0x1c8,
100		.features = DMA_SDM845_MASK_SDMA,
101		.sblk = &dpu_dma_sblk,
102		.xin_id = 1,
103		.type = SSPP_TYPE_DMA,
104		.clk_ctrl = DPU_CLK_CTRL_DMA0,
105	}, {
106		.name = "sspp_9", .id = SSPP_DMA1,
107		.base = 0x26000, .len = 0x1c8,
108		.features = DMA_SDM845_MASK_SDMA,
109		.sblk = &dpu_dma_sblk,
110		.xin_id = 5,
111		.type = SSPP_TYPE_DMA,
112		.clk_ctrl = DPU_CLK_CTRL_DMA1,
113	}, {
114		.name = "sspp_10", .id = SSPP_DMA2,
115		.base = 0x28000, .len = 0x1c8,
116		.features = DMA_CURSOR_SDM845_MASK_SDMA,
117		.sblk = &dpu_dma_sblk,
118		.xin_id = 9,
119		.type = SSPP_TYPE_DMA,
120		.clk_ctrl = DPU_CLK_CTRL_DMA2,
121	}, {
122		.name = "sspp_11", .id = SSPP_DMA3,
123		.base = 0x2a000, .len = 0x1c8,
124		.features = DMA_CURSOR_SDM845_MASK_SDMA,
125		.sblk = &dpu_dma_sblk,
126		.xin_id = 13,
127		.type = SSPP_TYPE_DMA,
128		.clk_ctrl = DPU_CLK_CTRL_DMA3,
129	},
130};
131
132static const struct dpu_lm_cfg sdm845_lm[] = {
133	{
134		.name = "lm_0", .id = LM_0,
135		.base = 0x44000, .len = 0x320,
136		.features = MIXER_MSM8998_MASK,
137		.sblk = &sdm845_lm_sblk,
138		.lm_pair = LM_1,
139		.pingpong = PINGPONG_0,
140		.dspp = DSPP_0,
141	}, {
142		.name = "lm_1", .id = LM_1,
143		.base = 0x45000, .len = 0x320,
144		.features = MIXER_MSM8998_MASK,
145		.sblk = &sdm845_lm_sblk,
146		.lm_pair = LM_0,
147		.pingpong = PINGPONG_1,
148		.dspp = DSPP_1,
149	}, {
150		.name = "lm_2", .id = LM_2,
151		.base = 0x46000, .len = 0x320,
152		.features = MIXER_MSM8998_MASK,
153		.sblk = &sdm845_lm_sblk,
154		.lm_pair = LM_5,
155		.pingpong = PINGPONG_2,
156		.dspp = DSPP_2,
157	}, {
158		.name = "lm_5", .id = LM_5,
159		.base = 0x49000, .len = 0x320,
160		.features = MIXER_MSM8998_MASK,
161		.sblk = &sdm845_lm_sblk,
162		.lm_pair = LM_2,
163		.pingpong = PINGPONG_3,
164		.dspp = DSPP_3,
165	},
166};
167
168static const struct dpu_dspp_cfg sdm845_dspp[] = {
169	{
170		.name = "dspp_0", .id = DSPP_0,
171		.base = 0x54000, .len = 0x1800,
172		.sblk = &sdm845_dspp_sblk,
173	}, {
174		.name = "dspp_1", .id = DSPP_1,
175		.base = 0x56000, .len = 0x1800,
176		.sblk = &sdm845_dspp_sblk,
177	}, {
178		.name = "dspp_2", .id = DSPP_2,
179		.base = 0x58000, .len = 0x1800,
180		.sblk = &sdm845_dspp_sblk,
181	}, {
182		.name = "dspp_3", .id = DSPP_3,
183		.base = 0x5a000, .len = 0x1800,
184		.sblk = &sdm845_dspp_sblk,
185	},
186};
187
188static const struct dpu_pingpong_cfg sdm845_pp[] = {
189	{
190		.name = "pingpong_0", .id = PINGPONG_0,
191		.base = 0x70000, .len = 0xd4,
192		.sblk = &sdm845_pp_sblk,
193		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
194		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
195	}, {
196		.name = "pingpong_1", .id = PINGPONG_1,
197		.base = 0x70800, .len = 0xd4,
198		.sblk = &sdm845_pp_sblk,
199		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
200		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
201	}, {
202		.name = "pingpong_2", .id = PINGPONG_2,
203		.base = 0x71000, .len = 0xd4,
204		.sblk = &sdm845_pp_sblk,
205		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
206		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
207	}, {
208		.name = "pingpong_3", .id = PINGPONG_3,
209		.base = 0x71800, .len = 0xd4,
210		.sblk = &sdm845_pp_sblk,
211		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
212		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
213	},
214};
215
216static const struct dpu_dsc_cfg sdm845_dsc[] = {
217	{
218		.name = "dsc_0", .id = DSC_0,
219		.base = 0x80000, .len = 0x140,
220	}, {
221		.name = "dsc_1", .id = DSC_1,
222		.base = 0x80400, .len = 0x140,
223	}, {
224		.name = "dsc_2", .id = DSC_2,
225		.base = 0x80800, .len = 0x140,
226	}, {
227		.name = "dsc_3", .id = DSC_3,
228		.base = 0x80c00, .len = 0x140,
229	},
230};
231
232static const struct dpu_intf_cfg sdm845_intf[] = {
233	{
234		.name = "intf_0", .id = INTF_0,
235		.base = 0x6a000, .len = 0x280,
236		.type = INTF_DP,
237		.controller_id = MSM_DP_CONTROLLER_0,
238		.prog_fetch_lines_worst_case = 24,
239		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
240		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
241	}, {
242		.name = "intf_1", .id = INTF_1,
243		.base = 0x6a800, .len = 0x280,
244		.type = INTF_DSI,
245		.controller_id = MSM_DSI_CONTROLLER_0,
246		.prog_fetch_lines_worst_case = 24,
247		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
248		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
249	}, {
250		.name = "intf_2", .id = INTF_2,
251		.base = 0x6b000, .len = 0x280,
252		.type = INTF_DSI,
253		.controller_id = MSM_DSI_CONTROLLER_1,
254		.prog_fetch_lines_worst_case = 24,
255		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
256		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
257	}, {
258		.name = "intf_3", .id = INTF_3,
259		.base = 0x6b800, .len = 0x280,
260		.type = INTF_DP,
261		.controller_id = MSM_DP_CONTROLLER_1,
262		.prog_fetch_lines_worst_case = 24,
263		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
264		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
265	},
266};
267
268static const struct dpu_perf_cfg sdm845_perf_data = {
269	.max_bw_low = 6800000,
270	.max_bw_high = 6800000,
271	.min_core_ib = 2400000,
272	.min_llcc_ib = 800000,
273	.min_dram_ib = 800000,
274	.undersized_prefill_lines = 2,
275	.xtra_prefill_lines = 2,
276	.dest_scale_prefill_lines = 3,
277	.macrotile_prefill_lines = 4,
278	.yuv_nv12_prefill_lines = 8,
279	.linear_prefill_lines = 1,
280	.downscaling_prefill_lines = 1,
281	.amortizable_threshold = 25,
282	.min_prefill_lines = 24,
283	.danger_lut_tbl = {0xf, 0xffff, 0x0},
284	.safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
285	.qos_lut_tbl = {
286		{.nentry = ARRAY_SIZE(sdm845_qos_linear),
287		.entries = sdm845_qos_linear
288		},
289		{.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
290		.entries = sdm845_qos_macrotile
291		},
292		{.nentry = ARRAY_SIZE(sdm845_qos_nrt),
293		.entries = sdm845_qos_nrt
294		},
295	},
296	.cdp_cfg = {
297		{.rd_enable = 1, .wr_enable = 1},
298		{.rd_enable = 1, .wr_enable = 0}
299	},
300	.clk_inefficiency_factor = 105,
301	.bw_inefficiency_factor = 120,
302};
303
304static const struct dpu_mdss_version sdm845_mdss_ver = {
305	.core_major_ver = 4,
306	.core_minor_ver = 0,
307};
308
309const struct dpu_mdss_cfg dpu_sdm845_cfg = {
310	.mdss_ver = &sdm845_mdss_ver,
311	.caps = &sdm845_dpu_caps,
312	.mdp = &sdm845_mdp,
313	.cdm = &dpu_cdm_1_x_4_x,
314	.ctl_count = ARRAY_SIZE(sdm845_ctl),
315	.ctl = sdm845_ctl,
316	.sspp_count = ARRAY_SIZE(sdm845_sspp),
317	.sspp = sdm845_sspp,
318	.mixer_count = ARRAY_SIZE(sdm845_lm),
319	.mixer = sdm845_lm,
320	.dspp_count = ARRAY_SIZE(sdm845_dspp),
321	.dspp = sdm845_dspp,
322	.pingpong_count = ARRAY_SIZE(sdm845_pp),
323	.pingpong = sdm845_pp,
324	.dsc_count = ARRAY_SIZE(sdm845_dsc),
325	.dsc = sdm845_dsc,
326	.intf_count = ARRAY_SIZE(sdm845_intf),
327	.intf = sdm845_intf,
328	.vbif_count = ARRAY_SIZE(sdm845_vbif),
329	.vbif = sdm845_vbif,
330	.perf = &sdm845_perf_data,
331};
332
333#endif