dpu_3_2_sdm660.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2023. Linaro Inc. All rights reserved.
  4 */
  5
  6#ifndef _DPU_3_2_SDM660_H
  7#define _DPU_3_2_SDM660_H
  8
  9static const struct dpu_caps sdm660_dpu_caps = {
 10	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 11	.max_mixer_blendstages = 0x7,
 12	.has_src_split = true,
 13	.has_dim_layer = true,
 14	.has_idle_pc = true,
 15	.has_3d_merge = true,
 16	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 17	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 18	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 19	.max_vdeci_exp = MAX_VERT_DECIMATION,
 20};
 21
 22static const struct dpu_mdp_cfg sdm660_mdp = {
 23	.name = "top_0",
 24	.base = 0x0, .len = 0x458,
 25	.clk_ctrls = {
 26		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 27		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 28		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 29		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 30		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
 31		[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
 32	},
 33};
 34
 35static const struct dpu_ctl_cfg sdm660_ctl[] = {
 36	{
 37		.name = "ctl_0", .id = CTL_0,
 38		.base = 0x1000, .len = 0x94,
 39		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
 40	}, {
 41		.name = "ctl_1", .id = CTL_1,
 42		.base = 0x1200, .len = 0x94,
 43	}, {
 44		.name = "ctl_2", .id = CTL_2,
 45		.base = 0x1400, .len = 0x94,
 46		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
 47	}, {
 48		.name = "ctl_3", .id = CTL_3,
 49		.base = 0x1600, .len = 0x94,
 50	}, {
 51		.name = "ctl_4", .id = CTL_4,
 52		.base = 0x1800, .len = 0x94,
 53	},
 54};
 55
 56static const struct dpu_sspp_cfg sdm660_sspp[] = {
 57	{
 58		.name = "sspp_0", .id = SSPP_VIG0,
 59		.base = 0x4000, .len = 0x1ac,
 60		.features = VIG_MSM8998_MASK,
 61		.sblk = &dpu_vig_sblk_qseed3_1_2,
 62		.xin_id = 0,
 63		.type = SSPP_TYPE_VIG,
 64		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 65	}, {
 66		.name = "sspp_1", .id = SSPP_VIG1,
 67		.base = 0x6000, .len = 0x1ac,
 68		.features = VIG_MSM8998_MASK,
 69		.sblk = &dpu_vig_sblk_qseed3_1_2,
 70		.xin_id = 4,
 71		.type = SSPP_TYPE_VIG,
 72		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 73	}, {
 74		.name = "sspp_8", .id = SSPP_DMA0,
 75		.base = 0x24000, .len = 0x1ac,
 76		.features = DMA_MSM8998_MASK,
 77		.sblk = &dpu_dma_sblk,
 78		.xin_id = 1,
 79		.type = SSPP_TYPE_DMA,
 80		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 81	}, {
 82		.name = "sspp_9", .id = SSPP_DMA1,
 83		.base = 0x26000, .len = 0x1ac,
 84		.features = DMA_MSM8998_MASK,
 85		.sblk = &dpu_dma_sblk,
 86		.xin_id = 5,
 87		.type = SSPP_TYPE_DMA,
 88		.clk_ctrl = DPU_CLK_CTRL_DMA1,
 89	}, {
 90		.name = "sspp_10", .id = SSPP_DMA2,
 91		.base = 0x28000, .len = 0x1ac,
 92		.features = DMA_CURSOR_MSM8998_MASK,
 93		.sblk = &dpu_dma_sblk,
 94		.xin_id = 9,
 95		.type = SSPP_TYPE_DMA,
 96		.clk_ctrl = DPU_CLK_CTRL_DMA2,
 97	},
 98};
 99
100static const struct dpu_lm_cfg sdm660_lm[] = {
101	{
102		.name = "lm_0", .id = LM_0,
103		.base = 0x44000, .len = 0x320,
104		.features = MIXER_MSM8998_MASK,
105		.sblk = &msm8998_lm_sblk,
106		.lm_pair = LM_1,
107		.pingpong = PINGPONG_0,
108		.dspp = DSPP_0,
109	}, {
110		.name = "lm_1", .id = LM_1,
111		.base = 0x45000, .len = 0x320,
112		.features = MIXER_MSM8998_MASK,
113		.sblk = &msm8998_lm_sblk,
114		.lm_pair = LM_0,
115		.pingpong = PINGPONG_1,
116		.dspp = DSPP_1,
117	}, {
118		.name = "lm_2", .id = LM_2,
119		.base = 0x46000, .len = 0x320,
120		.features = MIXER_MSM8998_MASK,
121		.sblk = &msm8998_lm_sblk,
122		.lm_pair = LM_5,
123		.pingpong = PINGPONG_2,
124	}, {
125		.name = "lm_5", .id = LM_5,
126		.base = 0x49000, .len = 0x320,
127		.features = MIXER_MSM8998_MASK,
128		.sblk = &msm8998_lm_sblk,
129		.lm_pair = LM_2,
130		.pingpong = PINGPONG_3,
131	},
132};
133
134static const struct dpu_pingpong_cfg sdm660_pp[] = {
135	{
136		.name = "pingpong_0", .id = PINGPONG_0,
137		.base = 0x70000, .len = 0xd4,
138		.sblk = &sdm845_pp_sblk,
139		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
140		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
141	}, {
142		.name = "pingpong_1", .id = PINGPONG_1,
143		.base = 0x70800, .len = 0xd4,
144		.sblk = &sdm845_pp_sblk,
145		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
146		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
147	}, {
148		.name = "pingpong_2", .id = PINGPONG_2,
149		.base = 0x71000, .len = 0xd4,
150		.sblk = &sdm845_pp_sblk,
151		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
152		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
153	}, {
154		.name = "pingpong_3", .id = PINGPONG_3,
155		.base = 0x71800, .len = 0xd4,
156		.sblk = &sdm845_pp_sblk,
157		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
158		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
159	},
160};
161
162static const struct dpu_dsc_cfg sdm660_dsc[] = {
163	{
164		.name = "dsc_0", .id = DSC_0,
165		.base = 0x80000, .len = 0x140,
166	}, {
167		.name = "dsc_1", .id = DSC_1,
168		.base = 0x80400, .len = 0x140,
169	},
170};
171
172static const struct dpu_dspp_cfg sdm660_dspp[] = {
173	{
174		.name = "dspp_0", .id = DSPP_0,
175		.base = 0x54000, .len = 0x1800,
176		.sblk = &msm8998_dspp_sblk,
177	}, {
178		.name = "dspp_1", .id = DSPP_1,
179		.base = 0x56000, .len = 0x1800,
180		.sblk = &msm8998_dspp_sblk,
181	},
182};
183
184static const struct dpu_intf_cfg sdm660_intf[] = {
185	{
186		.name = "intf_0", .id = INTF_0,
187		.base = 0x6a000, .len = 0x280,
188		.type = INTF_DP,
189		.controller_id = MSM_DP_CONTROLLER_0,
190		.prog_fetch_lines_worst_case = 21,
191		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
192		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
193	}, {
194		.name = "intf_1", .id = INTF_1,
195		.base = 0x6a800, .len = 0x280,
196		.type = INTF_DSI,
197		.controller_id = MSM_DSI_CONTROLLER_0,
198		.prog_fetch_lines_worst_case = 21,
199		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
200		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
201	}, {
202		.name = "intf_2", .id = INTF_2,
203		.base = 0x6b000, .len = 0x280,
204		.type = INTF_DSI,
205		.controller_id = MSM_DSI_CONTROLLER_1,
206		.prog_fetch_lines_worst_case = 21,
207		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
208		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
209	},
210};
211
212static const struct dpu_perf_cfg sdm660_perf_data = {
213	.max_bw_low = 6600000,
214	.max_bw_high = 6600000,
215	.min_core_ib = 3100000,
216	.min_llcc_ib = 800000,
217	.min_dram_ib = 800000,
218	.undersized_prefill_lines = 2,
219	.xtra_prefill_lines = 2,
220	.dest_scale_prefill_lines = 3,
221	.macrotile_prefill_lines = 4,
222	.yuv_nv12_prefill_lines = 8,
223	.linear_prefill_lines = 1,
224	.downscaling_prefill_lines = 1,
225	.amortizable_threshold = 25,
226	.min_prefill_lines = 25,
227	.danger_lut_tbl = {0xf, 0xffff, 0x0},
228	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
229	.qos_lut_tbl = {
230		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
231		.entries = msm8998_qos_linear
232		},
233		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
234		.entries = msm8998_qos_macrotile
235		},
236		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
237		.entries = msm8998_qos_nrt
238		},
239	},
240	.cdp_cfg = {
241		{.rd_enable = 1, .wr_enable = 1},
242		{.rd_enable = 1, .wr_enable = 0}
243	},
244	.clk_inefficiency_factor = 200,
245	.bw_inefficiency_factor = 120,
246};
247
248static const struct dpu_mdss_version sdm660_mdss_ver = {
249	.core_major_ver = 3,
250	.core_minor_ver = 2,
251};
252
253const struct dpu_mdss_cfg dpu_sdm660_cfg = {
254	.mdss_ver = &sdm660_mdss_ver,
255	.caps = &sdm660_dpu_caps,
256	.mdp = &sdm660_mdp,
257	.cdm = &dpu_cdm_1_x_4_x,
258	.ctl_count = ARRAY_SIZE(sdm660_ctl),
259	.ctl = sdm660_ctl,
260	.sspp_count = ARRAY_SIZE(sdm660_sspp),
261	.sspp = sdm660_sspp,
262	.mixer_count = ARRAY_SIZE(sdm660_lm),
263	.mixer = sdm660_lm,
264	.dspp_count = ARRAY_SIZE(sdm660_dspp),
265	.dspp = sdm660_dspp,
266	.pingpong_count = ARRAY_SIZE(sdm660_pp),
267	.pingpong = sdm660_pp,
268	.dsc_count = ARRAY_SIZE(sdm660_dsc),
269	.dsc = sdm660_dsc,
270	.intf_count = ARRAY_SIZE(sdm660_intf),
271	.intf = sdm660_intf,
272	.vbif_count = ARRAY_SIZE(msm8998_vbif),
273	.vbif = msm8998_vbif,
274	.perf = &sdm660_perf_data,
275};
276
277#endif