dpu_3_0_msm8998.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_3_0_MSM8998_H
  8#define _DPU_3_0_MSM8998_H
  9
 10static const struct dpu_caps msm8998_dpu_caps = {
 11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 12	.max_mixer_blendstages = 0x7,
 13	.has_src_split = true,
 14	.has_dim_layer = true,
 15	.has_idle_pc = true,
 16	.has_3d_merge = true,
 17	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 19	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 20	.max_vdeci_exp = MAX_VERT_DECIMATION,
 21};
 22
 23static const struct dpu_mdp_cfg msm8998_mdp = {
 24	.name = "top_0",
 25	.base = 0x0, .len = 0x458,
 26	.clk_ctrls = {
 27		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 28		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 29		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
 30		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
 31		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 32		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 33		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
 34		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
 35		[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
 36		[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
 37	},
 38};
 39
 40static const struct dpu_ctl_cfg msm8998_ctl[] = {
 41	{
 42		.name = "ctl_0", .id = CTL_0,
 43		.base = 0x1000, .len = 0x94,
 44		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
 45	}, {
 46		.name = "ctl_1", .id = CTL_1,
 47		.base = 0x1200, .len = 0x94,
 48	}, {
 49		.name = "ctl_2", .id = CTL_2,
 50		.base = 0x1400, .len = 0x94,
 51		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
 52	}, {
 53		.name = "ctl_3", .id = CTL_3,
 54		.base = 0x1600, .len = 0x94,
 55	}, {
 56		.name = "ctl_4", .id = CTL_4,
 57		.base = 0x1800, .len = 0x94,
 58	},
 59};
 60
 61static const struct dpu_sspp_cfg msm8998_sspp[] = {
 62	{
 63		.name = "sspp_0", .id = SSPP_VIG0,
 64		.base = 0x4000, .len = 0x1ac,
 65		.features = VIG_MSM8998_MASK,
 66		.sblk = &dpu_vig_sblk_qseed3_1_2,
 67		.xin_id = 0,
 68		.type = SSPP_TYPE_VIG,
 69		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 70	}, {
 71		.name = "sspp_1", .id = SSPP_VIG1,
 72		.base = 0x6000, .len = 0x1ac,
 73		.features = VIG_MSM8998_MASK,
 74		.sblk = &dpu_vig_sblk_qseed3_1_2,
 75		.xin_id = 4,
 76		.type = SSPP_TYPE_VIG,
 77		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 78	}, {
 79		.name = "sspp_2", .id = SSPP_VIG2,
 80		.base = 0x8000, .len = 0x1ac,
 81		.features = VIG_MSM8998_MASK,
 82		.sblk = &dpu_vig_sblk_qseed3_1_2,
 83		.xin_id = 8,
 84		.type = SSPP_TYPE_VIG,
 85		.clk_ctrl = DPU_CLK_CTRL_VIG2,
 86	}, {
 87		.name = "sspp_3", .id = SSPP_VIG3,
 88		.base = 0xa000, .len = 0x1ac,
 89		.features = VIG_MSM8998_MASK,
 90		.sblk = &dpu_vig_sblk_qseed3_1_2,
 91		.xin_id = 12,
 92		.type = SSPP_TYPE_VIG,
 93		.clk_ctrl = DPU_CLK_CTRL_VIG3,
 94	}, {
 95		.name = "sspp_8", .id = SSPP_DMA0,
 96		.base = 0x24000, .len = 0x1ac,
 97		.features = DMA_MSM8998_MASK,
 98		.sblk = &dpu_dma_sblk,
 99		.xin_id = 1,
100		.type = SSPP_TYPE_DMA,
101		.clk_ctrl = DPU_CLK_CTRL_DMA0,
102	}, {
103		.name = "sspp_9", .id = SSPP_DMA1,
104		.base = 0x26000, .len = 0x1ac,
105		.features = DMA_MSM8998_MASK,
106		.sblk = &dpu_dma_sblk,
107		.xin_id = 5,
108		.type = SSPP_TYPE_DMA,
109		.clk_ctrl = DPU_CLK_CTRL_DMA1,
110	}, {
111		.name = "sspp_10", .id = SSPP_DMA2,
112		.base = 0x28000, .len = 0x1ac,
113		.features = DMA_CURSOR_MSM8998_MASK,
114		.sblk = &dpu_dma_sblk,
115		.xin_id = 9,
116		.type = SSPP_TYPE_DMA,
117		.clk_ctrl = DPU_CLK_CTRL_DMA2,
118	}, {
119		.name = "sspp_11", .id = SSPP_DMA3,
120		.base = 0x2a000, .len = 0x1ac,
121		.features = DMA_CURSOR_MSM8998_MASK,
122		.sblk = &dpu_dma_sblk,
123		.xin_id = 13,
124		.type = SSPP_TYPE_DMA,
125		.clk_ctrl = DPU_CLK_CTRL_DMA3,
126	},
127};
128
129static const struct dpu_lm_cfg msm8998_lm[] = {
130	{
131		.name = "lm_0", .id = LM_0,
132		.base = 0x44000, .len = 0x320,
133		.features = MIXER_MSM8998_MASK,
134		.sblk = &msm8998_lm_sblk,
135		.lm_pair = LM_1,
136		.pingpong = PINGPONG_0,
137		.dspp = DSPP_0,
138	}, {
139		.name = "lm_1", .id = LM_1,
140		.base = 0x45000, .len = 0x320,
141		.features = MIXER_MSM8998_MASK,
142		.sblk = &msm8998_lm_sblk,
143		.lm_pair = LM_0,
144		.pingpong = PINGPONG_1,
145		.dspp = DSPP_1,
146	}, {
147		.name = "lm_2", .id = LM_2,
148		.base = 0x46000, .len = 0x320,
149		.features = MIXER_MSM8998_MASK,
150		.sblk = &msm8998_lm_sblk,
151		.lm_pair = LM_5,
152		.pingpong = PINGPONG_2,
153	}, {
154		.name = "lm_5", .id = LM_5,
155		.base = 0x49000, .len = 0x320,
156		.features = MIXER_MSM8998_MASK,
157		.sblk = &msm8998_lm_sblk,
158		.lm_pair = LM_2,
159		.pingpong = PINGPONG_3,
160	},
161};
162
163static const struct dpu_pingpong_cfg msm8998_pp[] = {
164	{
165		.name = "pingpong_0", .id = PINGPONG_0,
166		.base = 0x70000, .len = 0xd4,
167		.sblk = &sdm845_pp_sblk,
168		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
169		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
170	}, {
171		.name = "pingpong_1", .id = PINGPONG_1,
172		.base = 0x70800, .len = 0xd4,
173		.sblk = &sdm845_pp_sblk,
174		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
175		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
176	}, {
177		.name = "pingpong_2", .id = PINGPONG_2,
178		.base = 0x71000, .len = 0xd4,
179		.sblk = &sdm845_pp_sblk,
180		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
181		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
182	}, {
183		.name = "pingpong_3", .id = PINGPONG_3,
184		.base = 0x71800, .len = 0xd4,
185		.sblk = &sdm845_pp_sblk,
186		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
187		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
188	},
189};
190
191static const struct dpu_dsc_cfg msm8998_dsc[] = {
192	{
193		.name = "dsc_0", .id = DSC_0,
194		.base = 0x80000, .len = 0x140,
195	}, {
196		.name = "dsc_1", .id = DSC_1,
197		.base = 0x80400, .len = 0x140,
198	},
199};
200
201static const struct dpu_dspp_cfg msm8998_dspp[] = {
202	{
203		.name = "dspp_0", .id = DSPP_0,
204		.base = 0x54000, .len = 0x1800,
205		.sblk = &msm8998_dspp_sblk,
206	}, {
207		.name = "dspp_1", .id = DSPP_1,
208		.base = 0x56000, .len = 0x1800,
209		.sblk = &msm8998_dspp_sblk,
210	},
211};
212
213static const struct dpu_intf_cfg msm8998_intf[] = {
214	{
215		.name = "intf_0", .id = INTF_0,
216		.base = 0x6a000, .len = 0x280,
217		.type = INTF_DP,
218		.controller_id = MSM_DP_CONTROLLER_0,
219		.prog_fetch_lines_worst_case = 21,
220		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
221		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
222	}, {
223		.name = "intf_1", .id = INTF_1,
224		.base = 0x6a800, .len = 0x280,
225		.type = INTF_DSI,
226		.controller_id = MSM_DSI_CONTROLLER_0,
227		.prog_fetch_lines_worst_case = 21,
228		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
229		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
230	}, {
231		.name = "intf_2", .id = INTF_2,
232		.base = 0x6b000, .len = 0x280,
233		.type = INTF_DSI,
234		.controller_id = MSM_DSI_CONTROLLER_1,
235		.prog_fetch_lines_worst_case = 21,
236		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
237		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
238	}, {
239		.name = "intf_3", .id = INTF_3,
240		.base = 0x6b800, .len = 0x280,
241		.type = INTF_HDMI,
242		.prog_fetch_lines_worst_case = 21,
243		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
244		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
245	},
246};
247
248static const struct dpu_perf_cfg msm8998_perf_data = {
249	.max_bw_low = 6700000,
250	.max_bw_high = 6700000,
251	.min_core_ib = 2400000,
252	.min_llcc_ib = 800000,
253	.min_dram_ib = 800000,
254	.undersized_prefill_lines = 2,
255	.xtra_prefill_lines = 2,
256	.dest_scale_prefill_lines = 3,
257	.macrotile_prefill_lines = 4,
258	.yuv_nv12_prefill_lines = 8,
259	.linear_prefill_lines = 1,
260	.downscaling_prefill_lines = 1,
261	.amortizable_threshold = 25,
262	.min_prefill_lines = 25,
263	.danger_lut_tbl = {0xf, 0xffff, 0x0},
264	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
265	.qos_lut_tbl = {
266		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
267		.entries = msm8998_qos_linear
268		},
269		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
270		.entries = msm8998_qos_macrotile
271		},
272		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
273		.entries = msm8998_qos_nrt
274		},
275	},
276	.cdp_cfg = {
277		{.rd_enable = 1, .wr_enable = 1},
278		{.rd_enable = 1, .wr_enable = 0}
279	},
280	.clk_inefficiency_factor = 200,
281	.bw_inefficiency_factor = 120,
282};
283
284static const struct dpu_mdss_version msm8998_mdss_ver = {
285	.core_major_ver = 3,
286	.core_minor_ver = 0,
287};
288
289const struct dpu_mdss_cfg dpu_msm8998_cfg = {
290	.mdss_ver = &msm8998_mdss_ver,
291	.caps = &msm8998_dpu_caps,
292	.mdp = &msm8998_mdp,
293	.cdm = &dpu_cdm_1_x_4_x,
294	.ctl_count = ARRAY_SIZE(msm8998_ctl),
295	.ctl = msm8998_ctl,
296	.sspp_count = ARRAY_SIZE(msm8998_sspp),
297	.sspp = msm8998_sspp,
298	.mixer_count = ARRAY_SIZE(msm8998_lm),
299	.mixer = msm8998_lm,
300	.dspp_count = ARRAY_SIZE(msm8998_dspp),
301	.dspp = msm8998_dspp,
302	.pingpong_count = ARRAY_SIZE(msm8998_pp),
303	.pingpong = msm8998_pp,
304	.dsc_count = ARRAY_SIZE(msm8998_dsc),
305	.dsc = msm8998_dsc,
306	.intf_count = ARRAY_SIZE(msm8998_intf),
307	.intf = msm8998_intf,
308	.vbif_count = ARRAY_SIZE(msm8998_vbif),
309	.vbif = msm8998_vbif,
310	.perf = &msm8998_perf_data,
311};
312
313#endif