dpu_1_7_msm8996.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2023, Linaro Limited
  4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  6 */
  7
  8#ifndef _DPU_1_7_MSM8996_H
  9#define _DPU_1_7_MSM8996_H
 10
 11static const struct dpu_caps msm8996_dpu_caps = {
 12	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 13	.max_mixer_blendstages = 0x7,
 14	.has_src_split = true,
 15	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 16	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 17	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 18	.max_vdeci_exp = MAX_VERT_DECIMATION,
 19};
 20
 21static const struct dpu_mdp_cfg msm8996_mdp[] = {
 22	{
 23		.name = "top_0",
 24		.base = 0x0, .len = 0x454,
 25		.clk_ctrls = {
 26			[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 27			[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
 28			[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
 29			[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
 30			[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
 31			[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
 32			[DPU_CLK_CTRL_RGB2] = { .reg_off = 0x2bc, .bit_off = 4 },
 33			[DPU_CLK_CTRL_RGB3] = { .reg_off = 0x2c4, .bit_off = 4 },
 34			[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 35			[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
 36			[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
 37			[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
 38		},
 39	},
 40};
 41
 42static const struct dpu_ctl_cfg msm8996_ctl[] = {
 43	{
 44		.name = "ctl_0", .id = CTL_0,
 45		.base = 0x1000, .len = 0x64,
 46	}, {
 47		.name = "ctl_1", .id = CTL_1,
 48		.base = 0x1200, .len = 0x64,
 49	}, {
 50		.name = "ctl_2", .id = CTL_2,
 51		.base = 0x1400, .len = 0x64,
 52	}, {
 53		.name = "ctl_3", .id = CTL_3,
 54		.base = 0x1600, .len = 0x64,
 55	}, {
 56		.name = "ctl_4", .id = CTL_4,
 57		.base = 0x1800, .len = 0x64,
 58	},
 59};
 60
 61static const struct dpu_sspp_cfg msm8996_sspp[] = {
 62	{
 63		.name = "sspp_0", .id = SSPP_VIG0,
 64		.base = 0x4000, .len = 0x150,
 65		.features = VIG_MSM8996_MASK,
 66		.sblk = &dpu_vig_sblk_qseed2,
 67		.xin_id = 0,
 68		.type = SSPP_TYPE_VIG,
 69		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 70	}, {
 71		.name = "sspp_1", .id = SSPP_VIG1,
 72		.base = 0x6000, .len = 0x150,
 73		.features = VIG_MSM8996_MASK,
 74		.sblk = &dpu_vig_sblk_qseed2,
 75		.xin_id = 4,
 76		.type = SSPP_TYPE_VIG,
 77		.clk_ctrl = DPU_CLK_CTRL_VIG1,
 78	}, {
 79		.name = "sspp_2", .id = SSPP_VIG2,
 80		.base = 0x8000, .len = 0x150,
 81		.features = VIG_MSM8996_MASK,
 82		.sblk = &dpu_vig_sblk_qseed2,
 83		.xin_id = 8,
 84		.type = SSPP_TYPE_VIG,
 85		.clk_ctrl = DPU_CLK_CTRL_VIG2,
 86	}, {
 87		.name = "sspp_3", .id = SSPP_VIG3,
 88		.base = 0xa000, .len = 0x150,
 89		.features = VIG_MSM8996_MASK,
 90		.sblk = &dpu_vig_sblk_qseed2,
 91		.xin_id = 12,
 92		.type = SSPP_TYPE_VIG,
 93		.clk_ctrl = DPU_CLK_CTRL_VIG3,
 94	}, {
 95		.name = "sspp_4", .id = SSPP_RGB0,
 96		.base = 0x14000, .len = 0x150,
 97		.features = RGB_MSM8996_MASK,
 98		.sblk = &dpu_rgb_sblk,
 99		.xin_id = 1,
100		.type = SSPP_TYPE_RGB,
101		.clk_ctrl = DPU_CLK_CTRL_RGB0,
102	}, {
103		.name = "sspp_5", .id = SSPP_RGB1,
104		.base = 0x16000, .len = 0x150,
105		.features = RGB_MSM8996_MASK,
106		.sblk = &dpu_rgb_sblk,
107		.xin_id = 5,
108		.type = SSPP_TYPE_RGB,
109		.clk_ctrl = DPU_CLK_CTRL_RGB1,
110	}, {
111		.name = "sspp_6", .id = SSPP_RGB2,
112		.base = 0x18000, .len = 0x150,
113		.features = RGB_MSM8996_MASK,
114		.sblk = &dpu_rgb_sblk,
115		.xin_id = 9,
116		.type = SSPP_TYPE_RGB,
117		.clk_ctrl = DPU_CLK_CTRL_RGB2,
118	}, {
119		.name = "sspp_7", .id = SSPP_RGB3,
120		.base = 0x1a000, .len = 0x150,
121		.features = RGB_MSM8996_MASK,
122		.sblk = &dpu_rgb_sblk,
123		.xin_id = 13,
124		.type = SSPP_TYPE_RGB,
125		.clk_ctrl = DPU_CLK_CTRL_RGB3,
126	}, {
127		.name = "sspp_8", .id = SSPP_DMA0,
128		.base = 0x24000, .len = 0x150,
129		.features = DMA_MSM8996_MASK,
130		.sblk = &dpu_dma_sblk,
131		.xin_id = 2,
132		.type = SSPP_TYPE_DMA,
133		.clk_ctrl = DPU_CLK_CTRL_DMA0,
134	}, {
135		.name = "sspp_9", .id = SSPP_DMA1,
136		.base = 0x26000, .len = 0x150,
137		.features = DMA_MSM8996_MASK,
138		.sblk = &dpu_dma_sblk,
139		.xin_id = 10,
140		.type = SSPP_TYPE_DMA,
141		.clk_ctrl = DPU_CLK_CTRL_DMA1,
142	},
143};
144
145static const struct dpu_lm_cfg msm8996_lm[] = {
146	{
147		.name = "lm_0", .id = LM_0,
148		.base = 0x44000, .len = 0x320,
149		.features = MIXER_MSM8998_MASK,
150		.sblk = &msm8998_lm_sblk,
151		.lm_pair = LM_1,
152		.pingpong = PINGPONG_0,
153		.dspp = DSPP_0,
154	}, {
155		.name = "lm_1", .id = LM_1,
156		.base = 0x45000, .len = 0x320,
157		.features = MIXER_MSM8998_MASK,
158		.sblk = &msm8998_lm_sblk,
159		.lm_pair = LM_0,
160		.pingpong = PINGPONG_1,
161		.dspp = DSPP_1,
162	}, {
163		.name = "lm_2", .id = LM_2,
164		.base = 0x46000, .len = 0x320,
165		.features = MIXER_MSM8998_MASK,
166		.sblk = &msm8998_lm_sblk,
167		.lm_pair = LM_5,
168		.pingpong = PINGPONG_2,
169	}, {
170		.name = "lm_5", .id = LM_5,
171		.base = 0x49000, .len = 0x320,
172		.features = MIXER_MSM8998_MASK,
173		.sblk = &msm8998_lm_sblk,
174		.lm_pair = LM_2,
175		.pingpong = PINGPONG_3,
176	},
177};
178
179static const struct dpu_pingpong_cfg msm8996_pp[] = {
180	{
181		.name = "pingpong_0", .id = PINGPONG_0,
182		.base = 0x70000, .len = 0xd4,
183		.sblk = &msm8996_pp_sblk,
184		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
185		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
186	}, {
187		.name = "pingpong_1", .id = PINGPONG_1,
188		.base = 0x70800, .len = 0xd4,
189		.sblk = &msm8996_pp_sblk,
190		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
191		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
192	}, {
193		.name = "pingpong_2", .id = PINGPONG_2,
194		.base = 0x71000, .len = 0xd4,
195		.sblk = &msm8996_pp_sblk,
196		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
197		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
198	}, {
199		.name = "pingpong_3", .id = PINGPONG_3,
200		.base = 0x71800, .len = 0xd4,
201		.sblk = &msm8996_pp_sblk,
202		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
203		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
204	},
205};
206
207static const struct dpu_dsc_cfg msm8996_dsc[] = {
208	{
209		.name = "dsc_0", .id = DSC_0,
210		.base = 0x80000, .len = 0x140,
211	}, {
212		.name = "dsc_1", .id = DSC_1,
213		.base = 0x80400, .len = 0x140,
214	},
215};
216
217static const struct dpu_dspp_cfg msm8996_dspp[] = {
218	{
219		.name = "dspp_0", .id = DSPP_0,
220		.base = 0x54000, .len = 0x1800,
221		.sblk = &msm8998_dspp_sblk,
222	}, {
223		.name = "dspp_1", .id = DSPP_1,
224		.base = 0x56000, .len = 0x1800,
225		.sblk = &msm8998_dspp_sblk,
226	},
227};
228
229static const struct dpu_intf_cfg msm8996_intf[] = {
230	{
231		.name = "intf_0", .id = INTF_0,
232		.base = 0x6a000, .len = 0x268,
233		.type = INTF_NONE,
234		.prog_fetch_lines_worst_case = 25,
235		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
236		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
237	}, {
238		.name = "intf_1", .id = INTF_1,
239		.base = 0x6a800, .len = 0x268,
240		.type = INTF_DSI,
241		.controller_id = MSM_DSI_CONTROLLER_0,
242		.prog_fetch_lines_worst_case = 25,
243		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
244		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
245	}, {
246		.name = "intf_2", .id = INTF_2,
247		.base = 0x6b000, .len = 0x268,
248		.type = INTF_DSI,
249		.controller_id = MSM_DSI_CONTROLLER_1,
250		.prog_fetch_lines_worst_case = 25,
251		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
252		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
253	}, {
254		.name = "intf_3", .id = INTF_3,
255		.base = 0x6b800, .len = 0x268,
256		.type = INTF_HDMI,
257		.prog_fetch_lines_worst_case = 25,
258		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
259		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
260	},
261};
262
263static const struct dpu_perf_cfg msm8996_perf_data = {
264	.max_bw_low = 9600000,
265	.max_bw_high = 9600000,
266	.min_core_ib = 2400000,
267	.min_llcc_ib = 0, /* No LLCC on this SoC */
268	.min_dram_ib = 800000,
269	.undersized_prefill_lines = 2,
270	.xtra_prefill_lines = 2,
271	.dest_scale_prefill_lines = 3,
272	.macrotile_prefill_lines = 4,
273	.yuv_nv12_prefill_lines = 8,
274	.linear_prefill_lines = 1,
275	.downscaling_prefill_lines = 1,
276	.amortizable_threshold = 25,
277	.min_prefill_lines = 21,
278	.danger_lut_tbl = {0xf, 0xffff, 0x0},
279	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
280	.qos_lut_tbl = {
281		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
282		.entries = msm8998_qos_linear
283		},
284		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
285		.entries = msm8998_qos_macrotile
286		},
287		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
288		.entries = msm8998_qos_nrt
289		},
290	},
291	.cdp_cfg = {
292		{.rd_enable = 1, .wr_enable = 1},
293		{.rd_enable = 1, .wr_enable = 0}
294	},
295	.clk_inefficiency_factor = 105,
296	.bw_inefficiency_factor = 120,
297};
298
299static const struct dpu_mdss_version msm8996_mdss_ver = {
300	.core_major_ver = 1,
301	.core_minor_ver = 7,
302};
303
304const struct dpu_mdss_cfg dpu_msm8996_cfg = {
305	.mdss_ver = &msm8996_mdss_ver,
306	.caps = &msm8996_dpu_caps,
307	.mdp = msm8996_mdp,
308	.cdm = &dpu_cdm_1_x_4_x,
309	.ctl_count = ARRAY_SIZE(msm8996_ctl),
310	.ctl = msm8996_ctl,
311	.sspp_count = ARRAY_SIZE(msm8996_sspp),
312	.sspp = msm8996_sspp,
313	.mixer_count = ARRAY_SIZE(msm8996_lm),
314	.mixer = msm8996_lm,
315	.dspp_count = ARRAY_SIZE(msm8996_dspp),
316	.dspp = msm8996_dspp,
317	.pingpong_count = ARRAY_SIZE(msm8996_pp),
318	.pingpong = msm8996_pp,
319	.dsc_count = ARRAY_SIZE(msm8996_dsc),
320	.dsc = msm8996_dsc,
321	.intf_count = ARRAY_SIZE(msm8996_intf),
322	.intf = msm8996_intf,
323	.vbif_count = ARRAY_SIZE(msm8996_vbif),
324	.vbif = msm8996_vbif,
325	.perf = &msm8996_perf_data,
326};
327
328#endif