dpu_1_15_msm8917.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2023, Linaro Limited
  4 */
  5
  6#ifndef _DPU_1_14_MSM8917_H
  7#define _DPU_1_14_MSM8917_H
  8
  9static const struct dpu_caps msm8917_dpu_caps = {
 10	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
 11	.max_mixer_blendstages = 0x4,
 12	.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
 13	.pixel_ram_size = 16 * 1024,
 14	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 15	.max_vdeci_exp = MAX_VERT_DECIMATION,
 16};
 17
 18static const struct dpu_mdp_cfg msm8917_mdp[] = {
 19	{
 20		.name = "top_0",
 21		.base = 0x0, .len = 0x454,
 22		.clk_ctrls = {
 23			[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 24			[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
 25			[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
 26			[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 27			[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
 28		},
 29	},
 30};
 31
 32static const struct dpu_ctl_cfg msm8917_ctl[] = {
 33	{
 34		.name = "ctl_0", .id = CTL_0,
 35		.base = 0x1000, .len = 0x64,
 36	}, {
 37		.name = "ctl_1", .id = CTL_1,
 38		.base = 0x1200, .len = 0x64,
 39	}, {
 40		.name = "ctl_2", .id = CTL_2,
 41		.base = 0x1400, .len = 0x64,
 42	},
 43};
 44
 45static const struct dpu_sspp_cfg msm8917_sspp[] = {
 46	{
 47		.name = "sspp_0", .id = SSPP_VIG0,
 48		.base = 0x4000, .len = 0x150,
 49		.features = VIG_MSM8953_MASK,
 50		.sblk = &dpu_vig_sblk_qseed2,
 51		.xin_id = 0,
 52		.type = SSPP_TYPE_VIG,
 53		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 54	}, {
 55		.name = "sspp_4", .id = SSPP_RGB0,
 56		.base = 0x14000, .len = 0x150,
 57		.features = RGB_MSM8953_MASK,
 58		.sblk = &dpu_rgb_sblk,
 59		.xin_id = 1,
 60		.type = SSPP_TYPE_RGB,
 61		.clk_ctrl = DPU_CLK_CTRL_RGB0,
 62	}, {
 63		.name = "sspp_5", .id = SSPP_RGB1,
 64		.base = 0x16000, .len = 0x150,
 65		.features = RGB_MSM8953_MASK,
 66		.sblk = &dpu_rgb_sblk,
 67		.xin_id = 5,
 68		.type = SSPP_TYPE_RGB,
 69		.clk_ctrl = DPU_CLK_CTRL_RGB1,
 70	}, {
 71		.name = "sspp_8", .id = SSPP_DMA0,
 72		.base = 0x24000, .len = 0x150,
 73		.features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
 74		.sblk = &dpu_dma_sblk,
 75		.xin_id = 2,
 76		.type = SSPP_TYPE_DMA,
 77		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 78	},
 79};
 80
 81static const struct dpu_lm_cfg msm8917_lm[] = {
 82	{
 83		.name = "lm_0", .id = LM_0,
 84		.base = 0x44000, .len = 0x320,
 85		.sblk = &msm8998_lm_sblk,
 86		.pingpong = PINGPONG_0,
 87		.dspp = DSPP_0,
 88	},
 89};
 90
 91static const struct dpu_pingpong_cfg msm8917_pp[] = {
 92	{
 93		.name = "pingpong_0", .id = PINGPONG_0,
 94		.base = 0x70000, .len = 0xd4,
 95		.sblk = &msm8996_pp_sblk,
 96		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
 97		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
 98	},
 99};
100
101static const struct dpu_dspp_cfg msm8917_dspp[] = {
102	{
103		.name = "dspp_0", .id = DSPP_0,
104		.base = 0x54000, .len = 0x1800,
105		.sblk = &msm8998_dspp_sblk,
106	},
107};
108
109static const struct dpu_intf_cfg msm8917_intf[] = {
110	{
111		.name = "intf_1", .id = INTF_1,
112		.base = 0x6a800, .len = 0x268,
113		.type = INTF_DSI,
114		.controller_id = MSM_DSI_CONTROLLER_0,
115		.prog_fetch_lines_worst_case = 14,
116		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
117		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
118	},
119};
120
121static const struct dpu_perf_cfg msm8917_perf_data = {
122	.max_bw_low = 1800000,
123	.max_bw_high = 1800000,
124	.min_core_ib = 2400000,
125	.min_llcc_ib = 0, /* No LLCC on this SoC */
126	.min_dram_ib = 800000,
127	.undersized_prefill_lines = 2,
128	.xtra_prefill_lines = 2,
129	.dest_scale_prefill_lines = 3,
130	.macrotile_prefill_lines = 4,
131	.yuv_nv12_prefill_lines = 8,
132	.linear_prefill_lines = 1,
133	.downscaling_prefill_lines = 1,
134	.amortizable_threshold = 25,
135	.min_prefill_lines = 21,
136	.danger_lut_tbl = {0xf, 0xffff, 0x0},
137	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
138	.qos_lut_tbl = {
139		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
140		.entries = msm8998_qos_linear
141		},
142		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
143		.entries = msm8998_qos_macrotile
144		},
145		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
146		.entries = msm8998_qos_nrt
147		},
148	},
149	.cdp_cfg = {
150		{.rd_enable = 1, .wr_enable = 1},
151		{.rd_enable = 1, .wr_enable = 0}
152	},
153	.clk_inefficiency_factor = 105,
154	.bw_inefficiency_factor = 120,
155};
156
157static const struct dpu_mdss_version msm8917_mdss_ver = {
158	.core_major_ver = 1,
159	.core_minor_ver = 15,
160};
161
162const struct dpu_mdss_cfg dpu_msm8917_cfg = {
163	.mdss_ver = &msm8917_mdss_ver,
164	.caps = &msm8917_dpu_caps,
165	.mdp = msm8917_mdp,
166	.cdm = &dpu_cdm_1_x_4_x,
167	.ctl_count = ARRAY_SIZE(msm8917_ctl),
168	.ctl = msm8917_ctl,
169	.sspp_count = ARRAY_SIZE(msm8917_sspp),
170	.sspp = msm8917_sspp,
171	.mixer_count = ARRAY_SIZE(msm8917_lm),
172	.mixer = msm8917_lm,
173	.dspp_count = ARRAY_SIZE(msm8917_dspp),
174	.dspp = msm8917_dspp,
175	.pingpong_count = ARRAY_SIZE(msm8917_pp),
176	.pingpong = msm8917_pp,
177	.intf_count = ARRAY_SIZE(msm8917_intf),
178	.intf = msm8917_intf,
179	.vbif_count = ARRAY_SIZE(msm8996_vbif),
180	.vbif = msm8996_vbif,
181	.perf = &msm8917_perf_data,
182};
183
184#endif