dpu_1_14_msm8937.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2023, Linaro Limited
  4 */
  5
  6#ifndef _DPU_1_14_MSM8937_H
  7#define _DPU_1_14_MSM8937_H
  8
  9static const struct dpu_caps msm8937_dpu_caps = {
 10	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
 11	.max_mixer_blendstages = 0x4,
 12	.max_linewidth = DEFAULT_DPU_LINE_WIDTH,
 13	.pixel_ram_size = 40 * 1024,
 14	.max_hdeci_exp = MAX_HORZ_DECIMATION,
 15	.max_vdeci_exp = MAX_VERT_DECIMATION,
 16};
 17
 18static const struct dpu_mdp_cfg msm8937_mdp[] = {
 19	{
 20		.name = "top_0",
 21		.base = 0x0, .len = 0x454,
 22		.clk_ctrls = {
 23			[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
 24			[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
 25			[DPU_CLK_CTRL_RGB1] = { .reg_off = 0x2b4, .bit_off = 4 },
 26			[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
 27			[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
 28		},
 29	},
 30};
 31
 32static const struct dpu_ctl_cfg msm8937_ctl[] = {
 33	{
 34		.name = "ctl_0", .id = CTL_0,
 35		.base = 0x1000, .len = 0x64,
 36	}, {
 37		.name = "ctl_1", .id = CTL_1,
 38		.base = 0x1200, .len = 0x64,
 39	}, {
 40		.name = "ctl_2", .id = CTL_2,
 41		.base = 0x1400, .len = 0x64,
 42	},
 43};
 44
 45static const struct dpu_sspp_cfg msm8937_sspp[] = {
 46	{
 47		.name = "sspp_0", .id = SSPP_VIG0,
 48		.base = 0x4000, .len = 0x150,
 49		.features = VIG_MSM8953_MASK,
 50		.sblk = &dpu_vig_sblk_qseed2,
 51		.xin_id = 0,
 52		.type = SSPP_TYPE_VIG,
 53		.clk_ctrl = DPU_CLK_CTRL_VIG0,
 54	}, {
 55		.name = "sspp_4", .id = SSPP_RGB0,
 56		.base = 0x14000, .len = 0x150,
 57		.features = RGB_MSM8953_MASK,
 58		.sblk = &dpu_rgb_sblk,
 59		.xin_id = 1,
 60		.type = SSPP_TYPE_RGB,
 61		.clk_ctrl = DPU_CLK_CTRL_RGB0,
 62	}, {
 63		.name = "sspp_5", .id = SSPP_RGB1,
 64		.base = 0x16000, .len = 0x150,
 65		.features = RGB_MSM8953_MASK,
 66		.sblk = &dpu_rgb_sblk,
 67		.xin_id = 5,
 68		.type = SSPP_TYPE_RGB,
 69		.clk_ctrl = DPU_CLK_CTRL_RGB1,
 70	}, {
 71		.name = "sspp_8", .id = SSPP_DMA0,
 72		.base = 0x24000, .len = 0x150,
 73		.features = DMA_MSM8953_MASK | BIT(DPU_SSPP_CURSOR),
 74		.sblk = &dpu_dma_sblk,
 75		.xin_id = 2,
 76		.type = SSPP_TYPE_DMA,
 77		.clk_ctrl = DPU_CLK_CTRL_DMA0,
 78	},
 79};
 80
 81static const struct dpu_lm_cfg msm8937_lm[] = {
 82	{
 83		.name = "lm_0", .id = LM_0,
 84		.base = 0x44000, .len = 0x320,
 85		.sblk = &msm8998_lm_sblk,
 86		.lm_pair = LM_1,
 87		.pingpong = PINGPONG_0,
 88		.dspp = DSPP_0,
 89	}, {
 90		.name = "lm_1", .id = LM_1,
 91		.base = 0x45000, .len = 0x320,
 92		.sblk = &msm8998_lm_sblk,
 93		.lm_pair = LM_0,
 94		.pingpong = PINGPONG_1,
 95	},
 96};
 97
 98static const struct dpu_pingpong_cfg msm8937_pp[] = {
 99	{
100		.name = "pingpong_0", .id = PINGPONG_0,
101		.base = 0x70000, .len = 0xd4,
102		.sblk = &msm8996_pp_sblk,
103		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
104		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
105	}, {
106		.name = "pingpong_1", .id = PINGPONG_1,
107		.base = 0x70800, .len = 0xd4,
108		.sblk = &msm8996_pp_sblk,
109		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
110		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
111	},
112};
113
114static const struct dpu_dspp_cfg msm8937_dspp[] = {
115	{
116		.name = "dspp_0", .id = DSPP_0,
117		.base = 0x54000, .len = 0x1800,
118		.sblk = &msm8998_dspp_sblk,
119	},
120};
121
122static const struct dpu_intf_cfg msm8937_intf[] = {
123	{
124		.name = "intf_1", .id = INTF_1,
125		.base = 0x6a800, .len = 0x268,
126		.type = INTF_DSI,
127		.controller_id = MSM_DSI_CONTROLLER_0,
128		.prog_fetch_lines_worst_case = 14,
129		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
130		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
131	}, {
132		.name = "intf_2", .id = INTF_2,
133		.base = 0x6b000, .len = 0x268,
134		.type = INTF_DSI,
135		.controller_id = MSM_DSI_CONTROLLER_1,
136		.prog_fetch_lines_worst_case = 14,
137		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
138		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
139	},
140};
141
142static const struct dpu_perf_cfg msm8937_perf_data = {
143	.max_bw_low = 3100000,
144	.max_bw_high = 3100000,
145	.min_core_ib = 2400000,
146	.min_llcc_ib = 0, /* No LLCC on this SoC */
147	.min_dram_ib = 800000,
148	.undersized_prefill_lines = 2,
149	.xtra_prefill_lines = 2,
150	.dest_scale_prefill_lines = 3,
151	.macrotile_prefill_lines = 4,
152	.yuv_nv12_prefill_lines = 8,
153	.linear_prefill_lines = 1,
154	.downscaling_prefill_lines = 1,
155	.amortizable_threshold = 25,
156	.min_prefill_lines = 14,
157	.danger_lut_tbl = {0xf, 0xffff, 0x0},
158	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
159	.qos_lut_tbl = {
160		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
161		.entries = msm8998_qos_linear
162		},
163		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
164		.entries = msm8998_qos_macrotile
165		},
166		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
167		.entries = msm8998_qos_nrt
168		},
169	},
170	.cdp_cfg = {
171		{.rd_enable = 1, .wr_enable = 1},
172		{.rd_enable = 1, .wr_enable = 0}
173	},
174	.clk_inefficiency_factor = 105,
175	.bw_inefficiency_factor = 120,
176};
177
178static const struct dpu_mdss_version msm8937_mdss_ver = {
179	.core_major_ver = 1,
180	.core_minor_ver = 14,
181};
182
183const struct dpu_mdss_cfg dpu_msm8937_cfg = {
184	.mdss_ver = &msm8937_mdss_ver,
185	.caps = &msm8937_dpu_caps,
186	.mdp = msm8937_mdp,
187	.cdm = &dpu_cdm_1_x_4_x,
188	.ctl_count = ARRAY_SIZE(msm8937_ctl),
189	.ctl = msm8937_ctl,
190	.sspp_count = ARRAY_SIZE(msm8937_sspp),
191	.sspp = msm8937_sspp,
192	.mixer_count = ARRAY_SIZE(msm8937_lm),
193	.mixer = msm8937_lm,
194	.dspp_count = ARRAY_SIZE(msm8937_dspp),
195	.dspp = msm8937_dspp,
196	.pingpong_count = ARRAY_SIZE(msm8937_pp),
197	.pingpong = msm8937_pp,
198	.intf_count = ARRAY_SIZE(msm8937_intf),
199	.intf = msm8937_intf,
200	.vbif_count = ARRAY_SIZE(msm8996_vbif),
201	.vbif = msm8996_vbif,
202	.perf = &msm8937_perf_data,
203};
204
205#endif