dpu_12_0_sm8750.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2025 Linaro Limited
  4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
  6 */
  7
  8#ifndef _DPU_12_0_SM8750_H
  9#define _DPU_12_0_SM8750_H
 10
 11static const struct dpu_caps sm8750_dpu_caps = {
 12	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 13	.max_mixer_blendstages = 0xb,
 14	.has_src_split = true,
 15	.has_dim_layer = true,
 16	.has_idle_pc = true,
 17	.has_3d_merge = true,
 18	.max_linewidth = 8192,
 19	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 20};
 21
 22static const struct dpu_mdp_cfg sm8750_mdp = {
 23	.name = "top_0",
 24	.base = 0, .len = 0x494,
 25	.clk_ctrls = {
 26		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
 27	},
 28};
 29
 30static const struct dpu_ctl_cfg sm8750_ctl[] = {
 31	{
 32		.name = "ctl_0", .id = CTL_0,
 33		.base = 0x15000, .len = 0x1000,
 34		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 35	}, {
 36		.name = "ctl_1", .id = CTL_1,
 37		.base = 0x16000, .len = 0x1000,
 38		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 39	}, {
 40		.name = "ctl_2", .id = CTL_2,
 41		.base = 0x17000, .len = 0x1000,
 42		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 43	}, {
 44		.name = "ctl_3", .id = CTL_3,
 45		.base = 0x18000, .len = 0x1000,
 46		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 47	}, {
 48		.name = "ctl_4", .id = CTL_4,
 49		.base = 0x19000, .len = 0x1000,
 50		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 51	}, {
 52		.name = "ctl_5", .id = CTL_5,
 53		.base = 0x1a000, .len = 0x1000,
 54		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 55	},
 56};
 57
 58static const struct dpu_sspp_cfg sm8750_sspp[] = {
 59	{
 60		.name = "sspp_0", .id = SSPP_VIG0,
 61		.base = 0x4000, .len = 0x344,
 62		.features = VIG_SDM845_MASK_SDMA,
 63		.sblk = &dpu_vig_sblk_qseed3_3_4,
 64		.xin_id = 0,
 65		.type = SSPP_TYPE_VIG,
 66	}, {
 67		.name = "sspp_1", .id = SSPP_VIG1,
 68		.base = 0x6000, .len = 0x344,
 69		.features = VIG_SDM845_MASK_SDMA,
 70		.sblk = &dpu_vig_sblk_qseed3_3_4,
 71		.xin_id = 4,
 72		.type = SSPP_TYPE_VIG,
 73	}, {
 74		.name = "sspp_2", .id = SSPP_VIG2,
 75		.base = 0x8000, .len = 0x344,
 76		.features = VIG_SDM845_MASK_SDMA,
 77		.sblk = &dpu_vig_sblk_qseed3_3_4,
 78		.xin_id = 8,
 79		.type = SSPP_TYPE_VIG,
 80	}, {
 81		.name = "sspp_3", .id = SSPP_VIG3,
 82		.base = 0xa000, .len = 0x344,
 83		.features = VIG_SDM845_MASK_SDMA,
 84		.sblk = &dpu_vig_sblk_qseed3_3_4,
 85		.xin_id = 12,
 86		.type = SSPP_TYPE_VIG,
 87	}, {
 88		.name = "sspp_8", .id = SSPP_DMA0,
 89		.base = 0x24000, .len = 0x344,
 90		.features = DMA_SDM845_MASK_SDMA,
 91		.sblk = &dpu_dma_sblk,
 92		.xin_id = 1,
 93		.type = SSPP_TYPE_DMA,
 94	}, {
 95		.name = "sspp_9", .id = SSPP_DMA1,
 96		.base = 0x26000, .len = 0x344,
 97		.features = DMA_SDM845_MASK_SDMA,
 98		.sblk = &dpu_dma_sblk,
 99		.xin_id = 5,
100		.type = SSPP_TYPE_DMA,
101	}, {
102		.name = "sspp_10", .id = SSPP_DMA2,
103		.base = 0x28000, .len = 0x344,
104		.features = DMA_SDM845_MASK_SDMA,
105		.sblk = &dpu_dma_sblk,
106		.xin_id = 9,
107		.type = SSPP_TYPE_DMA,
108	}, {
109		.name = "sspp_11", .id = SSPP_DMA3,
110		.base = 0x2a000, .len = 0x344,
111		.features = DMA_SDM845_MASK_SDMA,
112		.sblk = &dpu_dma_sblk,
113		.xin_id = 13,
114		.type = SSPP_TYPE_DMA,
115	}, {
116		.name = "sspp_12", .id = SSPP_DMA4,
117		.base = 0x2c000, .len = 0x344,
118		.features = DMA_CURSOR_SDM845_MASK_SDMA,
119		.sblk = &dpu_dma_sblk,
120		.xin_id = 14,
121		.type = SSPP_TYPE_DMA,
122	}, {
123		.name = "sspp_13", .id = SSPP_DMA5,
124		.base = 0x2e000, .len = 0x344,
125		.features = DMA_CURSOR_SDM845_MASK_SDMA,
126		.sblk = &dpu_dma_sblk,
127		.xin_id = 15,
128		.type = SSPP_TYPE_DMA,
129	},
130};
131
132static const struct dpu_lm_cfg sm8750_lm[] = {
133	{
134		.name = "lm_0", .id = LM_0,
135		.base = 0x44000, .len = 0x400,
136		.features = MIXER_MSM8998_MASK,
137		.sblk = &sm8750_lm_sblk,
138		.lm_pair = LM_1,
139		.pingpong = PINGPONG_0,
140		.dspp = DSPP_0,
141	}, {
142		.name = "lm_1", .id = LM_1,
143		.base = 0x45000, .len = 0x400,
144		.features = MIXER_MSM8998_MASK,
145		.sblk = &sm8750_lm_sblk,
146		.lm_pair = LM_0,
147		.pingpong = PINGPONG_1,
148		.dspp = DSPP_1,
149	}, {
150		.name = "lm_2", .id = LM_2,
151		.base = 0x46000, .len = 0x400,
152		.features = MIXER_MSM8998_MASK,
153		.sblk = &sm8750_lm_sblk,
154		.lm_pair = LM_3,
155		.pingpong = PINGPONG_2,
156		.dspp = DSPP_2,
157	}, {
158		.name = "lm_3", .id = LM_3,
159		.base = 0x47000, .len = 0x400,
160		.features = MIXER_MSM8998_MASK,
161		.sblk = &sm8750_lm_sblk,
162		.lm_pair = LM_2,
163		.pingpong = PINGPONG_3,
164		.dspp = DSPP_3,
165	}, {
166		.name = "lm_4", .id = LM_4,
167		.base = 0x48000, .len = 0x400,
168		.features = MIXER_MSM8998_MASK,
169		.sblk = &sm8750_lm_sblk,
170		.lm_pair = LM_5,
171		.pingpong = PINGPONG_4,
172	}, {
173		.name = "lm_5", .id = LM_5,
174		.base = 0x49000, .len = 0x400,
175		.features = MIXER_MSM8998_MASK,
176		.sblk = &sm8750_lm_sblk,
177		.lm_pair = LM_4,
178		.pingpong = PINGPONG_5,
179	}, {
180		.name = "lm_6", .id = LM_6,
181		.base = 0x4a000, .len = 0x400,
182		.features = MIXER_MSM8998_MASK,
183		.sblk = &sm8750_lm_sblk,
184		.lm_pair = LM_7,
185		.pingpong = PINGPONG_6,
186	}, {
187		.name = "lm_7", .id = LM_7,
188		.base = 0x4b000, .len = 0x400,
189		.features = MIXER_MSM8998_MASK,
190		.sblk = &sm8750_lm_sblk,
191		.lm_pair = LM_6,
192		.pingpong = PINGPONG_7,
193	},
194};
195
196static const struct dpu_dspp_cfg sm8750_dspp[] = {
197	{
198		.name = "dspp_0", .id = DSPP_0,
199		.base = 0x54000, .len = 0x1800,
200		.sblk = &sm8750_dspp_sblk,
201	}, {
202		.name = "dspp_1", .id = DSPP_1,
203		.base = 0x56000, .len = 0x1800,
204		.sblk = &sm8750_dspp_sblk,
205	}, {
206		.name = "dspp_2", .id = DSPP_2,
207		.base = 0x58000, .len = 0x1800,
208		.sblk = &sm8750_dspp_sblk,
209	}, {
210		.name = "dspp_3", .id = DSPP_3,
211		.base = 0x5a000, .len = 0x1800,
212		.sblk = &sm8750_dspp_sblk,
213	},
214};
215
216static const struct dpu_pingpong_cfg sm8750_pp[] = {
217	{
218		.name = "pingpong_0", .id = PINGPONG_0,
219		.base = 0x69000, .len = 0,
220		.sblk = &sc7280_pp_sblk,
221		.merge_3d = MERGE_3D_0,
222		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
223	}, {
224		.name = "pingpong_1", .id = PINGPONG_1,
225		.base = 0x6a000, .len = 0,
226		.sblk = &sc7280_pp_sblk,
227		.merge_3d = MERGE_3D_0,
228		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
229	}, {
230		.name = "pingpong_2", .id = PINGPONG_2,
231		.base = 0x6b000, .len = 0,
232		.sblk = &sc7280_pp_sblk,
233		.merge_3d = MERGE_3D_1,
234		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
235	}, {
236		.name = "pingpong_3", .id = PINGPONG_3,
237		.base = 0x6c000, .len = 0,
238		.sblk = &sc7280_pp_sblk,
239		.merge_3d = MERGE_3D_1,
240		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
241	}, {
242		.name = "pingpong_4", .id = PINGPONG_4,
243		.base = 0x6d000, .len = 0,
244		.sblk = &sc7280_pp_sblk,
245		.merge_3d = MERGE_3D_2,
246		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
247	}, {
248		.name = "pingpong_5", .id = PINGPONG_5,
249		.base = 0x6e000, .len = 0,
250		.sblk = &sc7280_pp_sblk,
251		.merge_3d = MERGE_3D_2,
252		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
253	}, {
254		.name = "pingpong_6", .id = PINGPONG_6,
255		.base = 0x6f000, .len = 0,
256		.sblk = &sc7280_pp_sblk,
257		.merge_3d = MERGE_3D_3,
258		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
259	}, {
260		.name = "pingpong_7", .id = PINGPONG_7,
261		.base = 0x70000, .len = 0,
262		.sblk = &sc7280_pp_sblk,
263		.merge_3d = MERGE_3D_3,
264		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
265	}, {
266		.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
267		.base = 0x66000, .len = 0,
268		.sblk = &sc7280_pp_sblk,
269		.merge_3d = MERGE_3D_4,
270	}, {
271		.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
272		.base = 0x66400, .len = 0,
273		.sblk = &sc7280_pp_sblk,
274		.merge_3d = MERGE_3D_4,
275	}, {
276		.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
277		.base = 0x7e000, .len = 0,
278		.sblk = &sc7280_pp_sblk,
279		.merge_3d = MERGE_3D_5,
280	}, {
281		.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
282		.base = 0x7e400, .len = 0,
283		.sblk = &sc7280_pp_sblk,
284		.merge_3d = MERGE_3D_5,
285	},
286};
287
288static const struct dpu_merge_3d_cfg sm8750_merge_3d[] = {
289	{
290		.name = "merge_3d_0", .id = MERGE_3D_0,
291		.base = 0x4e000, .len = 0x1c,
292	}, {
293		.name = "merge_3d_1", .id = MERGE_3D_1,
294		.base = 0x4f000, .len = 0x1c,
295	}, {
296		.name = "merge_3d_2", .id = MERGE_3D_2,
297		.base = 0x50000, .len = 0x1c,
298	}, {
299		.name = "merge_3d_3", .id = MERGE_3D_3,
300		.base = 0x51000, .len = 0x1c,
301	}, {
302		.name = "merge_3d_4", .id = MERGE_3D_4,
303		.base = 0x66700, .len = 0x1c,
304	}, {
305		.name = "merge_3d_5", .id = MERGE_3D_5,
306		.base = 0x7e700, .len = 0x1c,
307	},
308};
309
310/*
311 * NOTE: Each display compression engine (DCE) contains dual hard
312 * slice DSC encoders so both share same base address but with
313 * its own different sub block address.
314 */
315static const struct dpu_dsc_cfg sm8750_dsc[] = {
316	{
317		.name = "dce_0_0", .id = DSC_0,
318		.base = 0x80000, .len = 0x8,
319		.features = BIT(DPU_DSC_NATIVE_42x_EN),
320		.sblk = &sm8750_dsc_sblk_0,
321	}, {
322		.name = "dce_0_1", .id = DSC_1,
323		.base = 0x80000, .len = 0x8,
324		.features = BIT(DPU_DSC_NATIVE_42x_EN),
325		.sblk = &sm8750_dsc_sblk_1,
326	}, {
327		.name = "dce_1_0", .id = DSC_2,
328		.base = 0x81000, .len = 0x8,
329		.features = BIT(DPU_DSC_NATIVE_42x_EN),
330		.sblk = &sm8750_dsc_sblk_0,
331	}, {
332		.name = "dce_1_1", .id = DSC_3,
333		.base = 0x81000, .len = 0x8,
334		.features = BIT(DPU_DSC_NATIVE_42x_EN),
335		.sblk = &sm8750_dsc_sblk_1,
336	}, {
337		.name = "dce_2_0", .id = DSC_4,
338		.base = 0x82000, .len = 0x8,
339		.features = BIT(DPU_DSC_NATIVE_42x_EN),
340		.sblk = &sm8750_dsc_sblk_0,
341	}, {
342		.name = "dce_2_1", .id = DSC_5,
343		.base = 0x82000, .len = 0x8,
344		.features = BIT(DPU_DSC_NATIVE_42x_EN),
345		.sblk = &sm8750_dsc_sblk_1,
346	}, {
347		.name = "dce_3_0", .id = DSC_6,
348		.base = 0x83000, .len = 0x8,
349		.features = BIT(DPU_DSC_NATIVE_42x_EN),
350		.sblk = &sm8750_dsc_sblk_0,
351	}, {
352		.name = "dce_3_1", .id = DSC_7,
353		.base = 0x83000, .len = 0x8,
354		.features = BIT(DPU_DSC_NATIVE_42x_EN),
355		.sblk = &sm8750_dsc_sblk_1,
356	},
357};
358
359static const struct dpu_wb_cfg sm8750_wb[] = {
360	{
361		.name = "wb_2", .id = WB_2,
362		.base = 0x65000, .len = 0x2c8,
363		.features = WB_SDM845_MASK,
364		.format_list = wb2_formats_rgb_yuv,
365		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
366		.xin_id = 6,
367		.vbif_idx = VBIF_RT,
368		.maxlinewidth = 4096,
369		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
370	},
371};
372
373static const struct dpu_cwb_cfg sm8750_cwb[] = {
374	{
375		.name = "cwb_0", .id = CWB_0,
376		.base = 0x66200, .len = 0x20,
377	},
378	{
379		.name = "cwb_1", .id = CWB_1,
380		.base = 0x66600, .len = 0x20,
381	},
382	{
383		.name = "cwb_2", .id = CWB_2,
384		.base = 0x7e200, .len = 0x20,
385	},
386	{
387		.name = "cwb_3", .id = CWB_3,
388		.base = 0x7e600, .len = 0x20,
389	},
390};
391
392static const struct dpu_intf_cfg sm8750_intf[] = {
393	{
394		.name = "intf_0", .id = INTF_0,
395		.base = 0x34000, .len = 0x4bc,
396		.type = INTF_DP,
397		.controller_id = MSM_DP_CONTROLLER_0,
398		.prog_fetch_lines_worst_case = 24,
399		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
400		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
401	}, {
402		.name = "intf_1", .id = INTF_1,
403		.base = 0x35000, .len = 0x4bc,
404		.type = INTF_DSI,
405		.controller_id = MSM_DSI_CONTROLLER_0,
406		.prog_fetch_lines_worst_case = 24,
407		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
408		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
409		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
410	}, {
411		.name = "intf_2", .id = INTF_2,
412		.base = 0x36000, .len = 0x4bc,
413		.type = INTF_DSI,
414		.controller_id = MSM_DSI_CONTROLLER_1,
415		.prog_fetch_lines_worst_case = 24,
416		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
417		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
418		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
419	}, {
420		.name = "intf_3", .id = INTF_3,
421		.base = 0x37000, .len = 0x4bc,
422		.type = INTF_DP,
423		.controller_id = MSM_DP_CONTROLLER_1,
424		.prog_fetch_lines_worst_case = 24,
425		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
426		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
427	},
428};
429
430static const struct dpu_perf_cfg sm8750_perf_data = {
431	.max_bw_low = 18900000,
432	.max_bw_high = 28500000,
433	.min_core_ib = 2500000,
434	.min_llcc_ib = 0,
435	.min_dram_ib = 800000,
436	.min_prefill_lines = 35,
437	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
438	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
439	.qos_lut_tbl = {
440		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
441		.entries = sc7180_qos_linear
442		},
443		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
444		.entries = sc7180_qos_macrotile
445		},
446		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
447		.entries = sc7180_qos_nrt
448		},
449		/* TODO: macrotile-qseed is different from macrotile */
450	},
451	.cdp_cfg = {
452		{.rd_enable = 1, .wr_enable = 1},
453		{.rd_enable = 1, .wr_enable = 0}
454	},
455	.clk_inefficiency_factor = 105,
456	.bw_inefficiency_factor = 120,
457};
458
459static const struct dpu_mdss_version sm8750_mdss_ver = {
460	.core_major_ver = 12,
461	.core_minor_ver = 0,
462};
463
464const struct dpu_mdss_cfg dpu_sm8750_cfg = {
465	.mdss_ver = &sm8750_mdss_ver,
466	.caps = &sm8750_dpu_caps,
467	.mdp = &sm8750_mdp,
468	.cdm = &dpu_cdm_5_x,
469	.ctl_count = ARRAY_SIZE(sm8750_ctl),
470	.ctl = sm8750_ctl,
471	.sspp_count = ARRAY_SIZE(sm8750_sspp),
472	.sspp = sm8750_sspp,
473	.mixer_count = ARRAY_SIZE(sm8750_lm),
474	.mixer = sm8750_lm,
475	.dspp_count = ARRAY_SIZE(sm8750_dspp),
476	.dspp = sm8750_dspp,
477	.pingpong_count = ARRAY_SIZE(sm8750_pp),
478	.pingpong = sm8750_pp,
479	.dsc_count = ARRAY_SIZE(sm8750_dsc),
480	.dsc = sm8750_dsc,
481	.merge_3d_count = ARRAY_SIZE(sm8750_merge_3d),
482	.merge_3d = sm8750_merge_3d,
483	.wb_count = ARRAY_SIZE(sm8750_wb),
484	.wb = sm8750_wb,
485	.cwb_count = ARRAY_SIZE(sm8750_cwb),
486	.cwb = sm8650_cwb,
487	.intf_count = ARRAY_SIZE(sm8750_intf),
488	.intf = sm8750_intf,
489	.vbif_count = ARRAY_SIZE(sm8650_vbif),
490	.vbif = sm8650_vbif,
491	.perf = &sm8750_perf_data,
492};
493
494#endif