adreno_gpu.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2013 Red Hat
  4 * Author: Rob Clark <robdclark@gmail.com>
  5 *
  6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
  7 */
  8
  9#ifndef __ADRENO_GPU_H__
 10#define __ADRENO_GPU_H__
 11
 12#include <linux/firmware.h>
 13#include <linux/iopoll.h>
 14
 15#include <linux/soc/qcom/ubwc.h>
 16
 17#include "msm_gpu.h"
 18
 19#include "adreno_common.xml.h"
 20#include "adreno_pm4.xml.h"
 21
 22extern bool snapshot_debugbus;
 23
 24enum {
 25	ADRENO_FW_PM4 = 0,
 26	ADRENO_FW_SQE = 0, /* a6xx */
 27	ADRENO_FW_PFP = 1,
 28	ADRENO_FW_GMU = 1, /* a6xx */
 29	ADRENO_FW_GPMU = 2,
 30	ADRENO_FW_AQE = 3,
 31	ADRENO_FW_MAX,
 32};
 33
 34/**
 35 * @enum adreno_family: identify generation and possibly sub-generation
 36 *
 37 * In some cases there are distinct sub-generations within a major revision
 38 * so it helps to be able to group the GPU devices by generation and if
 39 * necessary sub-generation.
 40 */
 41enum adreno_family {
 42	ADRENO_2XX_GEN1,  /* a20x */
 43	ADRENO_2XX_GEN2,  /* a22x */
 44	ADRENO_3XX,
 45	ADRENO_4XX,
 46	ADRENO_5XX,
 47	ADRENO_6XX_GEN1,  /* a630 family */
 48	ADRENO_6XX_GEN2,  /* a640 family */
 49	ADRENO_6XX_GEN3,  /* a650 family */
 50	ADRENO_6XX_GEN4,  /* a660 family */
 51	ADRENO_7XX_GEN1,  /* a730 family */
 52	ADRENO_7XX_GEN2,  /* a740 family */
 53	ADRENO_7XX_GEN3,  /* a750 family */
 54	ADRENO_8XX_GEN1,  /* a830 family */
 55	ADRENO_8XX_GEN2,  /* a840 family */
 56};
 57
 58#define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
 59#define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
 60#define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
 61#define ADRENO_QUIRK_HAS_HW_APRIV		BIT(3)
 62#define ADRENO_QUIRK_HAS_CACHED_COHERENT	BIT(4)
 63#define ADRENO_QUIRK_PREEMPTION			BIT(5)
 64#define ADRENO_QUIRK_4GB_VA			BIT(6)
 65#define ADRENO_QUIRK_IFPC			BIT(7)
 66
 67/* Helper for formating the chip_id in the way that userspace tools like
 68 * crashdec expect.
 69 */
 70#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
 71#define ADRENO_CHIPID_ARGS(_c) \
 72	(((_c) >> 24) & 0xff), \
 73	(((_c) >> 16) & 0xff), \
 74	(((_c) >> 8)  & 0xff), \
 75	((_c) & 0xff)
 76
 77struct adreno_gpu;
 78
 79struct adreno_gpu_funcs {
 80	struct msm_gpu_funcs base;
 81	struct msm_gpu *(*init)(struct drm_device *dev);
 82	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
 83	void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
 84	int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
 85};
 86
 87struct adreno_reglist {
 88	u32 offset;
 89	u32 value;
 90};
 91
 92/* Reglist with pipe information */
 93struct adreno_reglist_pipe {
 94	u32 offset;
 95	u32 value;
 96	u32 pipe;
 97};
 98
 99struct adreno_speedbin {
100	uint16_t fuse;
101	uint16_t speedbin;
102};
103
104struct a6xx_info;
105
106struct adreno_info {
107	const char *machine;
108	/**
109	 * @chipids: Table of matching chip-ids
110	 *
111	 * Terminated with 0 sentinal
112	 */
113	uint32_t *chip_ids;
114	enum adreno_family family;
115	uint32_t revn;
116	const char *fw[ADRENO_FW_MAX];
117	uint32_t gmem;
118	u64 quirks;
119	const struct adreno_gpu_funcs *funcs;
120	const char *zapfw;
121	u32 inactive_period;
122	union {
123		const struct a6xx_info *a6xx;
124	};
125	/**
126	 * @speedbins: Optional table of fuse to speedbin mappings
127	 *
128	 * Consists of pairs of fuse, index mappings, terminated with
129	 * {SHRT_MAX, 0} sentinal.
130	 */
131	struct adreno_speedbin *speedbins;
132	u64 preempt_record_size;
133};
134
135#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }
136
137struct adreno_gpulist {
138	const struct adreno_info *gpus;
139	unsigned gpus_count;
140};
141
142#define DECLARE_ADRENO_GPULIST(name)                  \
143const struct adreno_gpulist name ## _gpulist = {      \
144	name ## _gpus, ARRAY_SIZE(name ## _gpus)      \
145}
146
147/*
148 * Helper to build a speedbin table, ie. the table:
149 *      fuse | speedbin
150 *      -----+---------
151 *        0  |   0
152 *       169 |   1
153 *       174 |   2
154 *
155 * would be declared as:
156 *
157 *     .speedbins = ADRENO_SPEEDBINS(
158 *                      { 0,   0 },
159 *                      { 169, 1 },
160 *                      { 174, 2 },
161 *     ),
162 */
163#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
164
165struct adreno_protect {
166	const uint32_t *regs;
167	uint32_t count;
168	uint32_t count_max;
169};
170
171#define DECLARE_ADRENO_PROTECT(name, __count_max)	\
172static const struct adreno_protect name = {		\
173	.regs = name ## _regs,				\
174	.count = ARRAY_SIZE(name ## _regs),		\
175	.count_max = __count_max,			\
176};
177
178struct adreno_reglist_list {
179	/** @reg: List of register **/
180	const u32 *regs;
181	/** @count: Number of registers in the list **/
182	u32 count;
183};
184
185#define DECLARE_ADRENO_REGLIST_LIST(name)	\
186static const struct adreno_reglist_list name = {		\
187	.regs = name ## _regs,				\
188	.count = ARRAY_SIZE(name ## _regs),		\
189};
190
191struct adreno_reglist_pipe_list {
192	/** @reg: List of register **/
193	const struct adreno_reglist_pipe *regs;
194	/** @count: Number of registers in the list **/
195	u32 count;
196};
197
198#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name)	\
199static const struct adreno_reglist_pipe_list name = {		\
200	.regs = name ## _regs,				\
201	.count = ARRAY_SIZE(name ## _regs),		\
202};
203
204struct adreno_gpu {
205	struct msm_gpu base;
206	const struct adreno_info *info;
207	uint32_t chip_id;
208	uint16_t speedbin;
209	const struct adreno_gpu_funcs *funcs;
210
211	struct completion fault_coredump_done;
212
213	/* interesting register offsets to dump: */
214	const unsigned int *registers;
215
216	/*
217	 * Are we loading fw from legacy path?  Prior to addition
218	 * of gpu firmware to linux-firmware, the fw files were
219	 * placed in toplevel firmware directory, following qcom's
220	 * android kernel.  But linux-firmware preferred they be
221	 * placed in a 'qcom' subdirectory.
222	 *
223	 * For backwards compatibility, we try first to load from
224	 * the new path, using request_firmware_direct() to avoid
225	 * any potential timeout waiting for usermode helper, then
226	 * fall back to the old path (with direct load).  And
227	 * finally fall back to request_firmware() with the new
228	 * path to allow the usermode helper.
229	 */
230	enum {
231		FW_LOCATION_UNKNOWN = 0,
232		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
233		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
234		FW_LOCATION_HELPER,
235	} fwloc;
236
237	/* firmware: */
238	const struct firmware *fw[ADRENO_FW_MAX];
239
240	/*
241	 * The migration to the central UBWC config db is still in flight - keep
242	 * a copy containing some local fixups until that's done.
243	 */
244	const struct qcom_ubwc_cfg_data *ubwc_config;
245	struct qcom_ubwc_cfg_data _ubwc_config;
246
247	/*
248	 * Register offsets are different between some GPUs.
249	 * GPU specific offsets will be exported by GPU specific
250	 * code (a3xx_gpu.c) and stored in this common location.
251	 */
252	const unsigned int *reg_offsets;
253	bool gmu_is_wrapper;
254
255	bool has_ray_tracing;
256
257	u64 uche_trap_base;
258};
259#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
260
261struct adreno_ocmem {
262	struct ocmem *ocmem;
263	unsigned long base;
264	void *hdl;
265};
266
267/* platform config data (ie. from DT, or pdata) */
268struct adreno_platform_config {
269	uint32_t chip_id;
270	const struct adreno_info *info;
271};
272
273#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
274
275#define spin_until(X) ({                                   \
276	int __ret = -ETIMEDOUT;                            \
277	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
278	do {                                               \
279		if (X) {                                   \
280			__ret = 0;                         \
281			break;                             \
282		}                                          \
283	} while (time_before(jiffies, __t));               \
284	__ret;                                             \
285})
286
287static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu)
288{
289	/* It is probably ok to assume legacy "adreno_rev" format
290	 * for all a6xx devices, but probably best to limit this
291	 * to older things.
292	 */
293	WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
294	return gpu->chip_id & 0xff;
295}
296
297static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
298{
299	if (WARN_ON_ONCE(!gpu->info))
300		return false;
301	return gpu->info->revn == revn;
302}
303
304static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
305{
306	return gpu->gmu_is_wrapper;
307}
308
309static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
310{
311	if (WARN_ON_ONCE(!gpu->info))
312		return false;
313	return gpu->info->family <= ADRENO_2XX_GEN2;
314}
315
316static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
317{
318	if (WARN_ON_ONCE(!gpu->info))
319		return false;
320	return gpu->info->family == ADRENO_2XX_GEN1;
321}
322
323static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
324{
325	return adreno_is_revn(gpu, 225);
326}
327
328static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
329{
330	return adreno_is_revn(gpu, 305);
331}
332
333static inline bool adreno_is_a305b(const struct adreno_gpu *gpu)
334{
335	return gpu->info->chip_ids[0] == 0x03000512;
336}
337
338static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
339{
340	/* yes, 307, because a305c is 306 */
341	return adreno_is_revn(gpu, 307);
342}
343
344static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)
345{
346	/* a306a (marketing name is a308) */
347	return adreno_is_revn(gpu, 308);
348}
349
350static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
351{
352	return adreno_is_revn(gpu, 320);
353}
354
355static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
356{
357	return adreno_is_revn(gpu, 330);
358}
359
360static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
361{
362	return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0);
363}
364
365static inline int adreno_is_a405(const struct adreno_gpu *gpu)
366{
367	return adreno_is_revn(gpu, 405);
368}
369
370static inline int adreno_is_a420(const struct adreno_gpu *gpu)
371{
372	return adreno_is_revn(gpu, 420);
373}
374
375static inline int adreno_is_a430(const struct adreno_gpu *gpu)
376{
377	return adreno_is_revn(gpu, 430);
378}
379
380static inline int adreno_is_a505(const struct adreno_gpu *gpu)
381{
382	return adreno_is_revn(gpu, 505);
383}
384
385static inline int adreno_is_a506(const struct adreno_gpu *gpu)
386{
387	return adreno_is_revn(gpu, 506);
388}
389
390static inline int adreno_is_a508(const struct adreno_gpu *gpu)
391{
392	return adreno_is_revn(gpu, 508);
393}
394
395static inline int adreno_is_a509(const struct adreno_gpu *gpu)
396{
397	return adreno_is_revn(gpu, 509);
398}
399
400static inline int adreno_is_a510(const struct adreno_gpu *gpu)
401{
402	return adreno_is_revn(gpu, 510);
403}
404
405static inline int adreno_is_a512(const struct adreno_gpu *gpu)
406{
407	return adreno_is_revn(gpu, 512);
408}
409
410static inline int adreno_is_a530(const struct adreno_gpu *gpu)
411{
412	return adreno_is_revn(gpu, 530);
413}
414
415static inline int adreno_is_a540(const struct adreno_gpu *gpu)
416{
417	return adreno_is_revn(gpu, 540);
418}
419
420static inline int adreno_is_a610(const struct adreno_gpu *gpu)
421{
422	return adreno_is_revn(gpu, 610);
423}
424
425static inline int adreno_is_a612(const struct adreno_gpu *gpu)
426{
427	return gpu->info->chip_ids[0] == 0x06010200;
428}
429
430static inline bool adreno_has_rgmu(const struct adreno_gpu *gpu)
431{
432	return adreno_is_a612(gpu);
433}
434
435static inline int adreno_is_a618(const struct adreno_gpu *gpu)
436{
437	return adreno_is_revn(gpu, 618);
438}
439
440static inline int adreno_is_a619(const struct adreno_gpu *gpu)
441{
442	return adreno_is_revn(gpu, 619);
443}
444
445static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
446{
447	return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
448}
449
450static inline int adreno_is_a621(const struct adreno_gpu *gpu)
451{
452	return gpu->info->chip_ids[0] == 0x06020100;
453}
454
455static inline int adreno_is_a623(const struct adreno_gpu *gpu)
456{
457	return gpu->info->chip_ids[0] == 0x06020300;
458}
459
460static inline int adreno_is_a630(const struct adreno_gpu *gpu)
461{
462	return adreno_is_revn(gpu, 630);
463}
464
465static inline int adreno_is_a640(const struct adreno_gpu *gpu)
466{
467	return adreno_is_revn(gpu, 640);
468}
469
470static inline int adreno_is_a650(const struct adreno_gpu *gpu)
471{
472	return adreno_is_revn(gpu, 650);
473}
474
475static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
476{
477	return gpu->info->chip_ids[0] == 0x06030500;
478}
479
480static inline int adreno_is_a660(const struct adreno_gpu *gpu)
481{
482	return adreno_is_revn(gpu, 660);
483}
484
485static inline int adreno_is_a680(const struct adreno_gpu *gpu)
486{
487	return adreno_is_revn(gpu, 680);
488}
489
490static inline int adreno_is_a663(const struct adreno_gpu *gpu)
491{
492	return gpu->info->chip_ids[0] == 0x06060300;
493}
494
495static inline int adreno_is_a690(const struct adreno_gpu *gpu)
496{
497	return gpu->info->chip_ids[0] == 0x06090000;
498}
499
500static inline int adreno_is_a702(const struct adreno_gpu *gpu)
501{
502	return gpu->info->chip_ids[0] == 0x07000200;
503}
504
505static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
506{
507	if (WARN_ON_ONCE(!gpu->info))
508		return false;
509	return adreno_is_a610(gpu) ||
510	       adreno_is_a612(gpu) ||
511	       adreno_is_a702(gpu);
512}
513
514/* TODO: 615/616 */
515static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
516{
517	return adreno_is_a618(gpu) ||
518	       adreno_is_a619(gpu);
519}
520
521static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
522{
523	if (WARN_ON_ONCE(!gpu->info))
524		return false;
525	return gpu->info->family == ADRENO_6XX_GEN1;
526}
527
528static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
529{
530	if (WARN_ON_ONCE(!gpu->info))
531		return false;
532	return gpu->info->family == ADRENO_6XX_GEN4;
533}
534
535/* check for a650, a660, or any derivatives */
536static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
537{
538	if (WARN_ON_ONCE(!gpu->info))
539		return false;
540	return gpu->info->family == ADRENO_6XX_GEN3 ||
541	       gpu->info->family == ADRENO_6XX_GEN4;
542}
543
544static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
545{
546	if (WARN_ON_ONCE(!gpu->info))
547		return false;
548	return gpu->info->family == ADRENO_6XX_GEN2;
549}
550
551static inline int adreno_is_a730(struct adreno_gpu *gpu)
552{
553	return gpu->info->chip_ids[0] == 0x07030001;
554}
555
556static inline int adreno_is_a740(struct adreno_gpu *gpu)
557{
558	return gpu->info->chip_ids[0] == 0x43050a01;
559}
560
561static inline int adreno_is_a750(struct adreno_gpu *gpu)
562{
563	return gpu->info->chip_ids[0] == 0x43051401;
564}
565
566static inline int adreno_is_x185(struct adreno_gpu *gpu)
567{
568	return gpu->info->chip_ids[0] == 0x43050c01;
569}
570
571static inline int adreno_is_a740_family(struct adreno_gpu *gpu)
572{
573	if (WARN_ON_ONCE(!gpu->info))
574		return false;
575	return gpu->info->family == ADRENO_7XX_GEN2 ||
576	       gpu->info->family == ADRENO_7XX_GEN3;
577}
578
579static inline int adreno_is_a750_family(struct adreno_gpu *gpu)
580{
581	return gpu->info->family == ADRENO_7XX_GEN3;
582}
583
584static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
585{
586	/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */
587	return gpu->info->family == ADRENO_7XX_GEN1 ||
588	       adreno_is_a740_family(gpu);
589}
590
591static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
592{
593	return gpu->info->family >= ADRENO_8XX_GEN1;
594}
595
596static inline int adreno_is_x285(struct adreno_gpu *gpu)
597{
598	return gpu->info->chip_ids[0] == 0x44070001;
599}
600
601static inline int adreno_is_a840(struct adreno_gpu *gpu)
602{
603	return gpu->info->chip_ids[0] == 0x44050a01;
604}
605
606/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
607#define ADRENO_VM_START 0x100000000ULL
608u64 adreno_private_vm_size(struct msm_gpu *gpu);
609int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
610		     uint32_t param, uint64_t *value, uint32_t *len);
611int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx,
612		     uint32_t param, uint64_t value, uint32_t len);
613const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
614		const char *fwname);
615struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
616		const struct firmware *fw, u64 *iova);
617int adreno_hw_init(struct msm_gpu *gpu);
618void adreno_recover(struct msm_gpu *gpu);
619void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
620bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
621#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
622void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
623		struct drm_printer *p);
624#endif
625void adreno_dump_info(struct msm_gpu *gpu);
626void adreno_dump(struct msm_gpu *gpu);
627void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
628struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
629
630int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
631			  struct adreno_ocmem *ocmem);
632void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
633
634int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
635		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
636		int nr_rings);
637void adreno_gpu_cleanup(struct adreno_gpu *gpu);
638int adreno_load_fw(struct adreno_gpu *adreno_gpu);
639
640void adreno_gpu_state_destroy(struct msm_gpu_state *state);
641
642int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
643int adreno_gpu_state_put(struct msm_gpu_state *state);
644void adreno_show_object(struct drm_printer *p, void **ptr, int len,
645		bool *encoded);
646
647/*
648 * Common helper function to initialize the default address space for arm-smmu
649 * attached targets
650 */
651struct drm_gpuvm *
652adreno_create_vm(struct msm_gpu *gpu,
653		 struct platform_device *pdev);
654
655struct drm_gpuvm *
656adreno_iommu_create_vm(struct msm_gpu *gpu,
657		       struct platform_device *pdev,
658		       unsigned long quirks);
659
660int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
661			 struct adreno_smmu_fault_info *info, const char *block,
662			 u32 scratch[4]);
663
664void adreno_check_and_reenable_stall(struct adreno_gpu *gpu);
665
666int adreno_read_speedbin(struct device *dev, u32 *speedbin);
667
668/*
669 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
670 * out of secure mode
671 */
672int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
673
674/* ringbuffer helpers (the parts that are adreno specific) */
675
676static inline void
677OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
678{
679	adreno_wait_ring(ring, cnt+1);
680	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
681}
682
683/* no-op packet: */
684static inline void
685OUT_PKT2(struct msm_ringbuffer *ring)
686{
687	adreno_wait_ring(ring, 1);
688	OUT_RING(ring, CP_TYPE2_PKT);
689}
690
691static inline void
692OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
693{
694	adreno_wait_ring(ring, cnt+1);
695	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
696}
697
698static inline u32 PM4_PARITY(u32 val)
699{
700	return (0x9669 >> (0xF & (val ^
701		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
702		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
703		(val >> 28)))) & 1;
704}
705
706/* Maximum number of values that can be executed for one opcode */
707#define TYPE4_MAX_PAYLOAD 127
708
709#define PKT4(_reg, _cnt) \
710	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
711	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
712
713static inline void
714OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
715{
716	adreno_wait_ring(ring, cnt + 1);
717	OUT_RING(ring, PKT4(regindx, cnt));
718}
719
720#define PKT7(opcode, cnt) \
721	(CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | \
722		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23))
723
724static inline void
725OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
726{
727	adreno_wait_ring(ring, cnt + 1);
728	OUT_RING(ring, PKT7(opcode, cnt));
729}
730
731static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
732{
733	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
734}
735
736/*
737 * Given a register and a count, return a value to program into
738 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
739 * registers starting at _reg.
740 *
741 * The register base needs to be a multiple of the length. If it is not, the
742 * hardware will quietly mask off the bits for you and shift the size. For
743 * example, if you intend the protection to start at 0x07 for a length of 4
744 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
745 * expose registers you intended to protect!
746 */
747#define ADRENO_PROTECT_RW(_reg, _len) \
748	((1 << 30) | (1 << 29) | \
749	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
750
751/*
752 * Same as above, but allow reads over the range. For areas of mixed use (such
753 * as performance counters) this allows us to protect a much larger range with a
754 * single register
755 */
756#define ADRENO_PROTECT_RDONLY(_reg, _len) \
757	((1 << 29) \
758	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
759
760
761#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
762	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
763		interval, timeout)
764
765#endif /* __ADRENO_GPU_H__ */