adreno_gpu.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2013 Red Hat
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 *
   6 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   7 */
   8
   9#include <linux/ascii85.h>
  10#include <linux/interconnect.h>
  11#include <linux/firmware/qcom/qcom_scm.h>
  12#include <linux/kernel.h>
  13#include <linux/of_reserved_mem.h>
  14#include <linux/pm_opp.h>
  15#include <linux/slab.h>
  16#include <linux/soc/qcom/mdt_loader.h>
  17#include <linux/nvmem-consumer.h>
  18#include <soc/qcom/ocmem.h>
  19#include "adreno_gpu.h"
  20#include "a6xx_gpu.h"
  21#include "msm_gem.h"
  22#include "msm_mmu.h"
  23
  24static u64 address_space_size = 0;
  25MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
  26module_param(address_space_size, ullong, 0600);
  27
  28static bool zap_available = true;
  29
  30static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
  31		u32 pasid)
  32{
  33	struct device *dev = &gpu->pdev->dev;
  34	const struct firmware *fw;
  35	const char *signed_fwname = NULL;
  36	struct device_node *np;
  37	struct resource r;
  38	phys_addr_t mem_phys;
  39	ssize_t mem_size;
  40	void *mem_region = NULL;
  41	int ret;
  42
  43	if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
  44		zap_available = false;
  45		return -EINVAL;
  46	}
  47
  48	np = of_get_child_by_name(dev->of_node, "zap-shader");
  49	if (!of_device_is_available(np)) {
  50		zap_available = false;
  51		return -ENODEV;
  52	}
  53
  54	ret = of_reserved_mem_region_to_resource(np, 0, &r);
  55	if (ret) {
  56		zap_available = false;
  57		return ret;
  58	}
  59	mem_phys = r.start;
  60
  61	/*
  62	 * Check for a firmware-name property.  This is the new scheme
  63	 * to handle firmware that may be signed with device specific
  64	 * keys, allowing us to have a different zap fw path for different
  65	 * devices.
  66	 *
  67	 * If the firmware-name property is found, we bypass the
  68	 * adreno_request_fw() mechanism, because we don't need to handle
  69	 * the /lib/firmware/qcom/... vs /lib/firmware/... case.
  70	 *
  71	 * If the firmware-name property is not found, for backwards
  72	 * compatibility we fall back to the fwname from the gpulist
  73	 * table.
  74	 */
  75	of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
  76	if (signed_fwname) {
  77		fwname = signed_fwname;
  78		ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
  79		if (ret)
  80			fw = ERR_PTR(ret);
  81	} else if (fwname) {
  82		/* Request the MDT file from the default location: */
  83		fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
  84	} else {
  85		/*
  86		 * For new targets, we require the firmware-name property,
  87		 * if a zap-shader is required, rather than falling back
  88		 * to a firmware name specified in gpulist.
  89		 *
  90		 * Because the firmware is signed with a (potentially)
  91		 * device specific key, having the name come from gpulist
  92		 * was a bad idea, and is only provided for backwards
  93		 * compatibility for older targets.
  94		 */
  95		return -ENOENT;
  96	}
  97
  98	if (IS_ERR(fw)) {
  99		DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
 100		return PTR_ERR(fw);
 101	}
 102
 103	/* Figure out how much memory we need */
 104	mem_size = qcom_mdt_get_size(fw);
 105	if (mem_size < 0) {
 106		ret = mem_size;
 107		goto out;
 108	}
 109
 110	if (mem_size > resource_size(&r)) {
 111		DRM_DEV_ERROR(dev,
 112			"memory region is too small to load the MDT\n");
 113		ret = -E2BIG;
 114		goto out;
 115	}
 116
 117	/* Allocate memory for the firmware image */
 118	mem_region = memremap(mem_phys, mem_size,  MEMREMAP_WC);
 119	if (!mem_region) {
 120		ret = -ENOMEM;
 121		goto out;
 122	}
 123
 124	/*
 125	 * Load the rest of the MDT
 126	 *
 127	 * Note that we could be dealing with two different paths, since
 128	 * with upstream linux-firmware it would be in a qcom/ subdir..
 129	 * adreno_request_fw() handles this, but qcom_mdt_load() does
 130	 * not.  But since we've already gotten through adreno_request_fw()
 131	 * we know which of the two cases it is:
 132	 */
 133	if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
 134		ret = qcom_mdt_load(dev, fw, fwname, pasid,
 135				mem_region, mem_phys, mem_size, NULL);
 136	} else {
 137		char *newname;
 138
 139		newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 140
 141		ret = qcom_mdt_load(dev, fw, newname, pasid,
 142				mem_region, mem_phys, mem_size, NULL);
 143		kfree(newname);
 144	}
 145	if (ret)
 146		goto out;
 147
 148	/* Send the image to the secure world */
 149	ret = qcom_scm_pas_auth_and_reset(pasid);
 150
 151	/*
 152	 * If the scm call returns -EOPNOTSUPP we assume that this target
 153	 * doesn't need/support the zap shader so quietly fail
 154	 */
 155	if (ret == -EOPNOTSUPP)
 156		zap_available = false;
 157	else if (ret)
 158		DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
 159
 160out:
 161	if (mem_region)
 162		memunmap(mem_region);
 163
 164	release_firmware(fw);
 165
 166	return ret;
 167}
 168
 169int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
 170{
 171	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 172	struct platform_device *pdev = gpu->pdev;
 173
 174	/* Short cut if we determine the zap shader isn't available/needed */
 175	if (!zap_available)
 176		return -ENODEV;
 177
 178	/* We need SCM to be able to load the firmware */
 179	if (!qcom_scm_is_available()) {
 180		DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
 181		return -EPROBE_DEFER;
 182	}
 183
 184	return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
 185}
 186
 187struct drm_gpuvm *
 188adreno_create_vm(struct msm_gpu *gpu,
 189		 struct platform_device *pdev)
 190{
 191	return adreno_iommu_create_vm(gpu, pdev, 0);
 192}
 193
 194struct drm_gpuvm *
 195adreno_iommu_create_vm(struct msm_gpu *gpu,
 196		       struct platform_device *pdev,
 197		       unsigned long quirks)
 198{
 199	struct iommu_domain_geometry *geometry;
 200	struct msm_mmu *mmu;
 201	struct drm_gpuvm *vm;
 202	u64 start, size;
 203
 204	mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks);
 205	if (IS_ERR(mmu))
 206		return ERR_CAST(mmu);
 207
 208	geometry = msm_iommu_get_geometry(mmu);
 209	if (IS_ERR(geometry))
 210		return ERR_CAST(geometry);
 211
 212	/*
 213	 * Use the aperture start or SZ_16M, whichever is greater. This will
 214	 * ensure that we align with the allocated pagetable range while still
 215	 * allowing room in the lower 32 bits for GMEM and whatnot
 216	 */
 217	start = max_t(u64, SZ_16M, geometry->aperture_start);
 218	size = geometry->aperture_end - start + 1;
 219
 220	vm = msm_gem_vm_create(gpu->dev, mmu, "gpu", start & GENMASK_ULL(48, 0),
 221			       size, true);
 222
 223	if (IS_ERR(vm) && !IS_ERR(mmu))
 224		mmu->funcs->destroy(mmu);
 225
 226	return vm;
 227}
 228
 229u64 adreno_private_vm_size(struct msm_gpu *gpu)
 230{
 231	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 232	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
 233	const struct io_pgtable_cfg *ttbr1_cfg;
 234
 235	if (address_space_size)
 236		return address_space_size;
 237
 238	if (adreno_gpu->info->quirks & ADRENO_QUIRK_4GB_VA)
 239		return SZ_4G;
 240
 241	if (!adreno_smmu || !adreno_smmu->get_ttbr1_cfg)
 242		return SZ_4G;
 243
 244	ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
 245
 246	/*
 247	 * Userspace VM is actually using TTBR0, but both are the same size,
 248	 * with b48 (sign bit) selecting which TTBRn to use.  So if IAS is
 249	 * 48, the total (kernel+user) address space size is effectively
 250	 * 49 bits.  But what userspace is control of is the lower 48.
 251	 */
 252	return BIT(ttbr1_cfg->ias) - ADRENO_VM_START;
 253}
 254
 255void adreno_check_and_reenable_stall(struct adreno_gpu *adreno_gpu)
 256{
 257	struct msm_gpu *gpu = &adreno_gpu->base;
 258	struct msm_drm_private *priv = gpu->dev->dev_private;
 259	unsigned long flags;
 260
 261	/*
 262	 * Wait until the cooldown period has passed and we would actually
 263	 * collect a crashdump to re-enable stall-on-fault.
 264	 */
 265	spin_lock_irqsave(&priv->fault_stall_lock, flags);
 266	if (!priv->stall_enabled &&
 267			ktime_after(ktime_get(), priv->stall_reenable_time) &&
 268			!READ_ONCE(gpu->crashstate)) {
 269		struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
 270
 271		priv->stall_enabled = true;
 272
 273		mmu->funcs->set_stall(mmu, true);
 274	}
 275	spin_unlock_irqrestore(&priv->fault_stall_lock, flags);
 276}
 277
 278#define ARM_SMMU_FSR_TF                 BIT(1)
 279#define ARM_SMMU_FSR_PF			BIT(3)
 280#define ARM_SMMU_FSR_EF			BIT(4)
 281#define ARM_SMMU_FSR_SS			BIT(30)
 282
 283int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
 284			 struct adreno_smmu_fault_info *info, const char *block,
 285			 u32 scratch[4])
 286{
 287	struct adreno_gpu *adreno_gpu = container_of(gpu, struct adreno_gpu, base);
 288	struct msm_drm_private *priv = gpu->dev->dev_private;
 289	struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
 290	const char *type = "UNKNOWN";
 291	bool do_devcoredump = info && (info->fsr & ARM_SMMU_FSR_SS) &&
 292		!READ_ONCE(gpu->crashstate);
 293	unsigned long irq_flags;
 294
 295	/*
 296	 * In case there is a subsequent storm of pagefaults, disable
 297	 * stall-on-fault for at least half a second.
 298	 */
 299	spin_lock_irqsave(&priv->fault_stall_lock, irq_flags);
 300	if (priv->stall_enabled) {
 301		priv->stall_enabled = false;
 302
 303		mmu->funcs->set_stall(mmu, false);
 304	}
 305
 306	priv->stall_reenable_time = ktime_add_ms(ktime_get(), 500);
 307	spin_unlock_irqrestore(&priv->fault_stall_lock, irq_flags);
 308
 309	/*
 310	 * Print a default message if we couldn't get the data from the
 311	 * adreno-smmu-priv
 312	 */
 313	if (!info) {
 314		pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
 315			iova, flags,
 316			scratch[0], scratch[1], scratch[2], scratch[3]);
 317
 318		return 0;
 319	}
 320
 321	if (info->fsr & ARM_SMMU_FSR_TF)
 322		type = "TRANSLATION";
 323	else if (info->fsr & ARM_SMMU_FSR_PF)
 324		type = "PERMISSION";
 325	else if (info->fsr & ARM_SMMU_FSR_EF)
 326		type = "EXTERNAL";
 327
 328	pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
 329			info->ttbr0, iova,
 330			flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
 331			type, block,
 332			scratch[0], scratch[1], scratch[2], scratch[3]);
 333
 334	if (do_devcoredump) {
 335		struct msm_gpu_fault_info fault_info = {};
 336
 337		/* Turn off the hangcheck timer to keep it from bothering us */
 338		timer_delete(&gpu->hangcheck_timer);
 339
 340		/* Let any concurrent GMU transactions know that the MMU may be
 341		 * blocked for a while and they should wait on us.
 342		 */
 343		reinit_completion(&adreno_gpu->fault_coredump_done);
 344
 345		fault_info.ttbr0 = info->ttbr0;
 346		fault_info.iova  = iova;
 347		fault_info.flags = flags;
 348		fault_info.type  = type;
 349		fault_info.block = block;
 350
 351		msm_gpu_fault_crashstate_capture(gpu, &fault_info);
 352
 353		complete_all(&adreno_gpu->fault_coredump_done);
 354	}
 355
 356	return 0;
 357}
 358
 359int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
 360		     uint32_t param, uint64_t *value, uint32_t *len)
 361{
 362	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 363	struct drm_device *drm = gpu->dev;
 364	/* Note ctx can be NULL when called from rd_open(): */
 365	struct drm_gpuvm *vm = ctx ? msm_context_vm(drm, ctx) : NULL;
 366
 367	/* No pointer params yet */
 368	if (*len != 0)
 369		return UERR(EINVAL, drm, "invalid len");
 370
 371	switch (param) {
 372	case MSM_PARAM_GPU_ID:
 373		*value = adreno_gpu->info->revn;
 374		return 0;
 375	case MSM_PARAM_GMEM_SIZE:
 376		*value = adreno_gpu->info->gmem;
 377		return 0;
 378	case MSM_PARAM_GMEM_BASE:
 379		if (adreno_gpu->info->family >= ADRENO_6XX_GEN4)
 380			*value = 0;
 381		else
 382			*value = 0x100000;
 383		return 0;
 384	case MSM_PARAM_CHIP_ID:
 385		*value = adreno_gpu->chip_id;
 386		if (!adreno_gpu->info->revn)
 387			*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
 388		return 0;
 389	case MSM_PARAM_MAX_FREQ:
 390		*value = adreno_gpu->base.fast_rate;
 391		return 0;
 392	case MSM_PARAM_TIMESTAMP:
 393		if (adreno_gpu->funcs->get_timestamp) {
 394			int ret;
 395
 396			pm_runtime_get_sync(&gpu->pdev->dev);
 397			ret = adreno_gpu->funcs->get_timestamp(gpu, value);
 398			pm_runtime_put_autosuspend(&gpu->pdev->dev);
 399
 400			return ret;
 401		}
 402		return -EINVAL;
 403	case MSM_PARAM_PRIORITIES:
 404		*value = gpu->nr_rings * NR_SCHED_PRIORITIES;
 405		return 0;
 406	case MSM_PARAM_PP_PGTABLE:
 407		*value = 0;
 408		return 0;
 409	case MSM_PARAM_FAULTS:
 410		if (vm)
 411			*value = gpu->global_faults + to_msm_vm(vm)->faults;
 412		else
 413			*value = gpu->global_faults;
 414		return 0;
 415	case MSM_PARAM_SUSPENDS:
 416		*value = gpu->suspend_count;
 417		return 0;
 418	case MSM_PARAM_VA_START:
 419		if (vm == gpu->vm)
 420			return UERR(EINVAL, drm, "requires per-process pgtables");
 421		*value = vm->mm_start;
 422		return 0;
 423	case MSM_PARAM_VA_SIZE:
 424		if (vm == gpu->vm)
 425			return UERR(EINVAL, drm, "requires per-process pgtables");
 426		*value = vm->mm_range;
 427		return 0;
 428	case MSM_PARAM_HIGHEST_BANK_BIT:
 429		*value = adreno_gpu->ubwc_config->highest_bank_bit;
 430		return 0;
 431	case MSM_PARAM_RAYTRACING:
 432		*value = adreno_gpu->has_ray_tracing;
 433		return 0;
 434	case MSM_PARAM_UBWC_SWIZZLE:
 435		*value = adreno_gpu->ubwc_config->ubwc_swizzle;
 436		return 0;
 437	case MSM_PARAM_MACROTILE_MODE:
 438		*value = adreno_gpu->ubwc_config->macrotile_mode;
 439		return 0;
 440	case MSM_PARAM_UCHE_TRAP_BASE:
 441		*value = adreno_gpu->uche_trap_base;
 442		return 0;
 443	case MSM_PARAM_HAS_PRR:
 444		*value = adreno_smmu_has_prr(gpu);
 445		return 0;
 446	default:
 447		return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
 448	}
 449}
 450
 451int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx,
 452		     uint32_t param, uint64_t value, uint32_t len)
 453{
 454	struct drm_device *drm = gpu->dev;
 455
 456	switch (param) {
 457	case MSM_PARAM_COMM:
 458	case MSM_PARAM_CMDLINE:
 459		/* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
 460		 * that should be a reasonable upper bound
 461		 */
 462		if (len > PAGE_SIZE)
 463			return UERR(EINVAL, drm, "invalid len");
 464		break;
 465	default:
 466		if (len != 0)
 467			return UERR(EINVAL, drm, "invalid len");
 468	}
 469
 470	switch (param) {
 471	case MSM_PARAM_COMM:
 472	case MSM_PARAM_CMDLINE: {
 473		char *str, **paramp;
 474
 475		str = memdup_user_nul(u64_to_user_ptr(value), len);
 476		if (IS_ERR(str))
 477			return PTR_ERR(str);
 478
 479		mutex_lock(&gpu->lock);
 480
 481		if (param == MSM_PARAM_COMM) {
 482			paramp = &ctx->comm;
 483		} else {
 484			paramp = &ctx->cmdline;
 485		}
 486
 487		kfree(*paramp);
 488		*paramp = str;
 489
 490		mutex_unlock(&gpu->lock);
 491
 492		return 0;
 493	}
 494	case MSM_PARAM_SYSPROF:
 495		if (!capable(CAP_SYS_ADMIN))
 496			return UERR(EPERM, drm, "invalid permissions");
 497		return msm_context_set_sysprof(ctx, gpu, value);
 498	case MSM_PARAM_EN_VM_BIND:
 499		/* We can only support VM_BIND with per-process pgtables: */
 500		if (ctx->vm == gpu->vm)
 501			return UERR(EINVAL, drm, "requires per-process pgtables");
 502
 503		/*
 504		 * We can only swtich to VM_BIND mode if the VM has not yet
 505		 * been created:
 506		 */
 507		if (ctx->vm)
 508			return UERR(EBUSY, drm, "VM already created");
 509
 510		ctx->userspace_managed_vm = value;
 511
 512		return 0;
 513	default:
 514		return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
 515	}
 516}
 517
 518const struct firmware *
 519adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
 520{
 521	struct drm_device *drm = adreno_gpu->base.dev;
 522	const struct firmware *fw = NULL;
 523	char *newname;
 524	int ret;
 525
 526	newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
 527	if (!newname)
 528		return ERR_PTR(-ENOMEM);
 529
 530	/*
 531	 * Try first to load from qcom/$fwfile using a direct load (to avoid
 532	 * a potential timeout waiting for usermode helper)
 533	 */
 534	if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 535	    (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
 536
 537		ret = request_firmware_direct(&fw, newname, drm->dev);
 538		if (!ret) {
 539			DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
 540				newname);
 541			adreno_gpu->fwloc = FW_LOCATION_NEW;
 542			goto out;
 543		} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 544			DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 545				newname, ret);
 546			fw = ERR_PTR(ret);
 547			goto out;
 548		}
 549	}
 550
 551	/*
 552	 * Then try the legacy location without qcom/ prefix
 553	 */
 554	if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 555	    (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
 556
 557		ret = request_firmware_direct(&fw, fwname, drm->dev);
 558		if (!ret) {
 559			DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
 560				fwname);
 561			adreno_gpu->fwloc = FW_LOCATION_LEGACY;
 562			goto out;
 563		} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 564			DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 565				fwname, ret);
 566			fw = ERR_PTR(ret);
 567			goto out;
 568		}
 569	}
 570
 571	/*
 572	 * Finally fall back to request_firmware() for cases where the
 573	 * usermode helper is needed (I think mainly android)
 574	 */
 575	if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
 576	    (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
 577
 578		ret = request_firmware(&fw, newname, drm->dev);
 579		if (!ret) {
 580			DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
 581				newname);
 582			adreno_gpu->fwloc = FW_LOCATION_HELPER;
 583			goto out;
 584		} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
 585			DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
 586				newname, ret);
 587			fw = ERR_PTR(ret);
 588			goto out;
 589		}
 590	}
 591
 592	DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
 593	fw = ERR_PTR(-ENOENT);
 594out:
 595	kfree(newname);
 596	return fw;
 597}
 598
 599int adreno_load_fw(struct adreno_gpu *adreno_gpu)
 600{
 601	int i;
 602
 603	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
 604		const struct firmware *fw;
 605
 606		if (!adreno_gpu->info->fw[i])
 607			continue;
 608
 609		/* Skip loading GMU firmware with GMU Wrapper */
 610		if (adreno_has_gmu_wrapper(adreno_gpu) && i == ADRENO_FW_GMU)
 611			continue;
 612
 613		/* Skip if the firmware has already been loaded */
 614		if (adreno_gpu->fw[i])
 615			continue;
 616
 617		fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
 618		if (IS_ERR(fw))
 619			return PTR_ERR(fw);
 620
 621		adreno_gpu->fw[i] = fw;
 622	}
 623
 624	return 0;
 625}
 626
 627struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
 628		const struct firmware *fw, u64 *iova)
 629{
 630	struct drm_gem_object *bo;
 631	void *ptr;
 632
 633	ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
 634		MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->vm, &bo, iova);
 635
 636	if (IS_ERR(ptr))
 637		return ERR_CAST(ptr);
 638
 639	memcpy(ptr, &fw->data[4], fw->size - 4);
 640
 641	msm_gem_put_vaddr(bo);
 642
 643	return bo;
 644}
 645
 646int adreno_hw_init(struct msm_gpu *gpu)
 647{
 648	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 649	int ret;
 650
 651	VERB("%s", gpu->name);
 652
 653	if (adreno_gpu->info->family >= ADRENO_6XX_GEN1 &&
 654	    qcom_scm_set_gpu_smmu_aperture_is_available()) {
 655		/* We currently always use context bank 0, so hard code this */
 656		ret = qcom_scm_set_gpu_smmu_aperture(0);
 657		if (ret)
 658			DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret);
 659	}
 660
 661	for (int i = 0; i < gpu->nr_rings; i++) {
 662		struct msm_ringbuffer *ring = gpu->rb[i];
 663
 664		if (!ring)
 665			continue;
 666
 667		ring->cur = ring->start;
 668		ring->next = ring->start;
 669		ring->memptrs->rptr = 0;
 670		ring->memptrs->bv_fence = ring->fctx->completed_fence;
 671
 672		/* Detect and clean up an impossible fence, ie. if GPU managed
 673		 * to scribble something invalid, we don't want that to confuse
 674		 * us into mistakingly believing that submits have completed.
 675		 */
 676		if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
 677			ring->memptrs->fence = ring->fctx->last_fence;
 678		}
 679	}
 680
 681	return 0;
 682}
 683
 684/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
 685static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
 686		struct msm_ringbuffer *ring)
 687{
 688	struct msm_gpu *gpu = &adreno_gpu->base;
 689
 690	return gpu->funcs->get_rptr(gpu, ring);
 691}
 692
 693struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
 694{
 695	return gpu->rb[0];
 696}
 697
 698void adreno_recover(struct msm_gpu *gpu)
 699{
 700	struct drm_device *dev = gpu->dev;
 701	int ret;
 702
 703	// XXX pm-runtime??  we *need* the device to be off after this
 704	// so maybe continuing to call ->pm_suspend/resume() is better?
 705
 706	gpu->funcs->pm_suspend(gpu);
 707	gpu->funcs->pm_resume(gpu);
 708
 709	ret = msm_gpu_hw_init(gpu);
 710	if (ret) {
 711		DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
 712		/* hmm, oh well? */
 713	}
 714}
 715
 716void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
 717{
 718	uint32_t wptr;
 719
 720	/* Copy the shadow to the actual register */
 721	ring->cur = ring->next;
 722
 723	/*
 724	 * Mask wptr value that we calculate to fit in the HW range. This is
 725	 * to account for the possibility that the last command fit exactly into
 726	 * the ringbuffer and rb->next hasn't wrapped to zero yet
 727	 */
 728	wptr = get_wptr(ring);
 729
 730	/* ensure writes to ringbuffer have hit system memory: */
 731	mb();
 732
 733	gpu_write(gpu, reg, wptr);
 734}
 735
 736bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 737{
 738	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 739	uint32_t wptr = get_wptr(ring);
 740
 741	/* wait for CP to drain ringbuffer: */
 742	if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
 743		return true;
 744
 745	/* TODO maybe we need to reset GPU here to recover from hang? */
 746	DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
 747		gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
 748
 749	return false;
 750}
 751
 752int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
 753{
 754	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 755	int i, count = 0;
 756
 757	WARN_ON(!mutex_is_locked(&gpu->lock));
 758
 759	kref_init(&state->ref);
 760
 761	ktime_get_real_ts64(&state->time);
 762
 763	for (i = 0; i < gpu->nr_rings; i++) {
 764		int size = 0, j;
 765
 766		state->ring[i].fence = gpu->rb[i]->memptrs->fence;
 767		state->ring[i].iova = gpu->rb[i]->iova;
 768		state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
 769		state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
 770		state->ring[i].wptr = get_wptr(gpu->rb[i]);
 771
 772		/* Copy at least 'wptr' dwords of the data */
 773		size = state->ring[i].wptr;
 774
 775		/* After wptr find the last non zero dword to save space */
 776		for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
 777			if (gpu->rb[i]->start[j])
 778				size = j + 1;
 779
 780		if (size) {
 781			state->ring[i].data = kvmemdup(gpu->rb[i]->start, size << 2, GFP_KERNEL);
 782			if (state->ring[i].data)
 783				state->ring[i].data_size = size << 2;
 784		}
 785	}
 786
 787	/* Some targets prefer to collect their own registers */
 788	if (!adreno_gpu->registers)
 789		return 0;
 790
 791	/* Count the number of registers */
 792	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
 793		count += adreno_gpu->registers[i + 1] -
 794			adreno_gpu->registers[i] + 1;
 795
 796	state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
 797	if (state->registers) {
 798		int pos = 0;
 799
 800		for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
 801			u32 start = adreno_gpu->registers[i];
 802			u32 end   = adreno_gpu->registers[i + 1];
 803			u32 addr;
 804
 805			for (addr = start; addr <= end; addr++) {
 806				state->registers[pos++] = addr;
 807				state->registers[pos++] = gpu_read(gpu, addr);
 808			}
 809		}
 810
 811		state->nr_registers = count;
 812	}
 813
 814	return 0;
 815}
 816
 817void adreno_gpu_state_destroy(struct msm_gpu_state *state)
 818{
 819	int i;
 820
 821	for (i = 0; i < ARRAY_SIZE(state->ring); i++)
 822		kvfree(state->ring[i].data);
 823
 824	for (i = 0; state->bos && i < state->nr_bos; i++)
 825		kvfree(state->bos[i].data);
 826
 827	kfree(state->vm_logs);
 828	kfree(state->bos);
 829	kfree(state->comm);
 830	kfree(state->cmd);
 831	kfree(state->registers);
 832}
 833
 834static void adreno_gpu_state_kref_destroy(struct kref *kref)
 835{
 836	struct msm_gpu_state *state = container_of(kref,
 837		struct msm_gpu_state, ref);
 838
 839	adreno_gpu_state_destroy(state);
 840	kfree(state);
 841}
 842
 843int adreno_gpu_state_put(struct msm_gpu_state *state)
 844{
 845	if (IS_ERR_OR_NULL(state))
 846		return 1;
 847
 848	return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
 849}
 850
 851#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
 852
 853static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
 854{
 855	void *buf;
 856	size_t buf_itr = 0, buffer_size;
 857	char out[ASCII85_BUFSZ];
 858	long l;
 859	int i;
 860
 861	if (!src || !len)
 862		return NULL;
 863
 864	l = ascii85_encode_len(len);
 865
 866	/*
 867	 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
 868	 * account for the worst case of 5 bytes per dword plus the 1 for '\0'
 869	 */
 870	buffer_size = (l * 5) + 1;
 871
 872	buf = kvmalloc(buffer_size, GFP_KERNEL);
 873	if (!buf)
 874		return NULL;
 875
 876	for (i = 0; i < l; i++)
 877		buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
 878				ascii85_encode(src[i], out));
 879
 880	return buf;
 881}
 882
 883/* len is expected to be in bytes
 884 *
 885 * WARNING: *ptr should be allocated with kvmalloc or friends.  It can be free'd
 886 * with kvfree() and replaced with a newly kvmalloc'd buffer on the first call
 887 * when the unencoded raw data is encoded
 888 */
 889void adreno_show_object(struct drm_printer *p, void **ptr, int len,
 890		bool *encoded)
 891{
 892	if (!*ptr || !len)
 893		return;
 894
 895	if (!*encoded) {
 896		long datalen, i;
 897		u32 *buf = *ptr;
 898
 899		/*
 900		 * Only dump the non-zero part of the buffer - rarely will
 901		 * any data completely fill the entire allocated size of
 902		 * the buffer.
 903		 */
 904		for (datalen = 0, i = 0; i < len >> 2; i++)
 905			if (buf[i])
 906				datalen = ((i + 1) << 2);
 907
 908		/*
 909		 * If we reach here, then the originally captured binary buffer
 910		 * will be replaced with the ascii85 encoded string
 911		 */
 912		*ptr = adreno_gpu_ascii85_encode(buf, datalen);
 913
 914		kvfree(buf);
 915
 916		*encoded = true;
 917	}
 918
 919	if (!*ptr)
 920		return;
 921
 922	drm_puts(p, "    data: !!ascii85 |\n");
 923	drm_puts(p, "     ");
 924
 925	drm_puts(p, *ptr);
 926
 927	drm_puts(p, "\n");
 928}
 929
 930void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
 931		struct drm_printer *p)
 932{
 933	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 934	int i;
 935
 936	if (IS_ERR_OR_NULL(state))
 937		return;
 938
 939	drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n",
 940			adreno_gpu->info->revn,
 941			ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
 942	/*
 943	 * If this is state collected due to iova fault, so fault related info
 944	 *
 945	 * TTBR0 would not be zero, so this is a good way to distinguish
 946	 */
 947	if (state->fault_info.ttbr0) {
 948		const struct msm_gpu_fault_info *info = &state->fault_info;
 949
 950		drm_puts(p, "fault-info:\n");
 951		drm_printf(p, "  - ttbr0=%.16llx\n", info->ttbr0);
 952		drm_printf(p, "  - iova=%.16lx\n", info->iova);
 953		drm_printf(p, "  - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
 954		drm_printf(p, "  - type=%s\n", info->type);
 955		drm_printf(p, "  - source=%s\n", info->block);
 956
 957		/* Information extracted from what we think are the current
 958		 * pgtables.  Hopefully the TTBR0 matches what we've extracted
 959		 * from the SMMU registers in smmu_info!
 960		 */
 961		drm_puts(p, "pgtable-fault-info:\n");
 962		drm_printf(p, "  - ttbr0: %.16llx\n", (u64)info->pgtbl_ttbr0);
 963		drm_printf(p, "  - asid: %d\n", info->asid);
 964		drm_printf(p, "  - ptes: %.16llx %.16llx %.16llx %.16llx\n",
 965			   info->ptes[0], info->ptes[1], info->ptes[2], info->ptes[3]);
 966	}
 967
 968	if (state->vm_logs) {
 969		drm_puts(p, "vm-log:\n");
 970		for (i = 0; i < state->nr_vm_logs; i++) {
 971			struct msm_gem_vm_log_entry *e = &state->vm_logs[i];
 972			drm_printf(p, "  - %s:%d: 0x%016llx-0x%016llx\n",
 973				   e->op, e->queue_id, e->iova,
 974				   e->iova + e->range);
 975		}
 976	}
 977
 978	drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
 979
 980	drm_puts(p, "ringbuffer:\n");
 981
 982	for (i = 0; i < gpu->nr_rings; i++) {
 983		drm_printf(p, "  - id: %d\n", i);
 984		drm_printf(p, "    iova: 0x%016llx\n", state->ring[i].iova);
 985		drm_printf(p, "    last-fence: %u\n", state->ring[i].seqno);
 986		drm_printf(p, "    retired-fence: %u\n", state->ring[i].fence);
 987		drm_printf(p, "    rptr: %u\n", state->ring[i].rptr);
 988		drm_printf(p, "    wptr: %u\n", state->ring[i].wptr);
 989		drm_printf(p, "    size: %u\n", MSM_GPU_RINGBUFFER_SZ);
 990
 991		adreno_show_object(p, &state->ring[i].data,
 992			state->ring[i].data_size, &state->ring[i].encoded);
 993	}
 994
 995	if (state->bos) {
 996		drm_puts(p, "bos:\n");
 997
 998		for (i = 0; i < state->nr_bos; i++) {
 999			drm_printf(p, "  - iova: 0x%016llx\n",
1000				state->bos[i].iova);
1001			drm_printf(p, "    size: %zd\n", state->bos[i].size);
1002			drm_printf(p, "    flags: 0x%x\n", state->bos[i].flags);
1003			drm_printf(p, "    name: %-32s\n", state->bos[i].name);
1004
1005			adreno_show_object(p, &state->bos[i].data,
1006				state->bos[i].size, &state->bos[i].encoded);
1007		}
1008	}
1009
1010	if (state->nr_registers) {
1011		drm_puts(p, "registers:\n");
1012
1013		for (i = 0; i < state->nr_registers; i++) {
1014			drm_printf(p, "  - { offset: 0x%04x, value: 0x%08x }\n",
1015				state->registers[i * 2] << 2,
1016				state->registers[(i * 2) + 1]);
1017		}
1018	}
1019}
1020#endif
1021
1022/* Dump common gpu status and scratch registers on any hang, to make
1023 * the hangcheck logs more useful.  The scratch registers seem always
1024 * safe to read when GPU has hung (unlike some other regs, depending
1025 * on how the GPU hung), and they are useful to match up to cmdstream
1026 * dumps when debugging hangs:
1027 */
1028void adreno_dump_info(struct msm_gpu *gpu)
1029{
1030	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1031	int i;
1032
1033	printk("revision: %u (%"ADRENO_CHIPID_FMT")\n",
1034			adreno_gpu->info->revn,
1035			ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
1036
1037	for (i = 0; i < gpu->nr_rings; i++) {
1038		struct msm_ringbuffer *ring = gpu->rb[i];
1039
1040		printk("rb %d: fence:    %d/%d\n", i,
1041			ring->memptrs->fence,
1042			ring->fctx->last_fence);
1043
1044		printk("rptr:     %d\n", get_rptr(adreno_gpu, ring));
1045		printk("rb wptr:  %d\n", get_wptr(ring));
1046	}
1047}
1048
1049/* would be nice to not have to duplicate the _show() stuff with printk(): */
1050void adreno_dump(struct msm_gpu *gpu)
1051{
1052	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1053	int i;
1054
1055	if (!adreno_gpu->registers)
1056		return;
1057
1058	/* dump these out in a form that can be parsed by demsm: */
1059	printk("IO:region %s 00000000 00020000\n", gpu->name);
1060	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
1061		uint32_t start = adreno_gpu->registers[i];
1062		uint32_t end   = adreno_gpu->registers[i+1];
1063		uint32_t addr;
1064
1065		for (addr = start; addr <= end; addr++) {
1066			uint32_t val = gpu_read(gpu, addr);
1067			printk("IO:R %08x %08x\n", addr<<2, val);
1068		}
1069	}
1070}
1071
1072static uint32_t ring_freewords(struct msm_ringbuffer *ring)
1073{
1074	struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
1075	uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
1076	/* Use ring->next to calculate free size */
1077	uint32_t wptr = ring->next - ring->start;
1078	uint32_t rptr = get_rptr(adreno_gpu, ring);
1079	return (rptr + (size - 1) - wptr) % size;
1080}
1081
1082void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
1083{
1084	if (spin_until(ring_freewords(ring) >= ndwords))
1085		DRM_DEV_ERROR(ring->gpu->dev->dev,
1086			"timeout waiting for space in ringbuffer %d\n",
1087			ring->id);
1088}
1089
1090static int adreno_get_pwrlevels(struct device *dev,
1091		struct msm_gpu *gpu)
1092{
1093	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1094	unsigned long freq = ULONG_MAX;
1095	struct dev_pm_opp *opp;
1096	int ret;
1097
1098	gpu->fast_rate = 0;
1099
1100	/* devm_pm_opp_of_add_table may error out but will still create an OPP table */
1101	ret = devm_pm_opp_of_add_table(dev);
1102	if (ret == -ENODEV) {
1103		/* Special cases for ancient hw with ancient DT bindings */
1104		if (adreno_is_a2xx(adreno_gpu)) {
1105			dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n");
1106			dev_pm_opp_add(dev, 200000000, 0);
1107		} else if (adreno_is_a320(adreno_gpu)) {
1108			dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n");
1109			dev_pm_opp_add(dev, 450000000, 0);
1110		} else {
1111			DRM_DEV_ERROR(dev, "Unable to find the OPP table\n");
1112			return -ENODEV;
1113		}
1114	} else if (ret) {
1115		DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
1116		return ret;
1117	}
1118
1119	/* Find the fastest defined rate */
1120	opp = dev_pm_opp_find_freq_floor(dev, &freq);
1121	if (IS_ERR(opp))
1122		return PTR_ERR(opp);
1123
1124	gpu->fast_rate = freq;
1125	dev_pm_opp_put(opp);
1126
1127	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
1128
1129	return 0;
1130}
1131
1132int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
1133			  struct adreno_ocmem *adreno_ocmem)
1134{
1135	struct ocmem_buf *ocmem_hdl;
1136	struct ocmem *ocmem;
1137
1138	ocmem = of_get_ocmem(dev);
1139	if (IS_ERR(ocmem)) {
1140		if (PTR_ERR(ocmem) == -ENODEV) {
1141			/*
1142			 * Return success since either the ocmem property was
1143			 * not specified in device tree, or ocmem support is
1144			 * not compiled into the kernel.
1145			 */
1146			return 0;
1147		}
1148
1149		return PTR_ERR(ocmem);
1150	}
1151
1152	ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem);
1153	if (IS_ERR(ocmem_hdl))
1154		return PTR_ERR(ocmem_hdl);
1155
1156	adreno_ocmem->ocmem = ocmem;
1157	adreno_ocmem->base = ocmem_hdl->addr;
1158	adreno_ocmem->hdl = ocmem_hdl;
1159
1160	if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem))
1161		return -ENOMEM;
1162
1163	return 0;
1164}
1165
1166void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
1167{
1168	if (adreno_ocmem && adreno_ocmem->base)
1169		ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1170			   adreno_ocmem->hdl);
1171}
1172
1173int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1174{
1175	return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1176}
1177
1178int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1179		struct adreno_gpu *adreno_gpu,
1180		const struct adreno_gpu_funcs *funcs, int nr_rings)
1181{
1182	struct device *dev = &pdev->dev;
1183	struct adreno_platform_config *config = dev->platform_data;
1184	struct msm_gpu_config adreno_gpu_config  = { 0 };
1185	struct msm_gpu *gpu = &adreno_gpu->base;
1186	const char *gpu_name;
1187	u32 speedbin;
1188	int ret;
1189
1190	adreno_gpu->funcs = funcs;
1191	adreno_gpu->info = config->info;
1192	adreno_gpu->chip_id = config->chip_id;
1193
1194	gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1;
1195	gpu->pdev = pdev;
1196
1197	/* Only handle the core clock when GMU is not in use (or is absent). */
1198	if (adreno_has_gmu_wrapper(adreno_gpu) ||
1199	    adreno_has_rgmu(adreno_gpu) ||
1200	    adreno_gpu->info->family < ADRENO_6XX_GEN1) {
1201		/*
1202		 * This can only be done before devm_pm_opp_of_add_table(), or
1203		 * dev_pm_opp_set_config() will WARN_ON()
1204		 */
1205		if (IS_ERR(devm_clk_get(dev, "core"))) {
1206			/*
1207			 * If "core" is absent, go for the legacy clock name.
1208			 * If we got this far in probing, it's a given one of
1209			 * them exists.
1210			 */
1211			devm_pm_opp_set_clkname(dev, "core_clk");
1212		} else
1213			devm_pm_opp_set_clkname(dev, "core");
1214	}
1215
1216	if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1217		speedbin = 0xffff;
1218	adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1219
1220	gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
1221			ADRENO_CHIPID_ARGS(config->chip_id));
1222	if (!gpu_name)
1223		return -ENOMEM;
1224
1225	adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1226
1227	adreno_gpu_config.nr_rings = nr_rings;
1228
1229	ret = adreno_get_pwrlevels(dev, gpu);
1230	if (ret)
1231		return ret;
1232
1233	init_completion(&adreno_gpu->fault_coredump_done);
1234	complete_all(&adreno_gpu->fault_coredump_done);
1235
1236	pm_runtime_set_autosuspend_delay(dev,
1237		adreno_gpu->info->inactive_period);
1238	pm_runtime_use_autosuspend(dev);
1239
1240	return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1241			gpu_name, &adreno_gpu_config);
1242}
1243
1244void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1245{
1246	struct msm_gpu *gpu = &adreno_gpu->base;
1247	struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL;
1248	unsigned int i;
1249
1250	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1251		release_firmware(adreno_gpu->fw[i]);
1252
1253	if (priv && pm_runtime_enabled(&priv->gpu_pdev->dev))
1254		pm_runtime_disable(&priv->gpu_pdev->dev);
1255
1256	msm_gpu_cleanup(&adreno_gpu->base);
1257}