FILE
a8xx_gpu.c
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linux-6.19.14/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ 3 4 5#include "msm_gem.h" 6#include "msm_mmu.h" 7#include "msm_gpu_trace.h" 8#include "a6xx_gpu.h" 9#include "a6xx_gmu.xml.h" 10 11#include <linux/bitfield.h> 12#include <linux/devfreq.h> 13#include <linux/firmware/qcom/qcom_scm.h> 14#include <linux/pm_domain.h> 15#include <linux/soc/qcom/llcc-qcom.h> 16 17#define GPU_PAS_ID 13 18 19static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) 20{ 21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 23 u32 val; 24 25 val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); 26 27 if (a6xx_gpu->cached_aperture == val) 28 return; 29 30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); 31 32 a6xx_gpu->cached_aperture = val; 33} 34 35static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) 36{ 37 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 38 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 39 40 spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); 41 42 a8xx_aperture_slice_set(gpu, pipe, 0); 43} 44 45static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) 46{ 47 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 48 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 49 50 spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); 51} 52 53static void a8xx_aperture_clear(struct msm_gpu *gpu) 54{ 55 unsigned long flags; 56 57 a8xx_aperture_acquire(gpu, PIPE_NONE, &flags); 58 a8xx_aperture_release(gpu, flags); 59} 60 61static void a8xx_write_pipe(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 offset, u32 data) 62{ 63 unsigned long flags; 64 65 a8xx_aperture_acquire(gpu, pipe, &flags); 66 gpu_write(gpu, offset, data); 67 a8xx_aperture_release(gpu, flags); 68} 69 70static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice, u32 offset) 71{ 72 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 73 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 74 unsigned long flags; 75 u32 val; 76 77 spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); 78 a8xx_aperture_slice_set(gpu, pipe, slice); 79 val = gpu_read(gpu, offset); 80 spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); 81 82 return val; 83} 84 85void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) 86{ 87 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 88 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 89 const struct a6xx_info *info = adreno_gpu->info->a6xx; 90 u32 slice_mask; 91 92 if (adreno_gpu->info->family < ADRENO_8XX_GEN1) 93 return; 94 95 if (a6xx_gpu->slice_mask) 96 return; 97 98 slice_mask = GENMASK(info->max_slices - 1, 0); 99 100 /* GEN1 doesn't support partial slice configurations */ 101 if (adreno_gpu->info->family == ADRENO_8XX_GEN1) { 102 a6xx_gpu->slice_mask = slice_mask; 103 return; 104 } 105 106 slice_mask &= a6xx_llc_read(a6xx_gpu, 107 REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL); 108 109 a6xx_gpu->slice_mask = slice_mask; 110 111 /* Chip ID depends on the number of slices available. So update it */ 112 adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask)); 113} 114 115static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu) 116{ 117 return ffs(a6xx_gpu->slice_mask) - 1; 118} 119 120static inline bool _a8xx_check_idle(struct msm_gpu *gpu) 121{ 122 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 123 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 124 125 /* Check that the GMU is idle */ 126 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) 127 return false; 128 129 /* Check that the CX master is idle */ 130 if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) & 131 ~A8XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 132 return false; 133 134 return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) & 135 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 136} 137 138static bool a8xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 139{ 140 /* wait for CP to drain ringbuffer: */ 141 if (!adreno_idle(gpu, ring)) 142 return false; 143 144 if (spin_until(_a8xx_check_idle(gpu))) { 145 DRM_ERROR( 146 "%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 147 gpu->name, __builtin_return_address(0), 148 gpu_read(gpu, REG_A8XX_RBBM_STATUS), 149 gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS), 150 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 151 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 152 return false; 153 } 154 155 return true; 156} 157 158void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 159{ 160 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 161 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 162 uint32_t wptr; 163 unsigned long flags; 164 165 spin_lock_irqsave(&ring->preempt_lock, flags); 166 167 /* Copy the shadow to the actual register */ 168 ring->cur = ring->next; 169 170 /* Make sure to wrap wptr if we need to */ 171 wptr = get_wptr(ring); 172 173 /* Update HW if this is the current ring and we are not in preempt*/ 174 if (!a6xx_in_preempt(a6xx_gpu)) { 175 if (a6xx_gpu->cur_ring == ring) 176 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 177 else 178 ring->restore_wptr = true; 179 } else { 180 ring->restore_wptr = true; 181 } 182 183 spin_unlock_irqrestore(&ring->preempt_lock, flags); 184} 185 186static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state) 187{ 188 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 189 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 190 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 191 u32 val; 192 193 if (adreno_is_x285(adreno_gpu) && state) 194 gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); 195 196 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 197 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 198 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 199 state ? 0x110111 : 0); 200 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 201 state ? 0x55555 : 0); 202 203 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 204 gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, !!state); 205 206 if (state) { 207 gpu_write(gpu, REG_A8XX_RBBM_CGC_P2S_TRIG_CMD, 1); 208 209 if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_CGC_P2S_STATUS, val, 210 val & A8XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 211 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 212 return; 213 } 214 215 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 216 } else { 217 /* 218 * GMU enables clk gating in GBIF during boot up. So, 219 * override that here when hwcg feature is disabled 220 */ 221 gpu_rmw(gpu, REG_A8XX_GBIF_CX_CONFIG, BIT(0), 0); 222 } 223} 224 225static void a8xx_set_cp_protect(struct msm_gpu *gpu) 226{ 227 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 228 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 229 u32 cntl, final_cfg; 230 unsigned int i; 231 232 cntl = A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_PROT_EN | 233 A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_FAULT_ON_VIOL_EN | 234 A8XX_CP_PROTECT_CNTL_PIPE_LAST_SPAN_INF_RANGE | 235 A8XX_CP_PROTECT_CNTL_PIPE_HALT_SQE_RANGE__MASK; 236 /* 237 * Enable access protection to privileged registers, fault on an access 238 * protect violation and select the last span to protect from the start 239 * address all the way to the end of the register address space 240 */ 241 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); 242 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); 243 244 a8xx_aperture_clear(gpu); 245 246 for (i = 0; i < protect->count; i++) { 247 /* Intentionally skip writing to some registers */ 248 if (protect->regs[i]) { 249 gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); 250 final_cfg = protect->regs[i]; 251 } 252 } 253 254 /* 255 * Last span feature is only supported on PIPE specific register. 256 * So update those here 257 */ 258 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); 259 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); 260 261 a8xx_aperture_clear(gpu); 262} 263 264static void a8xx_set_ubwc_config(struct msm_gpu *gpu) 265{ 266 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 267 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; 268 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); 269 u32 level3_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL3); 270 bool rgba8888_lossless = false, fp16compoptdis = false; 271 bool yuvnotcomptofc = false, min_acc_len_64b = false; 272 bool rgb565_predicator = false, amsbc = false; 273 bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); 274 u32 ubwc_version = cfg->ubwc_enc_version; 275 u32 hbb, hbb_hi, hbb_lo, mode = 1; 276 u8 uavflagprd_inv = 2; 277 278 switch (ubwc_version) { 279 case UBWC_5_0: 280 amsbc = true; 281 rgb565_predicator = true; 282 mode = 4; 283 break; 284 case UBWC_4_0: 285 amsbc = true; 286 rgb565_predicator = true; 287 fp16compoptdis = true; 288 rgba8888_lossless = true; 289 mode = 2; 290 break; 291 case UBWC_3_0: 292 amsbc = true; 293 mode = 1; 294 break; 295 default: 296 dev_err(&gpu->pdev->dev, "Unknown UBWC version: 0x%x\n", ubwc_version); 297 break; 298 } 299 300 /* 301 * We subtract 13 from the highest bank bit (13 is the minimum value 302 * allowed by hw) and write the lowest two bits of the remaining value 303 * as hbb_lo and the one above it as hbb_hi to the hardware. 304 */ 305 WARN_ON(cfg->highest_bank_bit < 13); 306 hbb = cfg->highest_bank_bit - 13; 307 hbb_hi = hbb >> 2; 308 hbb_lo = hbb & 3; 309 310 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_GRAS_NC_MODE_CNTL, 311 hbb << 5 | 312 level3_swizzling_dis << 4 | 313 level2_swizzling_dis << 3); 314 315 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_GRAS_NC_MODE_CNTL, 316 hbb << 5 | 317 level3_swizzling_dis << 4 | 318 level2_swizzling_dis << 3); 319 320 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CCU_NC_MODE_CNTL, 321 yuvnotcomptofc << 6 | 322 level3_swizzling_dis << 5 | 323 level2_swizzling_dis << 4 | 324 hbb_hi << 3 | 325 hbb_lo << 1); 326 327 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_CMP_NC_MODE_CNTL, 328 mode << 15 | 329 yuvnotcomptofc << 6 | 330 rgba8888_lossless << 4 | 331 fp16compoptdis << 3 | 332 rgb565_predicator << 2 | 333 amsbc << 1 | 334 min_acc_len_64b); 335 336 a8xx_aperture_clear(gpu); 337 338 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 339 level3_swizzling_dis << 13 | 340 level2_swizzling_dis << 12 | 341 hbb_hi << 10 | 342 uavflagprd_inv << 4 | 343 min_acc_len_64b << 3 | 344 hbb_lo << 1 | ubwc_mode); 345 346 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 347 level3_swizzling_dis << 7 | 348 level2_swizzling_dis << 6 | 349 hbb_hi << 4 | 350 min_acc_len_64b << 3 | 351 hbb_lo << 1 | ubwc_mode); 352} 353 354static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) 355{ 356 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 357 const struct a6xx_info *info = adreno_gpu->info->a6xx; 358 const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; 359 unsigned int pipe_id, i; 360 unsigned long flags; 361 362 for (pipe_id = PIPE_NONE; pipe_id <= PIPE_DDE_BV; pipe_id++) { 363 /* We don't have support for LPAC yet */ 364 if (pipe_id == PIPE_LPAC) 365 continue; 366 367 a8xx_aperture_acquire(gpu, pipe_id, &flags); 368 369 for (i = 0; regs[i].offset; i++) { 370 if (!(BIT(pipe_id) & regs[i].pipe)) 371 continue; 372 373 if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) 374 *gmem_protect = regs[i].value; 375 376 gpu_write(gpu, regs[i].offset, regs[i].value); 377 } 378 379 a8xx_aperture_release(gpu, flags); 380 } 381 382 a8xx_aperture_clear(gpu); 383} 384 385static int a8xx_cp_init(struct msm_gpu *gpu) 386{ 387 struct msm_ringbuffer *ring = gpu->rb[0]; 388 u32 mask; 389 390 /* Disable concurrent binning before sending CP init */ 391 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 392 OUT_RING(ring, BIT(27)); 393 394 OUT_PKT7(ring, CP_ME_INIT, 4); 395 396 /* Use multiple HW contexts */ 397 mask = BIT(0); 398 399 /* Enable error detection */ 400 mask |= BIT(1); 401 402 /* Set default reset state */ 403 mask |= BIT(3); 404 405 /* Disable save/restore of performance counters across preemption */ 406 mask |= BIT(6); 407 408 OUT_RING(ring, mask); 409 410 /* Enable multiple hardware contexts */ 411 OUT_RING(ring, 0x00000003); 412 413 /* Enable error detection */ 414 OUT_RING(ring, 0x20000000); 415 416 /* Operation mode mask */ 417 OUT_RING(ring, 0x00000002); 418 419 a6xx_flush(gpu, ring); 420 return a8xx_idle(gpu, ring) ? 0 : -EINVAL; 421} 422 423#define A8XX_INT_MASK \ 424 (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 425 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 426 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 427 A6XX_RBBM_INT_0_MASK_CP_SW | \ 428 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 429 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 430 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 431 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 432 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 433 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 434 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 435 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 436 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 437 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 438 439#define A8XX_APRIV_MASK \ 440 (A8XX_CP_APRIV_CNTL_PIPE_ICACHE | \ 441 A8XX_CP_APRIV_CNTL_PIPE_RBFETCH | \ 442 A8XX_CP_APRIV_CNTL_PIPE_RBPRIVLEVEL | \ 443 A8XX_CP_APRIV_CNTL_PIPE_RBRPWB) 444 445#define A8XX_BR_APRIV_MASK \ 446 (A8XX_APRIV_MASK | \ 447 A8XX_CP_APRIV_CNTL_PIPE_CDREAD | \ 448 A8XX_CP_APRIV_CNTL_PIPE_CDWRITE) 449 450#define A8XX_CP_GLOBAL_INT_MASK \ 451 (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBR | \ 452 A8XX_CP_GLOBAL_INT_MASK_HWFAULTBV | \ 453 A8XX_CP_GLOBAL_INT_MASK_HWFAULTLPAC | \ 454 A8XX_CP_GLOBAL_INT_MASK_HWFAULTAQE0 | \ 455 A8XX_CP_GLOBAL_INT_MASK_HWFAULTAQE1 | \ 456 A8XX_CP_GLOBAL_INT_MASK_HWFAULTDDEBR | \ 457 A8XX_CP_GLOBAL_INT_MASK_HWFAULTDDEBV | \ 458 A8XX_CP_GLOBAL_INT_MASK_SWFAULTBR | \ 459 A8XX_CP_GLOBAL_INT_MASK_SWFAULTBV | \ 460 A8XX_CP_GLOBAL_INT_MASK_SWFAULTLPAC | \ 461 A8XX_CP_GLOBAL_INT_MASK_SWFAULTAQE0 | \ 462 A8XX_CP_GLOBAL_INT_MASK_SWFAULTAQE1 | \ 463 A8XX_CP_GLOBAL_INT_MASK_SWFAULTDDEBR | \ 464 A8XX_CP_GLOBAL_INT_MASK_SWFAULTDDEBV) 465 466#define A8XX_CP_INTERRUPT_STATUS_MASK_PIPE \ 467 (A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFRBWRAP | \ 468 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB1WRAP | \ 469 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB2WRAP | \ 470 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFIB3WRAP | \ 471 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFSDSWRAP | \ 472 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFMRBWRAP | \ 473 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_CSFVSDWRAP | \ 474 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_OPCODEERROR | \ 475 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VSDPARITYERROR | \ 476 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_REGISTERPROTECTIONERROR | \ 477 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_ILLEGALINSTRUCTION | \ 478 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_SMMUFAULT | \ 479 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPCLIENT| \ 480 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPTYPE | \ 481 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESPREAD | \ 482 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_VBIFRESP | \ 483 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_RTWROVF | \ 484 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTWROVF | \ 485 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTREFCNTOVF | \ 486 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE_LRZRTCLRRESMISS) 487 488#define A8XX_CP_HW_FAULT_STATUS_MASK_PIPE \ 489 (A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFRBFAULT | \ 490 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB1FAULT | \ 491 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB2FAULT | \ 492 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFIB3FAULT | \ 493 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFSDSFAULT | \ 494 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFMRBFAULT | \ 495 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_CSFVSDFAULT | \ 496 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_SQEREADBURSTOVF | \ 497 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_EVENTENGINEOVF | \ 498 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE_UCODEERROR) 499 500static int hw_init(struct msm_gpu *gpu) 501{ 502 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 503 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 504 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 505 unsigned int pipe_id, i; 506 u32 gmem_protect = 0; 507 u64 gmem_range_min; 508 int ret; 509 510 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 511 if (ret) 512 return ret; 513 514 /* Clear the cached value to force aperture configuration next time */ 515 a6xx_gpu->cached_aperture = UINT_MAX; 516 a8xx_aperture_clear(gpu); 517 518 /* Clear GBIF halt in case GX domain was not collapsed */ 519 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 520 gpu_read(gpu, REG_A6XX_GBIF_HALT); 521 522 gpu_write(gpu, REG_A8XX_RBBM_GBIF_HALT, 0); 523 gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT); 524 525 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 526 527 /* 528 * Disable the trusted memory range - we don't actually supported secure 529 * memory rendering at this point in time and we don't want to block off 530 * part of the virtual memory space. 531 */ 532 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 533 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 534 535 /* Make all blocks contribute to the GPU BUSY perf counter */ 536 gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 537 538 /* Setup GMEM Range in UCHE */ 539 gmem_range_min = SZ_64M; 540 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 541 gpu_write64(gpu, REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, gmem_range_min); 542 gpu_write64(gpu, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, gmem_range_min); 543 544 /* Setup UCHE Trap region */ 545 gpu_write64(gpu, REG_A8XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 546 gpu_write64(gpu, REG_A8XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 547 gpu_write64(gpu, REG_A8XX_UCHE_CCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 548 gpu_write64(gpu, REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 549 550 /* Turn on performance counters */ 551 gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_CNTL, 0x1); 552 gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_CNTL, 0x1); 553 554 /* Turn on the IFPC counter (countable 4 on XOCLK1) */ 555 gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1, 556 FIELD_PREP(GENMASK(7, 0), 0x4)); 557 558 /* Select CP0 to always count cycles */ 559 gpu_write(gpu, REG_A8XX_CP_PERFCTR_CP_SEL(0), 1); 560 561 a8xx_set_ubwc_config(gpu); 562 563 /* Set weights for bicubic filtering */ 564 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); 565 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 0x3fe05ff4); 566 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 0x3fa0ebee); 567 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 0x3f5193ed); 568 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 0x3f0243f0); 569 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), 0x00000000); 570 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), 0x3fd093e8); 571 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), 0x3f4133dc); 572 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), 0x3ea1dfdb); 573 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), 0x3e0283e0); 574 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), 0x0000ac2b); 575 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), 0x0000f01d); 576 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), 0x00114412); 577 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), 0x0021980a); 578 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), 0x0051ec05); 579 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), 0x0000380e); 580 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), 0x3ff09001); 581 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), 0x3fc10bfa); 582 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), 0x3f9193f7); 583 gpu_write(gpu, REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), 0x3f7227f7); 584 585 gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 586 587 a8xx_nonctxt_config(gpu, &gmem_protect); 588 589 /* Enable fault detection */ 590 gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff); 591 gpu_write(gpu, REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, BIT(30)); 592 593 /* Set up the CX GMU counter 0 to count busy ticks */ 594 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 595 596 /* Enable the power counter */ 597 gmu_rmw(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_0, 0xff, BIT(5)); 598 gmu_write(gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 599 600 /* Protect registers from the CP */ 601 a8xx_set_cp_protect(gpu); 602 603 /* Enable the GMEM save/restore feature for preemption */ 604 a8xx_write_pipe(gpu, PIPE_BR, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 1); 605 606 for (pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) { 607 u32 apriv_mask = A8XX_APRIV_MASK; 608 unsigned long flags; 609 610 if (pipe_id == PIPE_LPAC) 611 continue; 612 613 if (pipe_id == PIPE_BR) 614 apriv_mask = A8XX_BR_APRIV_MASK; 615 616 a8xx_aperture_acquire(gpu, pipe_id, &flags); 617 gpu_write(gpu, REG_A8XX_CP_APRIV_CNTL_PIPE, apriv_mask); 618 gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 619 A8XX_CP_INTERRUPT_STATUS_MASK_PIPE); 620 gpu_write(gpu, REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 621 A8XX_CP_HW_FAULT_STATUS_MASK_PIPE); 622 a8xx_aperture_release(gpu, flags); 623 } 624 625 a8xx_aperture_clear(gpu); 626 627 /* Enable interrupts */ 628 gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, A8XX_CP_GLOBAL_INT_MASK); 629 gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, A8XX_INT_MASK); 630 631 ret = adreno_hw_init(gpu); 632 if (ret) 633 goto out; 634 635 gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 636 if (a6xx_gpu->aqe_iova) 637 gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova); 638 639 /* Set the ringbuffer address */ 640 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 641 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 642 643 /* Configure the RPTR shadow if needed: */ 644 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0])); 645 gpu_write64(gpu, REG_A8XX_CP_RB_RPTR_ADDR_BV, rbmemptr(gpu->rb[0], bv_rptr)); 646 647 for (i = 0; i < gpu->nr_rings; i++) 648 a6xx_gpu->shadow[i] = 0; 649 650 /* Always come up on rb 0 */ 651 a6xx_gpu->cur_ring = gpu->rb[0]; 652 653 for (i = 0; i < gpu->nr_rings; i++) 654 gpu->rb[i]->cur_ctx_seqno = 0; 655 656 /* Enable the SQE_to start the CP engine */ 657 gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 1); 658 659 ret = a8xx_cp_init(gpu); 660 if (ret) 661 goto out; 662 663 /* 664 * Try to load a zap shader into the secure world. If successful 665 * we can use the CP to switch out of secure mode. If not then we 666 * have no resource but to try to switch ourselves out manually. If we 667 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 668 * be blocked and a permissions violation will soon follow. 669 */ 670 ret = a6xx_zap_shader_init(gpu); 671 if (!ret) { 672 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 673 OUT_RING(gpu->rb[0], 0x00000000); 674 675 a6xx_flush(gpu, gpu->rb[0]); 676 if (!a8xx_idle(gpu, gpu->rb[0])) 677 return -EINVAL; 678 } else if (ret == -ENODEV) { 679 /* 680 * This device does not use zap shader (but print a warning 681 * just in case someone got their dt wrong.. hopefully they 682 * have a debug UART to realize the error of their ways... 683 * if you mess this up you are about to crash horribly) 684 */ 685 dev_warn_once(gpu->dev->dev, 686 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 687 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 688 ret = 0; 689 } else { 690 return ret; 691 } 692 693 /* 694 * GMEM_PROTECT register should be programmed after GPU is transitioned to 695 * non-secure mode 696 */ 697 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); 698 WARN_ON(!gmem_protect); 699 a8xx_aperture_clear(gpu); 700 701 /* Enable hardware clockgating */ 702 a8xx_set_hwcg(gpu, true); 703out: 704 /* 705 * Tell the GMU that we are done touching the GPU and it can start power 706 * management 707 */ 708 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 709 710 return ret; 711} 712 713int a8xx_hw_init(struct msm_gpu *gpu) 714{ 715 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 716 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 717 int ret; 718 719 mutex_lock(&a6xx_gpu->gmu.lock); 720 ret = hw_init(gpu); 721 mutex_unlock(&a6xx_gpu->gmu.lock); 722 723 return ret; 724} 725 726static void a8xx_dump(struct msm_gpu *gpu) 727{ 728 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", gpu_read(gpu, REG_A8XX_RBBM_STATUS)); 729 adreno_dump(gpu); 730} 731 732void a8xx_recover(struct msm_gpu *gpu) 733{ 734 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 735 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 736 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 737 int active_submits; 738 739 adreno_dump_info(gpu); 740 741 if (hang_debug) 742 a8xx_dump(gpu); 743 744 /* 745 * To handle recovery specific sequences during the rpm suspend we are 746 * about to trigger 747 */ 748 a6xx_gpu->hung = true; 749 750 /* Halt SQE first */ 751 gpu_write(gpu, REG_A8XX_CP_SQE_CNTL, 3); 752 753 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 754 755 /* active_submit won't change until we make a submission */ 756 mutex_lock(&gpu->active_lock); 757 active_submits = gpu->active_submits; 758 759 /* 760 * Temporarily clear active_submits count to silence a WARN() in the 761 * runtime suspend cb 762 */ 763 gpu->active_submits = 0; 764 765 reinit_completion(&gmu->pd_gate); 766 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 767 dev_pm_genpd_synced_poweroff(gmu->cxpd); 768 769 /* Drop the rpm refcount from active submits */ 770 if (active_submits) 771 pm_runtime_put(&gpu->pdev->dev); 772 773 /* And the final one from recover worker */ 774 pm_runtime_put_sync(&gpu->pdev->dev); 775 776 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 777 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 778 779 dev_pm_genpd_remove_notifier(gmu->cxpd); 780 781 pm_runtime_use_autosuspend(&gpu->pdev->dev); 782 783 if (active_submits) 784 pm_runtime_get(&gpu->pdev->dev); 785 786 pm_runtime_get_sync(&gpu->pdev->dev); 787 788 gpu->active_submits = active_submits; 789 mutex_unlock(&gpu->active_lock); 790 791 msm_gpu_hw_init(gpu); 792 a6xx_gpu->hung = false; 793} 794 795static const char *a8xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 796{ 797 static const char * const uche_clients[] = { 798 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 799 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 800 "STCHE", 801 }; 802 static const char * const uche_clients_lpac[] = { 803 "-", "SP_LPAC", "-", "-", "HLSQ_LPAC", "-", "-", "TP_LPAC", 804 }; 805 u32 val; 806 807 /* 808 * The source of the data depends on the mid ID read from FSYNR1. 809 * and the client ID read from the UCHE block 810 */ 811 val = gpu_read(gpu, REG_A8XX_UCHE_CLIENT_PF); 812 813 val &= GENMASK(6, 0); 814 815 /* mid=3 refers to BR or BV */ 816 if (mid == 3) { 817 if (val < ARRAY_SIZE(uche_clients)) 818 return uche_clients[val]; 819 else 820 return "UCHE"; 821 } 822 823 /* mid=8 refers to LPAC */ 824 if (mid == 8) { 825 if (val < ARRAY_SIZE(uche_clients_lpac)) 826 return uche_clients_lpac[val]; 827 else 828 return "UCHE_LPAC"; 829 } 830 831 return "Unknown"; 832} 833 834static const char *a8xx_fault_block(struct msm_gpu *gpu, u32 id) 835{ 836 switch (id) { 837 case 0x0: 838 return "CP"; 839 case 0x1: 840 return "UCHE: Unknown"; 841 case 0x2: 842 return "UCHE_LPAC: Unknown"; 843 case 0x3: 844 case 0x8: 845 return a8xx_uche_fault_block(gpu, id); 846 case 0x4: 847 return "CCU"; 848 case 0x5: 849 return "Flag cache"; 850 case 0x6: 851 return "PREFETCH"; 852 case 0x7: 853 return "GMU"; 854 case 0x9: 855 return "UCHE_HPAC"; 856 } 857 858 return "Unknown"; 859} 860 861int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 862{ 863 struct msm_gpu *gpu = arg; 864 struct adreno_smmu_fault_info *info = data; 865 const char *block = "unknown"; 866 867 u32 scratch[] = { 868 gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(0)), 869 gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(1)), 870 gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(2)), 871 gpu_read(gpu, REG_A8XX_CP_SCRATCH_GLOBAL(3)), 872 }; 873 874 if (info) 875 block = a8xx_fault_block(gpu, info->fsynr1 & 0xff); 876 877 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 878} 879 880static void a8xx_cp_hw_err_irq(struct msm_gpu *gpu) 881{ 882 u32 status = gpu_read(gpu, REG_A8XX_CP_INTERRUPT_STATUS_GLOBAL); 883 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 884 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 885 u32 slice = a8xx_get_first_slice(a6xx_gpu); 886 u32 hw_fault_mask = GENMASK(6, 0); 887 u32 sw_fault_mask = GENMASK(22, 16); 888 u32 pipe = 0; 889 890 dev_err_ratelimited(&gpu->pdev->dev, "CP Fault Global INT status: 0x%x\n", status); 891 892 if (status & (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBR | 893 A8XX_CP_GLOBAL_INT_MASK_SWFAULTBR)) 894 pipe |= BIT(PIPE_BR); 895 896 if (status & (A8XX_CP_GLOBAL_INT_MASK_HWFAULTBV | 897 A8XX_CP_GLOBAL_INT_MASK_SWFAULTBV)) 898 pipe |= BIT(PIPE_BV); 899 900 if (!pipe) { 901 dev_err_ratelimited(&gpu->pdev->dev, "CP Fault Unknown pipe\n"); 902 goto out; 903 } 904 905 for (unsigned int pipe_id = PIPE_NONE; pipe_id <= PIPE_DDE_BV; pipe_id++) { 906 if (!(BIT(pipe_id) & pipe)) 907 continue; 908 909 if (hw_fault_mask & status) { 910 status = a8xx_read_pipe_slice(gpu, pipe_id, slice, 911 REG_A8XX_CP_HW_FAULT_STATUS_PIPE); 912 dev_err_ratelimited(&gpu->pdev->dev, 913 "CP HW FAULT pipe: %u status: 0x%x\n", pipe_id, status); 914 } 915 916 if (sw_fault_mask & status) { 917 status = a8xx_read_pipe_slice(gpu, pipe_id, slice, 918 REG_A8XX_CP_INTERRUPT_STATUS_PIPE); 919 dev_err_ratelimited(&gpu->pdev->dev, 920 "CP SW FAULT pipe: %u status: 0x%x\n", pipe_id, status); 921 922 if (status & BIT(8)) { 923 a8xx_write_pipe(gpu, pipe_id, REG_A8XX_CP_SQE_STAT_ADDR_PIPE, 1); 924 status = a8xx_read_pipe_slice(gpu, pipe_id, slice, 925 REG_A8XX_CP_SQE_STAT_DATA_PIPE); 926 dev_err_ratelimited(&gpu->pdev->dev, 927 "CP Opcode error, opcode=0x%x\n", status); 928 } 929 930 if (status & BIT(10)) { 931 status = a8xx_read_pipe_slice(gpu, pipe_id, slice, 932 REG_A8XX_CP_PROTECT_STATUS_PIPE); 933 dev_err_ratelimited(&gpu->pdev->dev, 934 "CP REG PROTECT error, status=0x%x\n", status); 935 } 936 } 937 } 938 939out: 940 /* Turn off interrupts to avoid triggering recovery again */ 941 a8xx_aperture_clear(gpu); 942 gpu_write(gpu, REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL, 0); 943 gpu_write(gpu, REG_A8XX_RBBM_INT_0_MASK, 0); 944 945 kthread_queue_work(gpu->worker, &gpu->recover_work); 946} 947 948static u32 gpu_periph_read(struct msm_gpu *gpu, u32 dbg_offset) 949{ 950 gpu_write(gpu, REG_A8XX_CP_SQE_UCODE_DBG_ADDR_PIPE, dbg_offset); 951 952 return gpu_read(gpu, REG_A8XX_CP_SQE_UCODE_DBG_DATA_PIPE); 953} 954 955static u64 gpu_periph_read64(struct msm_gpu *gpu, u32 dbg_offset) 956{ 957 u64 lo, hi; 958 959 lo = gpu_periph_read(gpu, dbg_offset); 960 hi = gpu_periph_read(gpu, dbg_offset + 1); 961 962 return (hi << 32) | lo; 963} 964 965#define CP_PERIPH_IB1_BASE_LO 0x7005 966#define CP_PERIPH_IB1_BASE_HI 0x7006 967#define CP_PERIPH_IB1_SIZE 0x7007 968#define CP_PERIPH_IB1_OFFSET 0x7008 969#define CP_PERIPH_IB2_BASE_LO 0x7009 970#define CP_PERIPH_IB2_BASE_HI 0x700a 971#define CP_PERIPH_IB2_SIZE 0x700b 972#define CP_PERIPH_IB2_OFFSET 0x700c 973#define CP_PERIPH_IB3_BASE_LO 0x700d 974#define CP_PERIPH_IB3_BASE_HI 0x700e 975#define CP_PERIPH_IB3_SIZE 0x700f 976#define CP_PERIPH_IB3_OFFSET 0x7010 977 978static void a8xx_fault_detect_irq(struct msm_gpu *gpu) 979{ 980 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 981 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 982 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 983 unsigned long flags; 984 985 /* 986 * If stalled on SMMU fault, we could trip the GPU's hang detection, 987 * but the fault handler will trigger the devcore dump, and we want 988 * to otherwise resume normally rather than killing the submit, so 989 * just bail. 990 */ 991 if (gpu_read(gpu, REG_A8XX_RBBM_MISC_STATUS) & A8XX_RBBM_MISC_STATUS_SMMU_STALLED_ON_FAULT) 992 return; 993 994 /* 995 * Force the GPU to stay on until after we finish 996 * collecting information 997 */ 998 if (!adreno_has_gmu_wrapper(adreno_gpu)) 999 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1000 1001 DRM_DEV_ERROR(&gpu->pdev->dev, 1002 "gpu fault ring %d fence %x status %8.8X gfx_status %8.8X\n", 1003 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1004 gpu_read(gpu, REG_A8XX_RBBM_STATUS), gpu_read(gpu, REG_A8XX_RBBM_GFX_STATUS)); 1005 1006 a8xx_aperture_acquire(gpu, PIPE_BR, &flags); 1007 1008 DRM_DEV_ERROR(&gpu->pdev->dev, 1009 "BR: status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x ib3 %16.16llX/%4.4x\n", 1010 gpu_read(gpu, REG_A8XX_RBBM_GFX_BR_STATUS), 1011 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1012 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1013 gpu_periph_read64(gpu, CP_PERIPH_IB1_BASE_LO), 1014 gpu_periph_read(gpu, CP_PERIPH_IB1_OFFSET), 1015 gpu_periph_read64(gpu, CP_PERIPH_IB2_BASE_LO), 1016 gpu_periph_read(gpu, CP_PERIPH_IB2_OFFSET), 1017 gpu_periph_read64(gpu, CP_PERIPH_IB3_BASE_LO), 1018 gpu_periph_read(gpu, CP_PERIPH_IB3_OFFSET)); 1019 1020 a8xx_aperture_release(gpu, flags); 1021 a8xx_aperture_acquire(gpu, PIPE_BV, &flags); 1022 1023 DRM_DEV_ERROR(&gpu->pdev->dev, 1024 "BV: status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x ib3 %16.16llX/%4.4x\n", 1025 gpu_read(gpu, REG_A8XX_RBBM_GFX_BV_STATUS), 1026 gpu_read(gpu, REG_A8XX_CP_RB_RPTR_BV), 1027 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1028 gpu_periph_read64(gpu, CP_PERIPH_IB1_BASE_LO), 1029 gpu_periph_read(gpu, CP_PERIPH_IB1_OFFSET), 1030 gpu_periph_read64(gpu, CP_PERIPH_IB2_BASE_LO), 1031 gpu_periph_read(gpu, CP_PERIPH_IB2_OFFSET), 1032 gpu_periph_read64(gpu, CP_PERIPH_IB3_BASE_LO), 1033 gpu_periph_read(gpu, CP_PERIPH_IB3_OFFSET)); 1034 1035 a8xx_aperture_release(gpu, flags); 1036 a8xx_aperture_clear(gpu); 1037 1038 /* Turn off the hangcheck timer to keep it from bothering us */ 1039 timer_delete(&gpu->hangcheck_timer); 1040 1041 kthread_queue_work(gpu->worker, &gpu->recover_work); 1042} 1043 1044static void a8xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1045{ 1046 u32 status; 1047 1048 status = gpu_read(gpu, REG_A8XX_RBBM_SW_FUSE_INT_STATUS); 1049 gpu_write(gpu, REG_A8XX_RBBM_SW_FUSE_INT_MASK, 0); 1050 1051 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1052 1053 /* 1054 * Ignore FASTBLEND violations, because the HW will silently fall back 1055 * to legacy blending. 1056 */ 1057 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1058 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1059 timer_delete(&gpu->hangcheck_timer); 1060 1061 kthread_queue_work(gpu->worker, &gpu->recover_work); 1062 } 1063} 1064 1065irqreturn_t a8xx_irq(struct msm_gpu *gpu) 1066{ 1067 struct msm_drm_private *priv = gpu->dev->dev_private; 1068 u32 status = gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS); 1069 1070 gpu_write(gpu, REG_A8XX_RBBM_INT_CLEAR_CMD, status); 1071 1072 if (priv->disable_err_irq) 1073 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1074 1075 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1076 a8xx_fault_detect_irq(gpu); 1077 1078 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) { 1079 u32 rl0, rl1; 1080 1081 rl0 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0); 1082 rl1 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1); 1083 dev_err_ratelimited(&gpu->pdev->dev, 1084 "CP | AHB bus error RL_ERROR_0: %x, RL_ERROR_1: %x\n", rl0, rl1); 1085 } 1086 1087 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1088 a8xx_cp_hw_err_irq(gpu); 1089 1090 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1091 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1092 1093 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1094 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1095 1096 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1097 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1098 1099 if (status & A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 1100 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Trap interrupt\n"); 1101 1102 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1103 a8xx_sw_fuse_violation_irq(gpu); 1104 1105 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { 1106 msm_gpu_retire(gpu); 1107 a6xx_preempt_trigger(gpu); 1108 } 1109 1110 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1111 a6xx_preempt_irq(gpu); 1112 1113 return IRQ_HANDLED; 1114} 1115 1116void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1117{ 1118 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1119 struct msm_gpu *gpu = &adreno_gpu->base; 1120 1121 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1122 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1123 1124 gpu_scid &= GENMASK(5, 0); 1125 1126 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 1127 FIELD_PREP(GENMASK(29, 24), gpu_scid) | 1128 FIELD_PREP(GENMASK(23, 18), gpu_scid) | 1129 FIELD_PREP(GENMASK(17, 12), gpu_scid) | 1130 FIELD_PREP(GENMASK(11, 6), gpu_scid) | 1131 FIELD_PREP(GENMASK(5, 0), gpu_scid)); 1132 1133 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 1134 FIELD_PREP(GENMASK(27, 22), gpu_scid) | 1135 FIELD_PREP(GENMASK(21, 16), gpu_scid) | 1136 FIELD_PREP(GENMASK(15, 10), gpu_scid) | 1137 BIT(8)); 1138 } 1139 1140 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 1141} 1142 1143#define GBIF_CLIENT_HALT_MASK BIT(0) 1144#define GBIF_ARB_HALT_MASK BIT(1) 1145#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 1146#define VBIF_RESET_ACK_MASK 0xF0 1147#define GPR0_GBIF_HALT_REQUEST 0x1E0 1148 1149void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 1150{ 1151 struct msm_gpu *gpu = &adreno_gpu->base; 1152 1153 if (gx_off) { 1154 /* Halt the gx side of GBIF */ 1155 gpu_write(gpu, REG_A8XX_RBBM_GBIF_HALT, 1); 1156 spin_until(gpu_read(gpu, REG_A8XX_RBBM_GBIF_HALT_ACK) & 1); 1157 } 1158 1159 /* Halt new client requests on GBIF */ 1160 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 1161 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1162 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 1163 1164 /* Halt all AXI requests on GBIF */ 1165 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 1166 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1167 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 1168 1169 /* The GBIF halt needs to be explicitly cleared */ 1170 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 1171} 1172 1173int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1174{ 1175 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1176 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1177 1178 mutex_lock(&a6xx_gpu->gmu.lock); 1179 1180 /* Force the GPU power on so we can read this register */ 1181 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1182 1183 *value = gpu_read64(gpu, REG_A8XX_CP_ALWAYS_ON_COUNTER); 1184 1185 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1186 1187 mutex_unlock(&a6xx_gpu->gmu.lock); 1188 1189 return 0; 1190} 1191 1192u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 1193{ 1194 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1195 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1196 u64 busy_cycles; 1197 1198 /* 19.2MHz */ 1199 *out_sample_rate = 19200000; 1200 1201 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 1202 REG_A8XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 1203 REG_A8XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 1204 1205 return busy_cycles; 1206} 1207 1208bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 1209{ 1210 return true; 1211}
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