mgag200_g200eh5.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2
  3#include <linux/limits.h>
  4#include <linux/pci.h>
  5#include <linux/units.h>
  6
  7#include <drm/drm_atomic.h>
  8#include <drm/drm_atomic_helper.h>
  9#include <drm/drm_drv.h>
 10#include <drm/drm_gem_atomic_helper.h>
 11#include <drm/drm_print.h>
 12#include <drm/drm_probe_helper.h>
 13
 14#include "mgag200_drv.h"
 15
 16/*
 17 * PIXPLLC
 18 */
 19
 20static int mgag200_g200eh5_pixpllc_atomic_check(struct drm_crtc *crtc,
 21						struct drm_atomic_state *new_state)
 22{
 23	const unsigned long long VCO_MAX = 10 * GIGA; // Hz
 24	const unsigned long long VCO_MIN = 2500 * MEGA; // Hz
 25	const unsigned long long PLL_FREQ_REF = 25 * MEGA; // Hz
 26
 27	struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
 28	struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
 29	long clock = new_crtc_state->mode.clock;
 30	struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc;
 31
 32	unsigned long long fdelta = ULLONG_MAX;
 33
 34	u16 mult_max = (u16)(VCO_MAX / PLL_FREQ_REF); // 400 (0x190)
 35	u16 mult_min = (u16)(VCO_MIN / PLL_FREQ_REF); // 100 (0x64)
 36
 37	u64 ftmp_delta;
 38	u64 computed_fo;
 39
 40	u16 test_m;
 41	u8 test_div_a;
 42	u8 test_div_b;
 43	u64 fo_hz;
 44
 45	u8 uc_m = 0;
 46	u8 uc_n = 0;
 47	u8 uc_p = 0;
 48
 49	fo_hz = (u64)clock * HZ_PER_KHZ;
 50
 51	for (test_m = mult_min; test_m <= mult_max; test_m++) { // This gives 100 <= M <= 400
 52		for (test_div_a = 8; test_div_a > 0; test_div_a--) { // This gives 1 <= A <= 8
 53			for (test_div_b = 1; test_div_b <= test_div_a; test_div_b++) {
 54				// This gives 1 <= B <= A
 55				computed_fo = (PLL_FREQ_REF * test_m) /
 56					(4 * test_div_a * test_div_b);
 57
 58				if (computed_fo > fo_hz)
 59					ftmp_delta = computed_fo - fo_hz;
 60				else
 61					ftmp_delta = fo_hz - computed_fo;
 62
 63				if (ftmp_delta < fdelta) {
 64					fdelta = ftmp_delta;
 65					uc_m = (u8)(0xFF & test_m);
 66					uc_n = (u8)((0x7 & (test_div_a - 1))
 67						| (0x70 & (0x7 & (test_div_b - 1)) << 4));
 68					uc_p = (u8)(1 & (test_m >> 8));
 69				}
 70				if (fdelta == 0)
 71					break;
 72			}
 73			if (fdelta == 0)
 74				break;
 75		}
 76		if (fdelta == 0)
 77			break;
 78	}
 79
 80	pixpllc->m = uc_m + 1;
 81	pixpllc->n = uc_n + 1;
 82	pixpllc->p = uc_p + 1;
 83	pixpllc->s = 0;
 84
 85	return 0;
 86	}
 87
 88/*
 89 * Mode-setting pipeline
 90 */
 91
 92static const struct drm_plane_helper_funcs mgag200_g200eh5_primary_plane_helper_funcs = {
 93	MGAG200_PRIMARY_PLANE_HELPER_FUNCS,
 94};
 95
 96static const struct drm_plane_funcs mgag200_g200eh5_primary_plane_funcs = {
 97	MGAG200_PRIMARY_PLANE_FUNCS,
 98};
 99
100static const struct drm_crtc_helper_funcs mgag200_g200eh5_crtc_helper_funcs = {
101	MGAG200_CRTC_HELPER_FUNCS,
102};
103
104static const struct drm_crtc_funcs mgag200_g200eh5_crtc_funcs = {
105	MGAG200_CRTC_FUNCS,
106};
107
108static int mgag200_g200eh5_pipeline_init(struct mga_device *mdev)
109{
110	struct drm_device *dev = &mdev->base;
111	struct drm_plane *primary_plane = &mdev->primary_plane;
112	struct drm_crtc *crtc = &mdev->crtc;
113	int ret;
114
115	ret = drm_universal_plane_init(dev, primary_plane, 0,
116				       &mgag200_g200eh5_primary_plane_funcs,
117				       mgag200_primary_plane_formats,
118				       mgag200_primary_plane_formats_size,
119				       mgag200_primary_plane_fmtmods,
120				       DRM_PLANE_TYPE_PRIMARY, NULL);
121	if (ret) {
122		drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
123		return ret;
124	}
125	drm_plane_helper_add(primary_plane, &mgag200_g200eh5_primary_plane_helper_funcs);
126	drm_plane_enable_fb_damage_clips(primary_plane);
127
128	ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
129					&mgag200_g200eh5_crtc_funcs, NULL);
130	if (ret) {
131		drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n", ret);
132		return ret;
133	}
134
135	drm_crtc_helper_add(crtc, &mgag200_g200eh5_crtc_helper_funcs);
136
137	/* FIXME: legacy gamma tables, but atomic gamma doesn't work without */
138	drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE);
139	drm_crtc_enable_color_mgmt(crtc, 0, false, MGAG200_LUT_SIZE);
140	ret = mgag200_vga_bmc_output_init(mdev);
141
142	if (ret)
143		return ret;
144
145	return 0;
146}
147
148/*
149 * DRM device
150 */
151
152static const struct mgag200_device_info mgag200_g200eh5_device_info =
153	MGAG200_DEVICE_INFO_INIT(2048, 2048, 0, false, 1, 0, false);
154
155static const struct mgag200_device_funcs mgag200_g200eh5_device_funcs = {
156	.pixpllc_atomic_check = mgag200_g200eh5_pixpllc_atomic_check,
157	.pixpllc_atomic_update = mgag200_g200eh_pixpllc_atomic_update, // same as G200EH
158};
159
160struct mga_device *mgag200_g200eh5_device_create(struct pci_dev *pdev,
161						 const struct drm_driver *drv)
162{
163	struct mga_device *mdev;
164	struct drm_device *dev;
165	resource_size_t vram_available;
166	int ret;
167
168	mdev = devm_drm_dev_alloc(&pdev->dev, drv, struct mga_device, base);
169
170	if (IS_ERR(mdev))
171		return mdev;
172	dev = &mdev->base;
173
174	pci_set_drvdata(pdev, dev);
175
176	ret = mgag200_init_pci_options(pdev, 0x00000120, 0x0000b000);
177	if (ret)
178		return ERR_PTR(ret);
179
180	ret = mgag200_device_preinit(mdev);
181	if (ret)
182		return ERR_PTR(ret);
183
184	ret = mgag200_device_init(mdev, &mgag200_g200eh5_device_info,
185				  &mgag200_g200eh5_device_funcs);
186
187	if (ret)
188		return ERR_PTR(ret);
189
190	mgag200_g200eh_init_registers(mdev); // same as G200EH
191	vram_available = mgag200_device_probe_vram(mdev);
192
193	ret = mgag200_mode_config_init(mdev, vram_available);
194	if (ret)
195		return ERR_PTR(ret);
196
197	ret = mgag200_g200eh5_pipeline_init(mdev);
198	if (ret)
199		return ERR_PTR(ret);
200
201	drm_mode_config_reset(dev);
202	drm_kms_helper_poll_init(dev);
203
204	return mdev;
205}