mtk_hdmi_common.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2021 MediaTek Inc.
  4 * Copyright (c) 2024 Collabora Ltd.
  5 */
  6
  7#ifndef _MTK_HDMI_COMMON_H
  8#define _MTK_HDMI_COMMON_H
  9
 10#include <drm/drm_atomic_helper.h>
 11#include <drm/drm_bridge.h>
 12#include <drm/drm_crtc.h>
 13#include <drm/drm_crtc_helper.h>
 14#include <drm/drm_edid.h>
 15#include <drm/drm_print.h>
 16
 17#include <linux/clk.h>
 18#include <linux/device.h>
 19#include <linux/hdmi.h>
 20#include <linux/i2c.h>
 21#include <linux/mfd/syscon.h>
 22#include <linux/mutex.h>
 23#include <linux/phy/phy.h>
 24#include <linux/platform_device.h>
 25
 26#include <sound/hdmi-codec.h>
 27
 28enum hdmi_aud_input_type {
 29	HDMI_AUD_INPUT_I2S = 0,
 30	HDMI_AUD_INPUT_SPDIF,
 31};
 32
 33enum hdmi_aud_i2s_fmt {
 34	HDMI_I2S_MODE_RJT_24BIT = 0,
 35	HDMI_I2S_MODE_RJT_16BIT,
 36	HDMI_I2S_MODE_LJT_24BIT,
 37	HDMI_I2S_MODE_LJT_16BIT,
 38	HDMI_I2S_MODE_I2S_24BIT,
 39	HDMI_I2S_MODE_I2S_16BIT
 40};
 41
 42enum hdmi_aud_mclk {
 43	HDMI_AUD_MCLK_128FS,
 44	HDMI_AUD_MCLK_192FS,
 45	HDMI_AUD_MCLK_256FS,
 46	HDMI_AUD_MCLK_384FS,
 47	HDMI_AUD_MCLK_512FS,
 48	HDMI_AUD_MCLK_768FS,
 49	HDMI_AUD_MCLK_1152FS,
 50};
 51
 52enum hdmi_aud_channel_type {
 53	HDMI_AUD_CHAN_TYPE_1_0 = 0,
 54	HDMI_AUD_CHAN_TYPE_1_1,
 55	HDMI_AUD_CHAN_TYPE_2_0,
 56	HDMI_AUD_CHAN_TYPE_2_1,
 57	HDMI_AUD_CHAN_TYPE_3_0,
 58	HDMI_AUD_CHAN_TYPE_3_1,
 59	HDMI_AUD_CHAN_TYPE_4_0,
 60	HDMI_AUD_CHAN_TYPE_4_1,
 61	HDMI_AUD_CHAN_TYPE_5_0,
 62	HDMI_AUD_CHAN_TYPE_5_1,
 63	HDMI_AUD_CHAN_TYPE_6_0,
 64	HDMI_AUD_CHAN_TYPE_6_1,
 65	HDMI_AUD_CHAN_TYPE_7_0,
 66	HDMI_AUD_CHAN_TYPE_7_1,
 67	HDMI_AUD_CHAN_TYPE_3_0_LRS,
 68	HDMI_AUD_CHAN_TYPE_3_1_LRS,
 69	HDMI_AUD_CHAN_TYPE_4_0_CLRS,
 70	HDMI_AUD_CHAN_TYPE_4_1_CLRS,
 71	HDMI_AUD_CHAN_TYPE_6_1_CS,
 72	HDMI_AUD_CHAN_TYPE_6_1_CH,
 73	HDMI_AUD_CHAN_TYPE_6_1_OH,
 74	HDMI_AUD_CHAN_TYPE_6_1_CHR,
 75	HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
 76	HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
 77	HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
 78	HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
 79	HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
 80	HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
 81	HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
 82	HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
 83	HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
 84	HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
 85	HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
 86	HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
 87	HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
 88	HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
 89	HDMI_AUD_CHAN_TYPE_6_0_CS,
 90	HDMI_AUD_CHAN_TYPE_6_0_CH,
 91	HDMI_AUD_CHAN_TYPE_6_0_OH,
 92	HDMI_AUD_CHAN_TYPE_6_0_CHR,
 93	HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
 94	HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
 95	HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
 96	HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
 97	HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
 98	HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
 99	HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
100	HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
101	HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
102	HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
103	HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
104	HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
105	HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
106	HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
107	HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
108	HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
109};
110
111enum hdmi_aud_channel_swap_type {
112	HDMI_AUD_SWAP_LR,
113	HDMI_AUD_SWAP_LFE_CC,
114	HDMI_AUD_SWAP_LSRS,
115	HDMI_AUD_SWAP_RLS_RRS,
116	HDMI_AUD_SWAP_LR_STATUS,
117};
118
119struct hdmi_audio_param {
120	enum hdmi_audio_coding_type aud_codec;
121	enum hdmi_audio_sample_size aud_sample_size;
122	enum hdmi_aud_input_type aud_input_type;
123	enum hdmi_aud_i2s_fmt aud_i2s_fmt;
124	enum hdmi_aud_mclk aud_mclk;
125	enum hdmi_aud_channel_type aud_input_chan_type;
126	struct hdmi_codec_params codec_params;
127};
128
129enum hdmi_hpd_state {
130	HDMI_PLUG_OUT = 0,
131	HDMI_PLUG_IN_AND_SINK_POWER_ON,
132	HDMI_PLUG_IN_ONLY,
133};
134
135struct mtk_hdmi_ver_conf {
136	const struct drm_bridge_funcs *bridge_funcs;
137	const struct hdmi_codec_ops *codec_ops;
138	const char * const *mtk_hdmi_clock_names;
139	int num_clocks;
140	bool interlace_allowed;
141};
142
143struct mtk_hdmi_conf {
144	const struct mtk_hdmi_ver_conf *ver_conf;
145	bool tz_disabled;
146	bool cea_modes_only;
147	unsigned long max_mode_clock;
148	u32 reg_hdmi_tx_cfg;
149};
150
151struct mtk_hdmi {
152	struct drm_bridge bridge;
153	struct drm_bridge *next_bridge;
154	struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
155	struct device *dev;
156	const struct mtk_hdmi_conf *conf;
157	struct phy *phy;
158	struct device *cec_dev;
159	struct i2c_adapter *ddc_adpt;
160	struct clk **clk;
161	struct drm_display_mode mode;
162	bool dvi_mode;
163	struct regmap *sys_regmap;
164	unsigned int sys_offset;
165	struct regmap *regs;
166	struct platform_device *audio_pdev;
167	struct hdmi_audio_param aud_param;
168	bool audio_enable;
169	bool powered;
170	bool enabled;
171	int irq;
172	enum hdmi_hpd_state hpd;
173	hdmi_codec_plugged_cb plugged_cb;
174	struct device *codec_dev;
175	struct mutex update_plugged_status_lock;
176};
177
178static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
179{
180	return container_of(b, struct mtk_hdmi, bridge);
181}
182
183
184int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);
185void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
186				   struct device *codec_dev);
187int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt *daifmt,
188			  struct hdmi_codec_params *params);
189void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
190		       unsigned int *n, unsigned int *cts);
191bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
192				const struct drm_display_mode *mode,
193				struct drm_display_mode *adjusted_mode);
194void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
195			      const struct drm_display_mode *mode,
196			      const struct drm_display_mode *adjusted_mode);
197struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev);
198#endif /* _MTK_HDMI_COMMON_H */