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mtk_hdmi.c
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linux-6.19.14/drivers/gpu/drm/mediatek/mtk_hdmi.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7#include <linux/arm-smccc.h> 8#include <linux/clk.h> 9#include <linux/delay.h> 10#include <linux/hdmi.h> 11#include <linux/i2c.h> 12#include <linux/io.h> 13#include <linux/kernel.h> 14#include <linux/mfd/syscon.h> 15#include <linux/module.h> 16#include <linux/mutex.h> 17#include <linux/of_platform.h> 18#include <linux/of.h> 19#include <linux/of_graph.h> 20#include <linux/phy/phy.h> 21#include <linux/platform_device.h> 22#include <linux/regmap.h> 23 24#include <sound/hdmi-codec.h> 25 26#include <drm/drm_atomic_helper.h> 27#include <drm/drm_bridge.h> 28#include <drm/drm_crtc.h> 29#include <drm/drm_edid.h> 30#include <drm/drm_print.h> 31#include <drm/drm_probe_helper.h> 32 33#include "mtk_cec.h" 34#include "mtk_hdmi_common.h" 35#include "mtk_hdmi_regs.h" 36 37#define NCTS_BYTES 7 38 39enum mtk_hdmi_clk_id { 40 MTK_HDMI_CLK_HDMI_PIXEL, 41 MTK_HDMI_CLK_HDMI_PLL, 42 MTK_HDMI_CLK_AUD_BCLK, 43 MTK_HDMI_CLK_AUD_SPDIF, 44 MTK_HDMI_CLK_COUNT 45}; 46 47static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 48{ 49 regmap_update_bits(hdmi->regs, VIDEO_CFG_4, 50 VIDEO_SOURCE_SEL, black ? GEN_RGB : NORMAL_PATH); 51} 52 53static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 54{ 55 struct arm_smccc_res res; 56 57 /* 58 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 59 * output. This bit can only be controlled in ARM supervisor mode. 60 * The ARM trusted firmware provides an API for the HDMI driver to set 61 * this control bit to enable HDMI output in supervisor mode. 62 */ 63 if (hdmi->conf && hdmi->conf->tz_disabled) 64 regmap_update_bits(hdmi->sys_regmap, 65 hdmi->sys_offset + HDMI_SYS_CFG20, 66 0x80008005, enable ? 0x80000005 : 0x8000); 67 else 68 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 69 0x80000000, 0, 0, 0, 0, 0, &res); 70 71 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 72 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 73 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 74 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 75} 76 77static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 78{ 79 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 80 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 81} 82 83static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 84{ 85 regmap_set_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO); 86} 87 88static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 89{ 90 regmap_clear_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO); 91} 92 93static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 94{ 95 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 96 HDMI_RST, HDMI_RST); 97 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 98 HDMI_RST, 0); 99 regmap_clear_bits(hdmi->regs, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 100 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 101 ANLG_ON, ANLG_ON); 102} 103 104static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 105{ 106 regmap_update_bits(hdmi->regs, GRL_CFG2, CFG2_NOTICE_EN, 107 enable_notice ? CFG2_NOTICE_EN : 0); 108} 109 110static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 111{ 112 regmap_write(hdmi->regs, GRL_INT_MASK, int_mask); 113} 114 115static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 116{ 117 regmap_update_bits(hdmi->regs, GRL_CFG1, CFG1_DVI, enable ? CFG1_DVI : 0); 118} 119 120static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 121 u8 len) 122{ 123 u32 ctrl_reg = GRL_CTRL; 124 int i; 125 u8 *frame_data; 126 enum hdmi_infoframe_type frame_type; 127 u8 frame_ver; 128 u8 frame_len; 129 u8 checksum; 130 int ctrl_frame_en = 0; 131 132 frame_type = *buffer++; 133 frame_ver = *buffer++; 134 frame_len = *buffer++; 135 checksum = *buffer++; 136 frame_data = buffer; 137 138 dev_dbg(hdmi->dev, 139 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 140 frame_type, frame_ver, frame_len, checksum); 141 142 switch (frame_type) { 143 case HDMI_INFOFRAME_TYPE_AVI: 144 ctrl_frame_en = CTRL_AVI_EN; 145 ctrl_reg = GRL_CTRL; 146 break; 147 case HDMI_INFOFRAME_TYPE_SPD: 148 ctrl_frame_en = CTRL_SPD_EN; 149 ctrl_reg = GRL_CTRL; 150 break; 151 case HDMI_INFOFRAME_TYPE_AUDIO: 152 ctrl_frame_en = CTRL_AUDIO_EN; 153 ctrl_reg = GRL_CTRL; 154 break; 155 case HDMI_INFOFRAME_TYPE_VENDOR: 156 ctrl_frame_en = VS_EN; 157 ctrl_reg = GRL_ACP_ISRC_CTRL; 158 break; 159 default: 160 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); 161 return; 162 } 163 regmap_clear_bits(hdmi->regs, ctrl_reg, ctrl_frame_en); 164 regmap_write(hdmi->regs, GRL_INFOFRM_TYPE, frame_type); 165 regmap_write(hdmi->regs, GRL_INFOFRM_VER, frame_ver); 166 regmap_write(hdmi->regs, GRL_INFOFRM_LNG, frame_len); 167 168 regmap_write(hdmi->regs, GRL_IFM_PORT, checksum); 169 for (i = 0; i < frame_len; i++) 170 regmap_write(hdmi->regs, GRL_IFM_PORT, frame_data[i]); 171 172 regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en); 173} 174 175static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 176{ 177 regmap_update_bits(hdmi->regs, GRL_SHIFT_R2, 178 AUDIO_PACKET_OFF, enable ? 0 : AUDIO_PACKET_OFF); 179} 180 181static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 182{ 183 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 184 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 185 usleep_range(2000, 4000); 186 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 187 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 188} 189 190static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 191{ 192 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 193 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 194 COLOR_8BIT_MODE); 195} 196 197static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 198{ 199 regmap_clear_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE); 200 usleep_range(2000, 4000); 201 regmap_set_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE); 202} 203 204static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 205{ 206 regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET, 207 CFG4_AV_UNMUTE_EN); 208 usleep_range(2000, 4000); 209 regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET, 210 CFG4_AV_UNMUTE_SET); 211} 212 213static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 214{ 215 regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, CTS_CTRL_SOFT, 216 on ? 0 : CTS_CTRL_SOFT); 217} 218 219static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 220 bool enable) 221{ 222 regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, NCTS_WRI_ANYTIME, 223 enable ? NCTS_WRI_ANYTIME : 0); 224} 225 226static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 227 struct drm_display_mode *mode) 228{ 229 regmap_clear_bits(hdmi->regs, GRL_CFG4, CFG4_MHL_MODE); 230 231 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 232 mode->clock == 74250 && 233 mode->vdisplay == 1080) 234 regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL); 235 else 236 regmap_set_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL); 237} 238 239static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 240 enum hdmi_aud_channel_swap_type swap) 241{ 242 u8 swap_bit; 243 244 switch (swap) { 245 case HDMI_AUD_SWAP_LR: 246 swap_bit = LR_SWAP; 247 break; 248 case HDMI_AUD_SWAP_LFE_CC: 249 swap_bit = LFE_CC_SWAP; 250 break; 251 case HDMI_AUD_SWAP_LSRS: 252 swap_bit = LSRS_SWAP; 253 break; 254 case HDMI_AUD_SWAP_RLS_RRS: 255 swap_bit = RLS_RRS_SWAP; 256 break; 257 case HDMI_AUD_SWAP_LR_STATUS: 258 swap_bit = LR_STATUS_SWAP; 259 break; 260 default: 261 swap_bit = LFE_CC_SWAP; 262 break; 263 } 264 regmap_update_bits(hdmi->regs, GRL_CH_SWAP, 0xff, swap_bit); 265} 266 267static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 268 enum hdmi_audio_sample_size bit_num) 269{ 270 u32 val; 271 272 switch (bit_num) { 273 case HDMI_AUDIO_SAMPLE_SIZE_16: 274 val = AOUT_16BIT; 275 break; 276 case HDMI_AUDIO_SAMPLE_SIZE_20: 277 val = AOUT_20BIT; 278 break; 279 case HDMI_AUDIO_SAMPLE_SIZE_24: 280 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 281 val = AOUT_24BIT; 282 break; 283 } 284 285 regmap_update_bits(hdmi->regs, GRL_AOUT_CFG, AOUT_BNUM_SEL_MASK, val); 286} 287 288static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 289 enum hdmi_aud_i2s_fmt i2s_fmt) 290{ 291 u32 val; 292 293 regmap_read(hdmi->regs, GRL_CFG0, &val); 294 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 295 296 switch (i2s_fmt) { 297 case HDMI_I2S_MODE_RJT_24BIT: 298 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 299 break; 300 case HDMI_I2S_MODE_RJT_16BIT: 301 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 302 break; 303 case HDMI_I2S_MODE_LJT_24BIT: 304 default: 305 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 306 break; 307 case HDMI_I2S_MODE_LJT_16BIT: 308 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 309 break; 310 case HDMI_I2S_MODE_I2S_24BIT: 311 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 312 break; 313 case HDMI_I2S_MODE_I2S_16BIT: 314 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 315 break; 316 } 317 regmap_write(hdmi->regs, GRL_CFG0, val); 318} 319 320static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 321{ 322 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 323 u8 val; 324 325 /* Disable high bitrate, set DST packet normal/double */ 326 regmap_clear_bits(hdmi->regs, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 327 328 if (dst) 329 val = DST_NORMAL_DOUBLE | SACD_DST; 330 else 331 val = 0; 332 333 regmap_update_bits(hdmi->regs, GRL_AUDIO_CFG, mask, val); 334} 335 336static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 337 enum hdmi_aud_channel_type channel_type, 338 u8 channel_count) 339{ 340 unsigned int ch_switch; 341 u8 i2s_uv; 342 343 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 344 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 345 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 346 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 347 348 if (channel_count == 2) { 349 i2s_uv = I2S_UV_CH_EN(0); 350 } else if (channel_count == 3 || channel_count == 4) { 351 if (channel_count == 4 && 352 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 353 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 354 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 355 else 356 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 357 } else if (channel_count == 6 || channel_count == 5) { 358 if (channel_count == 6 && 359 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 360 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 361 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 362 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 363 } else { 364 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 365 I2S_UV_CH_EN(0); 366 } 367 } else if (channel_count == 8 || channel_count == 7) { 368 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 369 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 370 } else { 371 i2s_uv = I2S_UV_CH_EN(0); 372 } 373 374 regmap_write(hdmi->regs, GRL_CH_SW0, ch_switch & 0xff); 375 regmap_write(hdmi->regs, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 376 regmap_write(hdmi->regs, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 377 regmap_write(hdmi->regs, GRL_I2S_UV, i2s_uv); 378} 379 380static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 381 enum hdmi_aud_input_type input_type) 382{ 383 u32 val; 384 385 regmap_read(hdmi->regs, GRL_CFG1, &val); 386 if (input_type == HDMI_AUD_INPUT_I2S && 387 (val & CFG1_SPDIF) == CFG1_SPDIF) { 388 val &= ~CFG1_SPDIF; 389 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 390 (val & CFG1_SPDIF) == 0) { 391 val |= CFG1_SPDIF; 392 } 393 regmap_write(hdmi->regs, GRL_CFG1, val); 394} 395 396static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 397 u8 *channel_status) 398{ 399 int i; 400 401 for (i = 0; i < 5; i++) { 402 regmap_write(hdmi->regs, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 403 regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, channel_status[i]); 404 regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, channel_status[i]); 405 } 406 for (; i < 24; i++) { 407 regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, 0); 408 regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, 0); 409 } 410} 411 412static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 413{ 414 u32 val; 415 416 regmap_read(hdmi->regs, GRL_MIX_CTRL, &val); 417 if (val & MIX_CTRL_SRC_EN) { 418 val &= ~MIX_CTRL_SRC_EN; 419 regmap_write(hdmi->regs, GRL_MIX_CTRL, val); 420 usleep_range(255, 512); 421 val |= MIX_CTRL_SRC_EN; 422 regmap_write(hdmi->regs, GRL_MIX_CTRL, val); 423 } 424} 425 426static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 427{ 428 u32 val; 429 430 regmap_read(hdmi->regs, GRL_MIX_CTRL, &val); 431 val &= ~MIX_CTRL_SRC_EN; 432 regmap_write(hdmi->regs, GRL_MIX_CTRL, val); 433 regmap_write(hdmi->regs, GRL_SHIFT_L1, 0x00); 434} 435 436static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 437 enum hdmi_aud_mclk mclk) 438{ 439 u32 val; 440 441 regmap_read(hdmi->regs, GRL_CFG5, &val); 442 val &= CFG5_CD_RATIO_MASK; 443 444 switch (mclk) { 445 case HDMI_AUD_MCLK_128FS: 446 val |= CFG5_FS128; 447 break; 448 case HDMI_AUD_MCLK_256FS: 449 val |= CFG5_FS256; 450 break; 451 case HDMI_AUD_MCLK_384FS: 452 val |= CFG5_FS384; 453 break; 454 case HDMI_AUD_MCLK_512FS: 455 val |= CFG5_FS512; 456 break; 457 case HDMI_AUD_MCLK_768FS: 458 val |= CFG5_FS768; 459 break; 460 default: 461 val |= CFG5_FS256; 462 break; 463 } 464 regmap_write(hdmi->regs, GRL_CFG5, val); 465} 466 467static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 468 unsigned int cts) 469{ 470 unsigned char val[NCTS_BYTES]; 471 int i; 472 473 regmap_write(hdmi->regs, GRL_NCTS, 0); 474 regmap_write(hdmi->regs, GRL_NCTS, 0); 475 regmap_write(hdmi->regs, GRL_NCTS, 0); 476 memset(val, 0, sizeof(val)); 477 478 val[0] = (cts >> 24) & 0xff; 479 val[1] = (cts >> 16) & 0xff; 480 val[2] = (cts >> 8) & 0xff; 481 val[3] = cts & 0xff; 482 483 val[4] = (n >> 16) & 0xff; 484 val[5] = (n >> 8) & 0xff; 485 val[6] = n & 0xff; 486 487 for (i = 0; i < NCTS_BYTES; i++) 488 regmap_write(hdmi->regs, GRL_NCTS, val[i]); 489} 490 491static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 492 unsigned int sample_rate, 493 unsigned int clock) 494{ 495 unsigned int n, cts; 496 497 mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts); 498 499 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 500 __func__, sample_rate, clock, n, cts); 501 502 regmap_update_bits(hdmi->regs, DUMMY_304, AUDIO_I2S_NCTS_SEL, AUDIO_I2S_NCTS_SEL_64); 503 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 504} 505 506static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 507{ 508 switch (channel_type) { 509 case HDMI_AUD_CHAN_TYPE_1_0: 510 case HDMI_AUD_CHAN_TYPE_1_1: 511 case HDMI_AUD_CHAN_TYPE_2_0: 512 return 2; 513 case HDMI_AUD_CHAN_TYPE_2_1: 514 case HDMI_AUD_CHAN_TYPE_3_0: 515 return 3; 516 case HDMI_AUD_CHAN_TYPE_3_1: 517 case HDMI_AUD_CHAN_TYPE_4_0: 518 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 519 return 4; 520 case HDMI_AUD_CHAN_TYPE_4_1: 521 case HDMI_AUD_CHAN_TYPE_5_0: 522 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 523 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 524 return 5; 525 case HDMI_AUD_CHAN_TYPE_5_1: 526 case HDMI_AUD_CHAN_TYPE_6_0: 527 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 528 case HDMI_AUD_CHAN_TYPE_6_0_CS: 529 case HDMI_AUD_CHAN_TYPE_6_0_CH: 530 case HDMI_AUD_CHAN_TYPE_6_0_OH: 531 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 532 return 6; 533 case HDMI_AUD_CHAN_TYPE_6_1: 534 case HDMI_AUD_CHAN_TYPE_6_1_CS: 535 case HDMI_AUD_CHAN_TYPE_6_1_CH: 536 case HDMI_AUD_CHAN_TYPE_6_1_OH: 537 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 538 case HDMI_AUD_CHAN_TYPE_7_0: 539 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 540 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 541 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 542 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 543 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 544 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 545 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 546 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 547 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 548 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 549 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 550 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 551 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 552 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 553 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 554 return 7; 555 case HDMI_AUD_CHAN_TYPE_7_1: 556 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 557 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 558 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 559 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 560 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 561 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 562 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 563 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 564 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 565 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 566 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 567 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 568 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 569 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 570 return 8; 571 default: 572 return 2; 573 } 574} 575 576static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 577{ 578 unsigned long rate; 579 int ret; 580 581 /* The DPI driver already should have set TVDPLL to the correct rate */ 582 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 583 if (ret) { 584 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 585 ret); 586 return ret; 587 } 588 589 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 590 591 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 592 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 593 rate); 594 else 595 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 596 597 mtk_hdmi_hw_config_sys(hdmi); 598 mtk_hdmi_hw_set_deep_color_mode(hdmi); 599 return 0; 600} 601 602static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 603 struct drm_display_mode *mode) 604{ 605 mtk_hdmi_hw_reset(hdmi); 606 mtk_hdmi_hw_enable_notice(hdmi, true); 607 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 608 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 609 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 610 611 mtk_hdmi_hw_msic_setting(hdmi, mode); 612} 613 614 615static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 616{ 617 enum hdmi_aud_channel_type chan_type; 618 u8 chan_count; 619 bool dst; 620 621 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 622 regmap_set_bits(hdmi->regs, GRL_MIX_CTRL, MIX_CTRL_FLAT); 623 624 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 625 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 626 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 627 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 628 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 629 } 630 631 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 632 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 633 634 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 635 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 636 mtk_hdmi_hw_audio_config(hdmi, dst); 637 638 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 639 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 640 else 641 chan_type = hdmi->aud_param.aud_input_chan_type; 642 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 643 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 644 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 645} 646 647static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 648 struct drm_display_mode *display_mode) 649{ 650 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 651 652 mtk_hdmi_hw_ncts_enable(hdmi, false); 653 mtk_hdmi_hw_aud_src_disable(hdmi); 654 regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_ACLK_INV); 655 656 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 657 switch (sample_rate) { 658 case 32000: 659 case 44100: 660 case 48000: 661 case 88200: 662 case 96000: 663 break; 664 default: 665 return -EINVAL; 666 } 667 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 668 } else { 669 switch (sample_rate) { 670 case 32000: 671 case 44100: 672 case 48000: 673 break; 674 default: 675 return -EINVAL; 676 } 677 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 678 } 679 680 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 681 682 mtk_hdmi_hw_aud_src_reenable(hdmi); 683 return 0; 684} 685 686static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 687 struct drm_display_mode *display_mode) 688{ 689 mtk_hdmi_hw_aud_mute(hdmi); 690 mtk_hdmi_hw_send_aud_packet(hdmi, false); 691 692 mtk_hdmi_aud_set_input(hdmi); 693 mtk_hdmi_aud_set_src(hdmi, display_mode); 694 mtk_hdmi_hw_aud_set_channel_status(hdmi, 695 hdmi->aud_param.codec_params.iec.status); 696 697 usleep_range(50, 100); 698 699 mtk_hdmi_hw_ncts_enable(hdmi, true); 700 mtk_hdmi_hw_send_aud_packet(hdmi, true); 701 mtk_hdmi_hw_aud_unmute(hdmi); 702 return 0; 703} 704 705static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 706 struct drm_display_mode *mode) 707{ 708 struct hdmi_avi_infoframe frame; 709 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 710 ssize_t err; 711 712 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 713 hdmi->curr_conn, mode); 714 if (err < 0) { 715 dev_err(hdmi->dev, 716 "Failed to get AVI infoframe from mode: %zd\n", err); 717 return err; 718 } 719 720 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 721 if (err < 0) { 722 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 723 return err; 724 } 725 726 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 727 return 0; 728} 729 730static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi) 731{ 732 struct drm_bridge *bridge = &hdmi->bridge; 733 struct hdmi_spd_infoframe frame; 734 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; 735 ssize_t err; 736 737 err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product); 738 if (err < 0) { 739 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 740 err); 741 return err; 742 } 743 744 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 745 if (err < 0) { 746 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 747 return err; 748 } 749 750 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 751 return 0; 752} 753 754static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 755{ 756 struct hdmi_audio_infoframe frame; 757 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 758 ssize_t err; 759 760 err = hdmi_audio_infoframe_init(&frame); 761 if (err < 0) { 762 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 763 err); 764 return err; 765 } 766 767 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 768 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 769 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 770 frame.channels = mtk_hdmi_aud_get_chnl_count( 771 hdmi->aud_param.aud_input_chan_type); 772 773 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 774 if (err < 0) { 775 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 776 err); 777 return err; 778 } 779 780 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 781 return 0; 782} 783 784static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 785 struct drm_display_mode *mode) 786{ 787 struct hdmi_vendor_infoframe frame; 788 u8 buffer[10]; 789 ssize_t err; 790 791 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 792 hdmi->curr_conn, mode); 793 if (err) { 794 dev_err(hdmi->dev, 795 "Failed to get vendor infoframe from mode: %zd\n", err); 796 return err; 797 } 798 799 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 800 if (err < 0) { 801 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 802 err); 803 return err; 804 } 805 806 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 807 return 0; 808} 809 810static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 811{ 812 mtk_hdmi_hw_send_aud_packet(hdmi, true); 813 hdmi->audio_enable = true; 814} 815 816static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 817{ 818 mtk_hdmi_hw_send_aud_packet(hdmi, false); 819 hdmi->audio_enable = false; 820} 821 822static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 823 struct drm_display_mode *mode) 824{ 825 int ret; 826 827 mtk_hdmi_hw_vid_black(hdmi, true); 828 mtk_hdmi_hw_aud_mute(hdmi); 829 mtk_hdmi_hw_send_av_mute(hdmi); 830 phy_power_off(hdmi->phy); 831 832 ret = mtk_hdmi_video_change_vpll(hdmi, 833 mode->clock * 1000); 834 if (ret) { 835 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 836 return ret; 837 } 838 mtk_hdmi_video_set_display_mode(hdmi, mode); 839 840 phy_power_on(hdmi->phy); 841 mtk_hdmi_aud_output_config(hdmi, mode); 842 843 mtk_hdmi_hw_vid_black(hdmi, false); 844 mtk_hdmi_hw_aud_unmute(hdmi); 845 mtk_hdmi_hw_send_av_unmute(hdmi); 846 847 return 0; 848} 849 850static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 851 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 852 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 853 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 854 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 855}; 856 857static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 858{ 859 int ret; 860 861 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 862 if (ret) 863 return ret; 864 865 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 866 if (ret) { 867 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 868 return ret; 869 } 870 871 return 0; 872} 873 874static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 875{ 876 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 877 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 878} 879 880static enum drm_connector_status 881mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) 882{ 883 bool connected; 884 885 mutex_lock(&hdmi->update_plugged_status_lock); 886 connected = mtk_cec_hpd_high(hdmi->cec_dev); 887 if (hdmi->plugged_cb && hdmi->codec_dev) 888 hdmi->plugged_cb(hdmi->codec_dev, connected); 889 mutex_unlock(&hdmi->update_plugged_status_lock); 890 891 return connected ? 892 connector_status_connected : connector_status_disconnected; 893} 894 895static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi) 896{ 897 return mtk_hdmi_update_plugged_status(hdmi); 898} 899 900static enum drm_mode_status 901mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 902 const struct drm_display_info *info, 903 const struct drm_display_mode *mode) 904{ 905 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 906 907 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 908 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 909 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 910 911 if (hdmi->conf) { 912 if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode)) 913 return MODE_BAD; 914 915 if (hdmi->conf->max_mode_clock && 916 mode->clock > hdmi->conf->max_mode_clock) 917 return MODE_CLOCK_HIGH; 918 } 919 920 if (mode->clock < 27000) 921 return MODE_CLOCK_LOW; 922 if (mode->clock > 297000) 923 return MODE_CLOCK_HIGH; 924 925 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 926} 927 928static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 929{ 930 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 931 932 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) { 933 static enum drm_connector_status status; 934 935 status = mtk_hdmi_detect(hdmi); 936 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 937 drm_bridge_hpd_notify(&hdmi->bridge, status); 938 } 939} 940 941/* 942 * Bridge callbacks 943 */ 944 945static enum drm_connector_status 946mtk_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 947{ 948 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 949 950 return mtk_hdmi_detect(hdmi); 951} 952 953static const struct drm_edid *mtk_hdmi_bridge_edid_read(struct drm_bridge *bridge, 954 struct drm_connector *connector) 955{ 956 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 957 const struct drm_edid *drm_edid; 958 959 if (!hdmi->ddc_adpt) 960 return NULL; 961 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_adpt); 962 if (drm_edid) { 963 /* 964 * FIXME: This should use !connector->display_info.has_audio (or 965 * !connector->display_info.is_hdmi) from a path that has read 966 * the EDID and called drm_edid_connector_update(). 967 */ 968 const struct edid *edid = drm_edid_raw(drm_edid); 969 970 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 971 } 972 973 return drm_edid; 974} 975 976static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge, 977 struct drm_encoder *encoder, 978 enum drm_bridge_attach_flags flags) 979{ 980 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 981 int ret; 982 983 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { 984 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n", 985 __func__); 986 return -EINVAL; 987 } 988 989 if (hdmi->next_bridge) { 990 ret = drm_bridge_attach(encoder, hdmi->next_bridge, 991 bridge, flags); 992 if (ret) 993 return ret; 994 } 995 996 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 997 998 return 0; 999} 1000 1001static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 1002 struct drm_atomic_state *state) 1003{ 1004 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1005 1006 if (!hdmi->enabled) 1007 return; 1008 1009 phy_power_off(hdmi->phy); 1010 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1011 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1012 1013 hdmi->curr_conn = NULL; 1014 1015 hdmi->enabled = false; 1016} 1017 1018static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, 1019 struct drm_atomic_state *state) 1020{ 1021 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1022 1023 if (!hdmi->powered) 1024 return; 1025 1026 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1027 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1028 1029 hdmi->powered = false; 1030} 1031 1032static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1033 struct drm_atomic_state *state) 1034{ 1035 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1036 1037 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1038 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1039 1040 hdmi->powered = true; 1041} 1042 1043static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1044 struct drm_display_mode *mode) 1045{ 1046 mtk_hdmi_setup_audio_infoframe(hdmi); 1047 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1048 mtk_hdmi_setup_spd_infoframe(hdmi); 1049 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1050 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1051} 1052 1053static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 1054 struct drm_atomic_state *state) 1055{ 1056 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1057 1058 /* Retrieve the connector through the atomic state. */ 1059 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, 1060 bridge->encoder); 1061 1062 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1063 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1064 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1065 phy_power_on(hdmi->phy); 1066 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1067 1068 hdmi->enabled = true; 1069} 1070 1071static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1072 .mode_valid = mtk_hdmi_bridge_mode_valid, 1073 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1074 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1075 .atomic_reset = drm_atomic_helper_bridge_reset, 1076 .attach = mtk_hdmi_bridge_attach, 1077 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1078 .atomic_disable = mtk_hdmi_bridge_atomic_disable, 1079 .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable, 1080 .mode_set = mtk_hdmi_bridge_mode_set, 1081 .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable, 1082 .atomic_enable = mtk_hdmi_bridge_atomic_enable, 1083 .detect = mtk_hdmi_bridge_detect, 1084 .edid_read = mtk_hdmi_bridge_edid_read, 1085}; 1086 1087/* 1088 * HDMI audio codec callbacks 1089 */ 1090 1091static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1092 struct hdmi_codec_daifmt *daifmt, 1093 struct hdmi_codec_params *params) 1094{ 1095 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1096 1097 if (!hdmi->audio_enable) { 1098 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1099 return -EINVAL; 1100 } 1101 1102 mtk_hdmi_audio_params(hdmi, daifmt, params); 1103 mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1104 1105 return 0; 1106} 1107 1108static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1109{ 1110 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1111 1112 mtk_hdmi_audio_enable(hdmi); 1113 1114 return 0; 1115} 1116 1117static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1118{ 1119 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1120 1121 mtk_hdmi_audio_disable(hdmi); 1122} 1123 1124static int 1125mtk_hdmi_audio_mute(struct device *dev, void *data, 1126 bool enable, int direction) 1127{ 1128 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1129 1130 if (enable) 1131 mtk_hdmi_hw_aud_mute(hdmi); 1132 else 1133 mtk_hdmi_hw_aud_unmute(hdmi); 1134 1135 return 0; 1136} 1137 1138static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, 1139 hdmi_codec_plugged_cb fn, 1140 struct device *codec_dev) 1141{ 1142 struct mtk_hdmi *hdmi = data; 1143 1144 mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev); 1145 mtk_hdmi_update_plugged_status(hdmi); 1146 1147 return 0; 1148} 1149 1150static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1151 .hw_params = mtk_hdmi_audio_hw_params, 1152 .audio_startup = mtk_hdmi_audio_startup, 1153 .audio_shutdown = mtk_hdmi_audio_shutdown, 1154 .mute_stream = mtk_hdmi_audio_mute, 1155 .get_eld = mtk_hdmi_audio_get_eld, 1156 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, 1157}; 1158 1159static int mtk_hdmi_probe(struct platform_device *pdev) 1160{ 1161 struct mtk_hdmi *hdmi; 1162 int ret; 1163 1164 hdmi = mtk_hdmi_common_probe(pdev); 1165 if (IS_ERR(hdmi)) 1166 return PTR_ERR(hdmi); 1167 1168 if (!hdmi->cec_dev) 1169 return dev_err_probe(hdmi->dev, -ENODEV, "CEC is required by HDMIv1\n"); 1170 1171 ret = mtk_hdmi_clk_enable_audio(hdmi); 1172 if (ret) 1173 return dev_err_probe(hdmi->dev, ret, 1174 "Failed to enable audio clocks\n"); 1175 1176 return 0; 1177} 1178 1179static void mtk_hdmi_remove(struct platform_device *pdev) 1180{ 1181 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1182 1183 mtk_hdmi_clk_disable_audio(hdmi); 1184} 1185 1186static __maybe_unused int mtk_hdmi_suspend(struct device *dev) 1187{ 1188 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1189 1190 mtk_hdmi_clk_disable_audio(hdmi); 1191 1192 return 0; 1193} 1194 1195static __maybe_unused int mtk_hdmi_resume(struct device *dev) 1196{ 1197 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1198 1199 return mtk_hdmi_clk_enable_audio(hdmi); 1200} 1201 1202static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume); 1203 1204static const struct mtk_hdmi_ver_conf mtk_hdmi_v1_ver_conf = { 1205 .bridge_funcs = &mtk_hdmi_bridge_funcs, 1206 .codec_ops = &mtk_hdmi_audio_codec_ops, 1207 .mtk_hdmi_clock_names = mtk_hdmi_clk_names, 1208 .num_clocks = ARRAY_SIZE(mtk_hdmi_clk_names) 1209}; 1210 1211static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = { 1212 .tz_disabled = true, 1213 .ver_conf = &mtk_hdmi_v1_ver_conf 1214}; 1215 1216static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = { 1217 .cea_modes_only = true, 1218 .max_mode_clock = 148500, 1219 .ver_conf = &mtk_hdmi_v1_ver_conf 1220}; 1221 1222static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8173 = { 1223 .ver_conf = &mtk_hdmi_v1_ver_conf 1224}; 1225 1226static const struct of_device_id mtk_hdmi_of_ids[] = { 1227 { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 }, 1228 { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 }, 1229 { .compatible = "mediatek,mt8173-hdmi", .data = &mtk_hdmi_conf_mt8173 }, 1230 { /* sentinel */ } 1231}; 1232MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids); 1233 1234static struct platform_driver mtk_hdmi_driver = { 1235 .probe = mtk_hdmi_probe, 1236 .remove = mtk_hdmi_remove, 1237 .driver = { 1238 .name = "mediatek-drm-hdmi", 1239 .of_match_table = mtk_hdmi_of_ids, 1240 .pm = &mtk_hdmi_pm_ops, 1241 }, 1242}; 1243module_platform_driver(mtk_hdmi_driver); 1244 1245MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1246MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1247MODULE_LICENSE("GPL v2"); 1248MODULE_IMPORT_NS("DRM_MTK_HDMI_V1"); 1249MODULE_IMPORT_NS("DRM_MTK_HDMI");
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