mtk_dp.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2019-2022 MediaTek Inc.
   4 * Copyright (c) 2022 BayLibre
   5 */
   6
   7#include <drm/display/drm_dp_aux_bus.h>
   8#include <drm/display/drm_dp.h>
   9#include <drm/display/drm_dp_helper.h>
  10#include <drm/drm_atomic_helper.h>
  11#include <drm/drm_bridge.h>
  12#include <drm/drm_crtc.h>
  13#include <drm/drm_edid.h>
  14#include <drm/drm_of.h>
  15#include <drm/drm_panel.h>
  16#include <drm/drm_print.h>
  17#include <drm/drm_probe_helper.h>
  18#include <linux/arm-smccc.h>
  19#include <linux/clk.h>
  20#include <linux/delay.h>
  21#include <linux/errno.h>
  22#include <linux/kernel.h>
  23#include <linux/media-bus-format.h>
  24#include <linux/nvmem-consumer.h>
  25#include <linux/of.h>
  26#include <linux/of_irq.h>
  27#include <linux/of_platform.h>
  28#include <linux/phy/phy.h>
  29#include <linux/platform_device.h>
  30#include <linux/pm_runtime.h>
  31#include <linux/regmap.h>
  32#include <linux/soc/mediatek/mtk_sip_svc.h>
  33#include <sound/hdmi-codec.h>
  34#include <video/videomode.h>
  35
  36#include "mtk_dp_reg.h"
  37
  38#define MTK_DP_SIP_CONTROL_AARCH32	MTK_SIP_SMC_CMD(0x523)
  39#define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE	(BIT(0) | BIT(5))
  40#define MTK_DP_SIP_ATF_VIDEO_UNMUTE	BIT(5)
  41
  42#define MTK_DP_THREAD_CABLE_STATE_CHG	BIT(0)
  43#define MTK_DP_THREAD_HPD_EVENT		BIT(1)
  44
  45#define MTK_DP_4P1T 4
  46#define MTK_DP_HDE 2
  47#define MTK_DP_PIX_PER_ADDR 2
  48#define MTK_DP_AUX_WAIT_REPLY_COUNT 20
  49#define MTK_DP_TBC_BUF_READ_START_ADDR 0x8
  50#define MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY 5
  51#define MTK_DP_TRAIN_DOWNSCALE_RETRY 10
  52#define MTK_DP_VERSION 0x11
  53#define MTK_DP_SDP_AUI 0x4
  54
  55enum {
  56	MTK_DP_CAL_GLB_BIAS_TRIM = 0,
  57	MTK_DP_CAL_CLKTX_IMPSE,
  58	MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0,
  59	MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1,
  60	MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2,
  61	MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3,
  62	MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0,
  63	MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1,
  64	MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2,
  65	MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3,
  66	MTK_DP_CAL_MAX,
  67};
  68
  69struct mtk_dp_train_info {
  70	bool sink_ssc;
  71	bool cable_plugged_in;
  72	/* link_rate is in multiple of 0.27Gbps */
  73	int link_rate;
  74	int lane_count;
  75	unsigned int channel_eq_pattern;
  76};
  77
  78struct mtk_dp_audio_cfg {
  79	bool detect_monitor;
  80	int sad_count;
  81	int sample_rate;
  82	int word_length_bits;
  83	int channels;
  84};
  85
  86struct mtk_dp_info {
  87	enum dp_pixelformat format;
  88	struct videomode vm;
  89	struct mtk_dp_audio_cfg audio_cur_cfg;
  90};
  91
  92struct mtk_dp_efuse_fmt {
  93	unsigned short idx;
  94	unsigned short shift;
  95	unsigned short mask;
  96	unsigned short min_val;
  97	unsigned short max_val;
  98	unsigned short default_val;
  99};
 100
 101struct mtk_dp {
 102	bool enabled;
 103	bool need_debounce;
 104	int irq;
 105	u8 max_lanes;
 106	u8 max_linkrate;
 107	u8 rx_cap[DP_RECEIVER_CAP_SIZE];
 108	u32 cal_data[MTK_DP_CAL_MAX];
 109	u32 irq_thread_handle;
 110	/* irq_thread_lock is used to protect irq_thread_handle */
 111	spinlock_t irq_thread_lock;
 112
 113	struct device *dev;
 114	struct drm_bridge bridge;
 115	struct drm_bridge *next_bridge;
 116	struct drm_connector *conn;
 117	struct drm_device *drm_dev;
 118	struct drm_dp_aux aux;
 119
 120	const struct mtk_dp_data *data;
 121	struct mtk_dp_info info;
 122	struct mtk_dp_train_info train_info;
 123
 124	struct platform_device *phy_dev;
 125	struct phy *phy;
 126	struct regmap *regs;
 127	struct timer_list debounce_timer;
 128
 129	/* For audio */
 130	bool audio_enable;
 131	hdmi_codec_plugged_cb plugged_cb;
 132	struct platform_device *audio_pdev;
 133
 134	struct device *codec_dev;
 135	/* protect the plugged_cb as it's used in both bridge ops and audio */
 136	struct mutex update_plugged_status_lock;
 137};
 138
 139struct mtk_dp_data {
 140	int bridge_type;
 141	unsigned int smc_cmd;
 142	const struct mtk_dp_efuse_fmt *efuse_fmt;
 143	bool audio_supported;
 144	bool audio_pkt_in_hblank_area;
 145	u16 audio_m_div2_bit;
 146};
 147
 148static const struct mtk_dp_efuse_fmt mt8188_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
 149	[MTK_DP_CAL_GLB_BIAS_TRIM] = {
 150		.idx = 0,
 151		.shift = 10,
 152		.mask = 0x1f,
 153		.min_val = 1,
 154		.max_val = 0x1e,
 155		.default_val = 0xf,
 156	},
 157	[MTK_DP_CAL_CLKTX_IMPSE] = {
 158		.idx = 0,
 159		.shift = 15,
 160		.mask = 0xf,
 161		.min_val = 1,
 162		.max_val = 0xe,
 163		.default_val = 0x8,
 164	},
 165	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {
 166		.idx = 1,
 167		.shift = 0,
 168		.mask = 0xf,
 169		.min_val = 1,
 170		.max_val = 0xe,
 171		.default_val = 0x8,
 172	},
 173	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {
 174		.idx = 1,
 175		.shift = 8,
 176		.mask = 0xf,
 177		.min_val = 1,
 178		.max_val = 0xe,
 179		.default_val = 0x8,
 180	},
 181	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {
 182		.idx = 1,
 183		.shift = 16,
 184		.mask = 0xf,
 185		.min_val = 1,
 186		.max_val = 0xe,
 187		.default_val = 0x8,
 188	},
 189	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {
 190		.idx = 1,
 191		.shift = 24,
 192		.mask = 0xf,
 193		.min_val = 1,
 194		.max_val = 0xe,
 195		.default_val = 0x8,
 196	},
 197	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {
 198		.idx = 1,
 199		.shift = 4,
 200		.mask = 0xf,
 201		.min_val = 1,
 202		.max_val = 0xe,
 203		.default_val = 0x8,
 204	},
 205	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {
 206		.idx = 1,
 207		.shift = 12,
 208		.mask = 0xf,
 209		.min_val = 1,
 210		.max_val = 0xe,
 211		.default_val = 0x8,
 212	},
 213	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {
 214		.idx = 1,
 215		.shift = 20,
 216		.mask = 0xf,
 217		.min_val = 1,
 218		.max_val = 0xe,
 219		.default_val = 0x8,
 220	},
 221	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {
 222		.idx = 1,
 223		.shift = 28,
 224		.mask = 0xf,
 225		.min_val = 1,
 226		.max_val = 0xe,
 227		.default_val = 0x8,
 228	},
 229};
 230
 231static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
 232	[MTK_DP_CAL_GLB_BIAS_TRIM] = {
 233		.idx = 3,
 234		.shift = 27,
 235		.mask = 0x1f,
 236		.min_val = 1,
 237		.max_val = 0x1e,
 238		.default_val = 0xf,
 239	},
 240	[MTK_DP_CAL_CLKTX_IMPSE] = {
 241		.idx = 0,
 242		.shift = 9,
 243		.mask = 0xf,
 244		.min_val = 1,
 245		.max_val = 0xe,
 246		.default_val = 0x8,
 247	},
 248	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {
 249		.idx = 2,
 250		.shift = 28,
 251		.mask = 0xf,
 252		.min_val = 1,
 253		.max_val = 0xe,
 254		.default_val = 0x8,
 255	},
 256	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {
 257		.idx = 2,
 258		.shift = 20,
 259		.mask = 0xf,
 260		.min_val = 1,
 261		.max_val = 0xe,
 262		.default_val = 0x8,
 263	},
 264	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {
 265		.idx = 2,
 266		.shift = 12,
 267		.mask = 0xf,
 268		.min_val = 1,
 269		.max_val = 0xe,
 270		.default_val = 0x8,
 271	},
 272	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {
 273		.idx = 2,
 274		.shift = 4,
 275		.mask = 0xf,
 276		.min_val = 1,
 277		.max_val = 0xe,
 278		.default_val = 0x8,
 279	},
 280	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {
 281		.idx = 2,
 282		.shift = 24,
 283		.mask = 0xf,
 284		.min_val = 1,
 285		.max_val = 0xe,
 286		.default_val = 0x8,
 287	},
 288	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {
 289		.idx = 2,
 290		.shift = 16,
 291		.mask = 0xf,
 292		.min_val = 1,
 293		.max_val = 0xe,
 294		.default_val = 0x8,
 295	},
 296	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {
 297		.idx = 2,
 298		.shift = 8,
 299		.mask = 0xf,
 300		.min_val = 1,
 301		.max_val = 0xe,
 302		.default_val = 0x8,
 303	},
 304	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {
 305		.idx = 2,
 306		.shift = 0,
 307		.mask = 0xf,
 308		.min_val = 1,
 309		.max_val = 0xe,
 310		.default_val = 0x8,
 311	},
 312};
 313
 314static const struct mtk_dp_efuse_fmt mt8195_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
 315	[MTK_DP_CAL_GLB_BIAS_TRIM] = {
 316		.idx = 0,
 317		.shift = 27,
 318		.mask = 0x1f,
 319		.min_val = 1,
 320		.max_val = 0x1e,
 321		.default_val = 0xf,
 322	},
 323	[MTK_DP_CAL_CLKTX_IMPSE] = {
 324		.idx = 0,
 325		.shift = 13,
 326		.mask = 0xf,
 327		.min_val = 1,
 328		.max_val = 0xe,
 329		.default_val = 0x8,
 330	},
 331	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] = {
 332		.idx = 1,
 333		.shift = 28,
 334		.mask = 0xf,
 335		.min_val = 1,
 336		.max_val = 0xe,
 337		.default_val = 0x8,
 338	},
 339	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] = {
 340		.idx = 1,
 341		.shift = 20,
 342		.mask = 0xf,
 343		.min_val = 1,
 344		.max_val = 0xe,
 345		.default_val = 0x8,
 346	},
 347	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] = {
 348		.idx = 1,
 349		.shift = 12,
 350		.mask = 0xf,
 351		.min_val = 1,
 352		.max_val = 0xe,
 353		.default_val = 0x8,
 354	},
 355	[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] = {
 356		.idx = 1,
 357		.shift = 4,
 358		.mask = 0xf,
 359		.min_val = 1,
 360		.max_val = 0xe,
 361		.default_val = 0x8,
 362	},
 363	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] = {
 364		.idx = 1,
 365		.shift = 24,
 366		.mask = 0xf,
 367		.min_val = 1,
 368		.max_val = 0xe,
 369		.default_val = 0x8,
 370	},
 371	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] = {
 372		.idx = 1,
 373		.shift = 16,
 374		.mask = 0xf,
 375		.min_val = 1,
 376		.max_val = 0xe,
 377		.default_val = 0x8,
 378	},
 379	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] = {
 380		.idx = 1,
 381		.shift = 8,
 382		.mask = 0xf,
 383		.min_val = 1,
 384		.max_val = 0xe,
 385		.default_val = 0x8,
 386	},
 387	[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] = {
 388		.idx = 1,
 389		.shift = 0,
 390		.mask = 0xf,
 391		.min_val = 1,
 392		.max_val = 0xe,
 393		.default_val = 0x8,
 394	},
 395};
 396
 397static const struct regmap_config mtk_dp_regmap_config = {
 398	.reg_bits = 32,
 399	.val_bits = 32,
 400	.reg_stride = 4,
 401	.max_register = SEC_OFFSET + 0x90,
 402	.name = "mtk-dp-registers",
 403};
 404
 405static struct mtk_dp *mtk_dp_from_bridge(struct drm_bridge *b)
 406{
 407	return container_of(b, struct mtk_dp, bridge);
 408}
 409
 410static u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset)
 411{
 412	u32 read_val;
 413	int ret;
 414
 415	ret = regmap_read(mtk_dp->regs, offset, &read_val);
 416	if (ret) {
 417		dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n",
 418			offset, ret);
 419		return 0;
 420	}
 421
 422	return read_val;
 423}
 424
 425static int mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)
 426{
 427	int ret = regmap_write(mtk_dp->regs, offset, val);
 428
 429	if (ret)
 430		dev_err(mtk_dp->dev,
 431			"Failed to write register 0x%x with value 0x%x\n",
 432			offset, val);
 433	return ret;
 434}
 435
 436static int mtk_dp_update_bits(struct mtk_dp *mtk_dp, u32 offset,
 437			      u32 val, u32 mask)
 438{
 439	int ret = regmap_update_bits(mtk_dp->regs, offset, mask, val);
 440
 441	if (ret)
 442		dev_err(mtk_dp->dev,
 443			"Failed to update register 0x%x with value 0x%x, mask 0x%x\n",
 444			offset, val, mask);
 445	return ret;
 446}
 447
 448static void mtk_dp_bulk_16bit_write(struct mtk_dp *mtk_dp, u32 offset, u8 *buf,
 449				    size_t length)
 450{
 451	int i;
 452
 453	/* 2 bytes per register */
 454	for (i = 0; i < length; i += 2) {
 455		u32 val = buf[i] | (i + 1 < length ? buf[i + 1] << 8 : 0);
 456
 457		if (mtk_dp_write(mtk_dp, offset + i * 2, val))
 458			return;
 459	}
 460}
 461
 462static void mtk_dp_msa_bypass_enable(struct mtk_dp *mtk_dp, bool enable)
 463{
 464	u32 mask = HTOTAL_SEL_DP_ENC0_P0 | VTOTAL_SEL_DP_ENC0_P0 |
 465		   HSTART_SEL_DP_ENC0_P0 | VSTART_SEL_DP_ENC0_P0 |
 466		   HWIDTH_SEL_DP_ENC0_P0 | VHEIGHT_SEL_DP_ENC0_P0 |
 467		   HSP_SEL_DP_ENC0_P0 | HSW_SEL_DP_ENC0_P0 |
 468		   VSP_SEL_DP_ENC0_P0 | VSW_SEL_DP_ENC0_P0;
 469
 470	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3030, enable ? 0 : mask, mask);
 471}
 472
 473static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
 474{
 475	struct drm_display_mode mode;
 476	struct videomode *vm = &mtk_dp->info.vm;
 477
 478	drm_display_mode_from_videomode(vm, &mode);
 479
 480	/* horizontal */
 481	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3010,
 482			   mode.htotal, HTOTAL_SW_DP_ENC0_P0_MASK);
 483	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3018,
 484			   vm->hsync_len + vm->hback_porch,
 485			   HSTART_SW_DP_ENC0_P0_MASK);
 486	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,
 487			   vm->hsync_len, HSW_SW_DP_ENC0_P0_MASK);
 488	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3028,
 489			   0, HSP_SW_DP_ENC0_P0_MASK);
 490	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3020,
 491			   vm->hactive, HWIDTH_SW_DP_ENC0_P0_MASK);
 492
 493	/* vertical */
 494	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3014,
 495			   mode.vtotal, VTOTAL_SW_DP_ENC0_P0_MASK);
 496	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_301C,
 497			   vm->vsync_len + vm->vback_porch,
 498			   VSTART_SW_DP_ENC0_P0_MASK);
 499	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,
 500			   vm->vsync_len, VSW_SW_DP_ENC0_P0_MASK);
 501	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_302C,
 502			   0, VSP_SW_DP_ENC0_P0_MASK);
 503	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3024,
 504			   vm->vactive, VHEIGHT_SW_DP_ENC0_P0_MASK);
 505
 506	/* horizontal */
 507	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3064,
 508			   vm->hactive, HDE_NUM_LAST_DP_ENC0_P0_MASK);
 509	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3154,
 510			   mode.htotal, PGEN_HTOTAL_DP_ENC0_P0_MASK);
 511	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3158,
 512			   vm->hfront_porch,
 513			   PGEN_HSYNC_RISING_DP_ENC0_P0_MASK);
 514	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_315C,
 515			   vm->hsync_len,
 516			   PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
 517	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
 518			   vm->hback_porch + vm->hsync_len,
 519			   PGEN_HFDE_START_DP_ENC0_P0_MASK);
 520	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3164,
 521			   vm->hactive,
 522			   PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
 523
 524	/* vertical */
 525	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3168,
 526			   mode.vtotal,
 527			   PGEN_VTOTAL_DP_ENC0_P0_MASK);
 528	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_316C,
 529			   vm->vfront_porch,
 530			   PGEN_VSYNC_RISING_DP_ENC0_P0_MASK);
 531	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3170,
 532			   vm->vsync_len,
 533			   PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
 534	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
 535			   vm->vback_porch + vm->vsync_len,
 536			   PGEN_VFDE_START_DP_ENC0_P0_MASK);
 537	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3178,
 538			   vm->vactive,
 539			   PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
 540}
 541
 542static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
 543				   enum dp_pixelformat color_format)
 544{
 545	u32 val;
 546	u32 misc0_color;
 547
 548	switch (color_format) {
 549	case DP_PIXELFORMAT_YUV422:
 550		val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;
 551		misc0_color = DP_COLOR_FORMAT_YCbCr422;
 552		break;
 553	case DP_PIXELFORMAT_RGB:
 554		val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
 555		misc0_color = DP_COLOR_FORMAT_RGB;
 556		break;
 557	default:
 558		drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
 559			 color_format);
 560		return -EINVAL;
 561	}
 562
 563	/* update MISC0 */
 564	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
 565			   misc0_color,
 566			   DP_TEST_COLOR_FORMAT_MASK);
 567
 568	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
 569			   val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK);
 570	return 0;
 571}
 572
 573static void mtk_dp_set_color_depth(struct mtk_dp *mtk_dp)
 574{
 575	/* Only support 8 bits currently */
 576	/* Update MISC0 */
 577	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
 578			   DP_MSA_MISC_8_BPC, DP_TEST_BIT_DEPTH_MASK);
 579
 580	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
 581			   VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT,
 582			   VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK);
 583}
 584
 585static void mtk_dp_config_mn_mode(struct mtk_dp *mtk_dp)
 586{
 587	/* 0: hw mode, 1: sw mode */
 588	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
 589			   0, VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK);
 590}
 591
 592static void mtk_dp_set_sram_read_start(struct mtk_dp *mtk_dp, u32 val)
 593{
 594	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
 595			   val, SRAM_START_READ_THRD_DP_ENC0_P0_MASK);
 596}
 597
 598static void mtk_dp_setup_encoder(struct mtk_dp *mtk_dp)
 599{
 600	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
 601			   VIDEO_MN_GEN_EN_DP_ENC0_P0,
 602			   VIDEO_MN_GEN_EN_DP_ENC0_P0);
 603	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040,
 604			   SDP_DOWN_CNT_DP_ENC0_P0_VAL,
 605			   SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK);
 606	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,
 607			   SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL,
 608			   SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);
 609	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3300,
 610			   VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL << 8,
 611			   VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK);
 612	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,
 613			   FIFO_READ_START_POINT_DP_ENC1_P0_VAL << 12,
 614			   FIFO_READ_START_POINT_DP_ENC1_P0_MASK);
 615	mtk_dp_write(mtk_dp, MTK_DP_ENC1_P0_3368, DP_ENC1_P0_3368_VAL);
 616}
 617
 618static void mtk_dp_pg_enable(struct mtk_dp *mtk_dp, bool enable)
 619{
 620	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3038,
 621			   enable ? VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK : 0,
 622			   VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK);
 623	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31B0,
 624			   PGEN_PATTERN_SEL_VAL << 4, PGEN_PATTERN_SEL_MASK);
 625}
 626
 627static void mtk_dp_audio_setup_channels(struct mtk_dp *mtk_dp,
 628					struct mtk_dp_audio_cfg *cfg)
 629{
 630	u32 channel_enable_bits;
 631
 632	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3324,
 633			   AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX,
 634			   AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK);
 635
 636	/* audio channel count change reset */
 637	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4,
 638			   DP_ENC_DUMMY_RW_1, DP_ENC_DUMMY_RW_1);
 639	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304,
 640			   AU_PRTY_REGEN_DP_ENC1_P0_MASK |
 641			   AU_CH_STS_REGEN_DP_ENC1_P0_MASK |
 642			   AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK,
 643			   AU_PRTY_REGEN_DP_ENC1_P0_MASK |
 644			   AU_CH_STS_REGEN_DP_ENC1_P0_MASK |
 645			   AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK);
 646
 647	switch (cfg->channels) {
 648	case 2:
 649		channel_enable_bits = AUDIO_2CH_SEL_DP_ENC0_P0_MASK |
 650				      AUDIO_2CH_EN_DP_ENC0_P0_MASK;
 651		break;
 652	case 8:
 653	default:
 654		channel_enable_bits = AUDIO_8CH_SEL_DP_ENC0_P0_MASK |
 655				      AUDIO_8CH_EN_DP_ENC0_P0_MASK;
 656		break;
 657	}
 658	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088,
 659			   channel_enable_bits | AU_EN_DP_ENC0_P0,
 660			   AUDIO_2CH_SEL_DP_ENC0_P0_MASK |
 661			   AUDIO_2CH_EN_DP_ENC0_P0_MASK |
 662			   AUDIO_8CH_SEL_DP_ENC0_P0_MASK |
 663			   AUDIO_8CH_EN_DP_ENC0_P0_MASK |
 664			   AU_EN_DP_ENC0_P0);
 665
 666	/* audio channel count change reset */
 667	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, 0, DP_ENC_DUMMY_RW_1);
 668
 669	/* enable audio reset */
 670	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4,
 671			   DP_ENC_DUMMY_RW_1_AUDIO_RST_EN,
 672			   DP_ENC_DUMMY_RW_1_AUDIO_RST_EN);
 673}
 674
 675static void mtk_dp_audio_channel_status_set(struct mtk_dp *mtk_dp,
 676					    struct mtk_dp_audio_cfg *cfg)
 677{
 678	struct snd_aes_iec958 iec = { 0 };
 679
 680	switch (cfg->sample_rate) {
 681	case 32000:
 682		iec.status[3] = IEC958_AES3_CON_FS_32000;
 683		break;
 684	case 44100:
 685		iec.status[3] = IEC958_AES3_CON_FS_44100;
 686		break;
 687	case 48000:
 688		iec.status[3] = IEC958_AES3_CON_FS_48000;
 689		break;
 690	case 88200:
 691		iec.status[3] = IEC958_AES3_CON_FS_88200;
 692		break;
 693	case 96000:
 694		iec.status[3] = IEC958_AES3_CON_FS_96000;
 695		break;
 696	case 192000:
 697		iec.status[3] = IEC958_AES3_CON_FS_192000;
 698		break;
 699	default:
 700		iec.status[3] = IEC958_AES3_CON_FS_NOTID;
 701		break;
 702	}
 703
 704	switch (cfg->word_length_bits) {
 705	case 16:
 706		iec.status[4] = IEC958_AES4_CON_WORDLEN_20_16;
 707		break;
 708	case 20:
 709		iec.status[4] = IEC958_AES4_CON_WORDLEN_20_16 |
 710				IEC958_AES4_CON_MAX_WORDLEN_24;
 711		break;
 712	case 24:
 713		iec.status[4] = IEC958_AES4_CON_WORDLEN_24_20 |
 714				IEC958_AES4_CON_MAX_WORDLEN_24;
 715		break;
 716	default:
 717		iec.status[4] = IEC958_AES4_CON_WORDLEN_NOTID;
 718	}
 719
 720	/* IEC 60958 consumer channel status bits */
 721	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_308C,
 722			   0, CH_STATUS_0_DP_ENC0_P0_MASK);
 723	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3090,
 724			   iec.status[3] << 8, CH_STATUS_1_DP_ENC0_P0_MASK);
 725	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3094,
 726			   iec.status[4], CH_STATUS_2_DP_ENC0_P0_MASK);
 727}
 728
 729static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,
 730					      int channels)
 731{
 732	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_312C,
 733			   (min(8, channels) - 1) << 8,
 734			   ASP_HB2_DP_ENC0_P0_MASK | ASP_HB3_DP_ENC0_P0_MASK);
 735}
 736
 737static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)
 738{
 739	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,
 740			   mtk_dp->data->audio_m_div2_bit,
 741			   AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
 742}
 743
 744static void mtk_dp_sdp_trigger_aui(struct mtk_dp *mtk_dp)
 745{
 746	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280,
 747			   MTK_DP_SDP_AUI, SDP_PACKET_TYPE_DP_ENC1_P0_MASK);
 748	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280,
 749			   SDP_PACKET_W_DP_ENC1_P0, SDP_PACKET_W_DP_ENC1_P0);
 750}
 751
 752static void mtk_dp_sdp_set_data(struct mtk_dp *mtk_dp, u8 *data_bytes)
 753{
 754	mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_ENC1_P0_3200,
 755				data_bytes, 0x10);
 756}
 757
 758static void mtk_dp_sdp_set_header_aui(struct mtk_dp *mtk_dp,
 759				      struct dp_sdp_header *header)
 760{
 761	u32 db_addr = MTK_DP_ENC0_P0_30D8 + (MTK_DP_SDP_AUI - 1) * 8;
 762
 763	mtk_dp_bulk_16bit_write(mtk_dp, db_addr, (u8 *)header, 4);
 764}
 765
 766static void mtk_dp_disable_sdp_aui(struct mtk_dp *mtk_dp)
 767{
 768	/* Disable periodic send */
 769	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A8 & 0xfffc, 0,
 770			   0xff << ((MTK_DP_ENC0_P0_30A8 & 3) * 8));
 771}
 772
 773static void mtk_dp_setup_sdp_aui(struct mtk_dp *mtk_dp,
 774				 struct dp_sdp *sdp)
 775{
 776	u32 shift;
 777
 778	mtk_dp_sdp_set_data(mtk_dp, sdp->db);
 779	mtk_dp_sdp_set_header_aui(mtk_dp, &sdp->sdp_header);
 780	mtk_dp_disable_sdp_aui(mtk_dp);
 781
 782	shift = (MTK_DP_ENC0_P0_30A8 & 3) * 8;
 783
 784	mtk_dp_sdp_trigger_aui(mtk_dp);
 785	/* Enable periodic sending */
 786	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A8 & 0xfffc,
 787			   0x05 << shift, 0xff << shift);
 788}
 789
 790static void mtk_dp_aux_irq_clear(struct mtk_dp *mtk_dp)
 791{
 792	mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3640, DP_AUX_P0_3640_VAL);
 793}
 794
 795static void mtk_dp_aux_set_cmd(struct mtk_dp *mtk_dp, u8 cmd, u32 addr)
 796{
 797	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3644,
 798			   cmd, MCU_REQUEST_COMMAND_AUX_TX_P0_MASK);
 799	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3648,
 800			   addr, MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK);
 801	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_364C,
 802			   addr >> 16, MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK);
 803}
 804
 805static void mtk_dp_aux_clear_fifo(struct mtk_dp *mtk_dp)
 806{
 807	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3650,
 808			   MCU_ACK_TRAN_COMPLETE_AUX_TX_P0,
 809			   MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 |
 810			   PHY_FIFO_RST_AUX_TX_P0_MASK |
 811			   MCU_REQ_DATA_NUM_AUX_TX_P0_MASK);
 812}
 813
 814static void mtk_dp_aux_request_ready(struct mtk_dp *mtk_dp)
 815{
 816	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3630,
 817			   AUX_TX_REQUEST_READY_AUX_TX_P0,
 818			   AUX_TX_REQUEST_READY_AUX_TX_P0);
 819}
 820
 821static void mtk_dp_aux_fill_write_fifo(struct mtk_dp *mtk_dp, u8 *buf,
 822				       size_t length)
 823{
 824	mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_AUX_P0_3708, buf, length);
 825}
 826
 827static void mtk_dp_aux_read_rx_fifo(struct mtk_dp *mtk_dp, u8 *buf,
 828				    size_t length, int read_delay)
 829{
 830	int read_pos;
 831
 832	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3620,
 833			   0, AUX_RD_MODE_AUX_TX_P0_MASK);
 834
 835	for (read_pos = 0; read_pos < length; read_pos++) {
 836		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3620,
 837				   AUX_RX_FIFO_READ_PULSE_TX_P0,
 838				   AUX_RX_FIFO_READ_PULSE_TX_P0);
 839
 840		/* Hardware needs time to update the data */
 841		usleep_range(read_delay, read_delay * 2);
 842		buf[read_pos] = (u8)(mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3620) &
 843				     AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK);
 844	}
 845}
 846
 847static void mtk_dp_aux_set_length(struct mtk_dp *mtk_dp, size_t length)
 848{
 849	if (length > 0) {
 850		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3650,
 851				   (length - 1) << 12,
 852				   MCU_REQ_DATA_NUM_AUX_TX_P0_MASK);
 853		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,
 854				   0,
 855				   AUX_NO_LENGTH_AUX_TX_P0 |
 856				   AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |
 857				   AUX_RESERVED_RW_0_AUX_TX_P0_MASK);
 858	} else {
 859		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,
 860				   AUX_NO_LENGTH_AUX_TX_P0,
 861				   AUX_NO_LENGTH_AUX_TX_P0 |
 862				   AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |
 863				   AUX_RESERVED_RW_0_AUX_TX_P0_MASK);
 864	}
 865}
 866
 867static int mtk_dp_aux_wait_for_completion(struct mtk_dp *mtk_dp, bool is_read)
 868{
 869	int wait_reply = MTK_DP_AUX_WAIT_REPLY_COUNT;
 870
 871	while (--wait_reply) {
 872		u32 aux_irq_status;
 873
 874		if (is_read) {
 875			u32 fifo_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3618);
 876
 877			if (fifo_status &
 878			    (AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK |
 879			     AUX_RX_FIFO_FULL_AUX_TX_P0_MASK)) {
 880				return 0;
 881			}
 882		}
 883
 884		aux_irq_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3640);
 885		if (aux_irq_status & AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0)
 886			return 0;
 887
 888		if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0)
 889			return -ETIMEDOUT;
 890
 891		/* Give the hardware a chance to reach completion before retrying */
 892		usleep_range(100, 500);
 893	}
 894
 895	return -ETIMEDOUT;
 896}
 897
 898static int mtk_dp_aux_do_transfer(struct mtk_dp *mtk_dp, bool is_read, u8 cmd,
 899				  u32 addr, u8 *buf, size_t length, u8 *reply_cmd)
 900{
 901	int ret;
 902
 903	if (is_read && (length > DP_AUX_MAX_PAYLOAD_BYTES ||
 904			(cmd == DP_AUX_NATIVE_READ && !length)))
 905		return -EINVAL;
 906
 907	if (!is_read)
 908		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3704,
 909				   AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0,
 910				   AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0);
 911
 912	/* We need to clear fifo and irq before sending commands to the sink device. */
 913	mtk_dp_aux_clear_fifo(mtk_dp);
 914	mtk_dp_aux_irq_clear(mtk_dp);
 915
 916	mtk_dp_aux_set_cmd(mtk_dp, cmd, addr);
 917	mtk_dp_aux_set_length(mtk_dp, length);
 918
 919	if (!is_read) {
 920		if (length)
 921			mtk_dp_aux_fill_write_fifo(mtk_dp, buf, length);
 922
 923		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3704,
 924				   AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK,
 925				   AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK);
 926	}
 927
 928	mtk_dp_aux_request_ready(mtk_dp);
 929
 930	/* Wait for feedback from sink device. */
 931	ret = mtk_dp_aux_wait_for_completion(mtk_dp, is_read);
 932
 933	*reply_cmd = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3624) &
 934		     AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK;
 935
 936	if (ret) {
 937		u32 phy_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_3628) &
 938				 AUX_RX_PHY_STATE_AUX_TX_P0_MASK;
 939		if (phy_status != AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE) {
 940			dev_err(mtk_dp->dev,
 941				"AUX Rx Aux hang, need SW reset\n");
 942			return -EIO;
 943		}
 944
 945		return -ETIMEDOUT;
 946	}
 947
 948	if (!length) {
 949		mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_362C,
 950				   0,
 951				   AUX_NO_LENGTH_AUX_TX_P0 |
 952				   AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK |
 953				   AUX_RESERVED_RW_0_AUX_TX_P0_MASK);
 954	} else if (is_read) {
 955		int read_delay;
 956
 957		if (cmd == (DP_AUX_I2C_READ | DP_AUX_I2C_MOT) ||
 958		    cmd == DP_AUX_I2C_READ)
 959			read_delay = 500;
 960		else
 961			read_delay = 100;
 962
 963		mtk_dp_aux_read_rx_fifo(mtk_dp, buf, length, read_delay);
 964	}
 965
 966	return 0;
 967}
 968
 969static void mtk_dp_set_swing_pre_emphasis(struct mtk_dp *mtk_dp, int lane_num,
 970					  int swing_val, int preemphasis)
 971{
 972	u32 lane_shift = lane_num * DP_TX1_VOLT_SWING_SHIFT;
 973
 974	dev_dbg(mtk_dp->dev,
 975		"link training: swing_val = 0x%x, pre-emphasis = 0x%x\n",
 976		swing_val, preemphasis);
 977
 978	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
 979			   swing_val << (DP_TX0_VOLT_SWING_SHIFT + lane_shift),
 980			   DP_TX0_VOLT_SWING_MASK << lane_shift);
 981	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
 982			   preemphasis << (DP_TX0_PRE_EMPH_SHIFT + lane_shift),
 983			   DP_TX0_PRE_EMPH_MASK << lane_shift);
 984}
 985
 986static void mtk_dp_reset_swing_pre_emphasis(struct mtk_dp *mtk_dp)
 987{
 988	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_SWING_EMP,
 989			   0,
 990			   DP_TX0_VOLT_SWING_MASK |
 991			   DP_TX1_VOLT_SWING_MASK |
 992			   DP_TX2_VOLT_SWING_MASK |
 993			   DP_TX3_VOLT_SWING_MASK |
 994			   DP_TX0_PRE_EMPH_MASK |
 995			   DP_TX1_PRE_EMPH_MASK |
 996			   DP_TX2_PRE_EMPH_MASK |
 997			   DP_TX3_PRE_EMPH_MASK);
 998}
 999
1000static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk_dp)
1001{
1002	u32 irq_status = mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_35D0) &
1003			 SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK;
1004
1005	if (irq_status) {
1006		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8,
1007				   irq_status, SW_IRQ_CLR_DP_TRANS_P0_MASK);
1008		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35C8,
1009				   0, SW_IRQ_CLR_DP_TRANS_P0_MASK);
1010	}
1011
1012	return irq_status;
1013}
1014
1015static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
1016{
1017	u32 irq_status = (mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3418) &
1018			  IRQ_STATUS_DP_TRANS_P0_MASK) >> 12;
1019
1020	if (irq_status) {
1021		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,
1022				   irq_status, IRQ_CLR_DP_TRANS_P0_MASK);
1023		mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,
1024				   0, IRQ_CLR_DP_TRANS_P0_MASK);
1025	}
1026
1027	return irq_status;
1028}
1029
1030static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
1031{
1032	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,
1033			   enable ? 0 :
1034			   IRQ_MASK_DP_TRANS_P0_DISC_IRQ |
1035			   IRQ_MASK_DP_TRANS_P0_CONN_IRQ |
1036			   IRQ_MASK_DP_TRANS_P0_INT_IRQ,
1037			   IRQ_MASK_DP_TRANS_P0_MASK);
1038}
1039
1040static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
1041{
1042	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_342C,
1043			   XTAL_FREQ_DP_TRANS_P0_DEFAULT,
1044			   XTAL_FREQ_DP_TRANS_P0_MASK);
1045	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3540,
1046			   FEC_CLOCK_EN_MODE_DP_TRANS_P0,
1047			   FEC_CLOCK_EN_MODE_DP_TRANS_P0);
1048	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31EC,
1049			   AUDIO_CH_SRC_SEL_DP_ENC0_P0,
1050			   AUDIO_CH_SRC_SEL_DP_ENC0_P0);
1051	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C,
1052			   0, SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK);
1053	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK,
1054			   IRQ_MASK_AUX_TOP_IRQ, IRQ_MASK_AUX_TOP_IRQ);
1055}
1056
1057static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp)
1058{
1059	u32 val;
1060	/* Debounce threshold */
1061	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
1062			   8, HPD_DEB_THD_DP_TRANS_P0_MASK);
1063
1064	val = (HPD_INT_THD_DP_TRANS_P0_LOWER_500US |
1065	       HPD_INT_THD_DP_TRANS_P0_UPPER_1100US) << 4;
1066	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
1067			   val, HPD_INT_THD_DP_TRANS_P0_MASK);
1068
1069	/*
1070	 * Connect threshold 1.5ms + 5 x 0.1ms = 2ms
1071	 * Disconnect threshold 1.5ms + 5 x 0.1ms = 2ms
1072	 */
1073	val = (5 << 8) | (5 << 12);
1074	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
1075			   val,
1076			   HPD_DISC_THD_DP_TRANS_P0_MASK |
1077			   HPD_CONN_THD_DP_TRANS_P0_MASK);
1078	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3430,
1079			   HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT,
1080			   HPD_INT_THD_ECO_DP_TRANS_P0_MASK);
1081}
1082
1083static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)
1084{
1085	/* modify timeout threshold = 0x1595 */
1086	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_360C,
1087			   AUX_TIMEOUT_THR_AUX_TX_P0_VAL,
1088			   AUX_TIMEOUT_THR_AUX_TX_P0_MASK);
1089	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3658,
1090			   0, AUX_TX_OV_EN_AUX_TX_P0_MASK);
1091	/* 25 for 26M */
1092	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3634,
1093			   AUX_TX_OVER_SAMPLE_RATE_FOR_26M << 8,
1094			   AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK);
1095	/* 13 for 26M */
1096	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3614,
1097			   AUX_RX_UI_CNT_THR_AUX_FOR_26M,
1098			   AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK);
1099	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_37C8,
1100			   MTK_ATOP_EN_AUX_TX_P0,
1101			   MTK_ATOP_EN_AUX_TX_P0);
1102
1103	/* Set complete reply mode for AUX */
1104	mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_3690,
1105			   RX_REPLY_COMPLETE_MODE_AUX_TX_P0,
1106			   RX_REPLY_COMPLETE_MODE_AUX_TX_P0);
1107}
1108
1109static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)
1110{
1111	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C,
1112			   0, VBID_VIDEO_MUTE_DP_ENC0_P0_MASK);
1113
1114	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368,
1115			   BS2BS_MODE_DP_ENC1_P0_VAL << 12,
1116			   BS2BS_MODE_DP_ENC1_P0_MASK);
1117
1118	/* dp tx encoder reset all sw */
1119	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
1120			   DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0,
1121			   DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
1122
1123	/* Wait for sw reset to complete */
1124	usleep_range(1000, 5000);
1125	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
1126			   0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
1127}
1128
1129static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp)
1130{
1131	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C,
1132			   DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0,
1133			   DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);
1134
1135	/* Wait for sw reset to complete */
1136	usleep_range(1000, 5000);
1137	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C,
1138			   0, DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);
1139}
1140
1141static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp)
1142{
1143	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
1144			   SDP_RESET_SW_DP_ENC0_P0,
1145			   SDP_RESET_SW_DP_ENC0_P0);
1146
1147	/* Wait for sdp path reset to complete */
1148	usleep_range(1000, 5000);
1149	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
1150			   0, SDP_RESET_SW_DP_ENC0_P0);
1151}
1152
1153static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)
1154{
1155	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,
1156			   lanes == 0 ? 0 : DP_TRANS_DUMMY_RW_0,
1157			   DP_TRANS_DUMMY_RW_0_MASK);
1158	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
1159			   lanes, LANE_NUM_DP_ENC0_P0_MASK);
1160	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_34A4,
1161			   lanes << 2, LANE_NUM_DP_TRANS_P0_MASK);
1162}
1163
1164static void mtk_dp_get_calibration_data(struct mtk_dp *mtk_dp)
1165{
1166	const struct mtk_dp_efuse_fmt *fmt;
1167	struct device *dev = mtk_dp->dev;
1168	struct nvmem_cell *cell;
1169	u32 *cal_data = mtk_dp->cal_data;
1170	u32 *buf;
1171	int i;
1172	size_t len;
1173
1174	cell = nvmem_cell_get(dev, "dp_calibration_data");
1175	if (IS_ERR(cell)) {
1176		dev_warn(dev, "Failed to get nvmem cell dp_calibration_data\n");
1177		goto use_default_val;
1178	}
1179
1180	buf = (u32 *)nvmem_cell_read(cell, &len);
1181	nvmem_cell_put(cell);
1182
1183	if (IS_ERR(buf)) {
1184		dev_warn(dev, "Failed to read nvmem_cell_read\n");
1185		goto use_default_val;
1186	}
1187
1188	/* The cell length is in bytes. Convert it to be compatible with u32 buffer. */
1189	len /= sizeof(u32);
1190
1191	for (i = 0; i < MTK_DP_CAL_MAX; i++) {
1192		fmt = &mtk_dp->data->efuse_fmt[i];
1193
1194		if (fmt->idx >= len) {
1195			dev_warn(mtk_dp->dev,
1196				 "Out-of-bound efuse data access, fmt idx = %d, buf len = %zu\n",
1197				 fmt->idx, len);
1198			kfree(buf);
1199			goto use_default_val;
1200		}
1201
1202		cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt->mask;
1203
1204		if (cal_data[i] < fmt->min_val || cal_data[i] > fmt->max_val) {
1205			dev_warn(mtk_dp->dev, "Invalid efuse data, idx = %d\n", i);
1206			kfree(buf);
1207			goto use_default_val;
1208		}
1209	}
1210	kfree(buf);
1211
1212	return;
1213
1214use_default_val:
1215	dev_warn(mtk_dp->dev, "Use default calibration data\n");
1216	for (i = 0; i < MTK_DP_CAL_MAX; i++)
1217		cal_data[i] = mtk_dp->data->efuse_fmt[i].default_val;
1218}
1219
1220static void mtk_dp_set_calibration_data(struct mtk_dp *mtk_dp)
1221{
1222	u32 *cal_data = mtk_dp->cal_data;
1223
1224	mtk_dp_update_bits(mtk_dp, DP_PHY_GLB_DPAUX_TX,
1225			   cal_data[MTK_DP_CAL_CLKTX_IMPSE] << 20,
1226			   RG_CKM_PT0_CKTX_IMPSEL);
1227	mtk_dp_update_bits(mtk_dp, DP_PHY_GLB_BIAS_GEN_00,
1228			   cal_data[MTK_DP_CAL_GLB_BIAS_TRIM] << 16,
1229			   RG_XTP_GLB_BIAS_INTR_CTRL);
1230	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_0,
1231			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] << 12,
1232			   RG_XTP_LN0_TX_IMPSEL_PMOS);
1233	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_0,
1234			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] << 16,
1235			   RG_XTP_LN0_TX_IMPSEL_NMOS);
1236	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_1,
1237			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] << 12,
1238			   RG_XTP_LN1_TX_IMPSEL_PMOS);
1239	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_1,
1240			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] << 16,
1241			   RG_XTP_LN1_TX_IMPSEL_NMOS);
1242	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_2,
1243			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] << 12,
1244			   RG_XTP_LN2_TX_IMPSEL_PMOS);
1245	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_2,
1246			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] << 16,
1247			   RG_XTP_LN2_TX_IMPSEL_NMOS);
1248	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_3,
1249			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] << 12,
1250			   RG_XTP_LN3_TX_IMPSEL_PMOS);
1251	mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_3,
1252			   cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] << 16,
1253			   RG_XTP_LN3_TX_IMPSEL_NMOS);
1254}
1255
1256static int mtk_dp_phy_configure(struct mtk_dp *mtk_dp,
1257				u32 link_rate, int lane_count)
1258{
1259	int ret;
1260	union phy_configure_opts phy_opts = {
1261		.dp = {
1262			.link_rate = drm_dp_bw_code_to_link_rate(link_rate) / 100,
1263			.set_rate = 1,
1264			.lanes = lane_count,
1265			.set_lanes = 1,
1266			.ssc = mtk_dp->train_info.sink_ssc,
1267		}
1268	};
1269
1270	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
1271			   DP_PWR_STATE_MASK);
1272
1273	ret = phy_configure(mtk_dp->phy, &phy_opts);
1274	if (ret)
1275		return ret;
1276
1277	mtk_dp_set_calibration_data(mtk_dp);
1278	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
1279			   DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
1280
1281	return 0;
1282}
1283
1284static void mtk_dp_set_idle_pattern(struct mtk_dp *mtk_dp, bool enable)
1285{
1286	u32 val = POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK |
1287		  POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK |
1288		  POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK |
1289		  POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK;
1290
1291	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3580,
1292			   enable ? val : 0, val);
1293}
1294
1295static void mtk_dp_train_set_pattern(struct mtk_dp *mtk_dp, int pattern)
1296{
1297	/* TPS1 */
1298	if (pattern == 1)
1299		mtk_dp_set_idle_pattern(mtk_dp, false);
1300
1301	mtk_dp_update_bits(mtk_dp,
1302			   MTK_DP_TRANS_P0_3400,
1303			   pattern ? BIT(pattern - 1) << 12 : 0,
1304			   PATTERN1_EN_DP_TRANS_P0_MASK |
1305			   PATTERN2_EN_DP_TRANS_P0_MASK |
1306			   PATTERN3_EN_DP_TRANS_P0_MASK |
1307			   PATTERN4_EN_DP_TRANS_P0_MASK);
1308}
1309
1310static void mtk_dp_set_enhanced_frame_mode(struct mtk_dp *mtk_dp)
1311{
1312	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
1313			   ENHANCED_FRAME_EN_DP_ENC0_P0,
1314			   ENHANCED_FRAME_EN_DP_ENC0_P0);
1315}
1316
1317static void mtk_dp_training_set_scramble(struct mtk_dp *mtk_dp, bool enable)
1318{
1319	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3404,
1320			   enable ? DP_SCR_EN_DP_TRANS_P0_MASK : 0,
1321			   DP_SCR_EN_DP_TRANS_P0_MASK);
1322}
1323
1324static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable)
1325{
1326	struct arm_smccc_res res;
1327	u32 val = VIDEO_MUTE_SEL_DP_ENC0_P0 |
1328		  (enable ? VIDEO_MUTE_SW_DP_ENC0_P0 : 0);
1329
1330	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
1331			   val,
1332			   VIDEO_MUTE_SEL_DP_ENC0_P0 |
1333			   VIDEO_MUTE_SW_DP_ENC0_P0);
1334
1335	arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32,
1336		      mtk_dp->data->smc_cmd, enable,
1337		      0, 0, 0, 0, 0, &res);
1338
1339	dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n",
1340		mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1);
1341}
1342
1343static void mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute)
1344{
1345	u32 val[3];
1346
1347	if (mute) {
1348		val[0] = VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 |
1349			 VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0;
1350		val[1] = 0;
1351		val[2] = 0;
1352	} else {
1353		val[0] = 0;
1354		val[1] = AU_EN_DP_ENC0_P0;
1355		/* Send one every two frames */
1356		val[2] = 0x0F;
1357	}
1358
1359	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3030,
1360			   val[0],
1361			   VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 |
1362			   VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0);
1363	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088,
1364			   val[1], AU_EN_DP_ENC0_P0);
1365	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A4,
1366			   val[2], AU_TS_CFG_DP_ENC0_P0_MASK);
1367}
1368
1369static void mtk_dp_aux_panel_poweron(struct mtk_dp *mtk_dp, bool pwron)
1370{
1371	if (pwron) {
1372		/* power on aux */
1373		mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
1374				   DP_PWR_STATE_BANDGAP_TPLL_LANE,
1375				   DP_PWR_STATE_MASK);
1376
1377		/* power on panel */
1378		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1379		usleep_range(2000, 5000);
1380	} else {
1381		/* power off panel */
1382		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1383		usleep_range(2000, 3000);
1384
1385		/* power off aux */
1386		mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
1387				   DP_PWR_STATE_BANDGAP_TPLL,
1388				   DP_PWR_STATE_MASK);
1389	}
1390}
1391
1392static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)
1393{
1394	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,
1395			   0, SW_RST_B_PHYD);
1396
1397	/* Wait for power enable */
1398	usleep_range(10, 200);
1399
1400	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,
1401			   SW_RST_B_PHYD, SW_RST_B_PHYD);
1402	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
1403			   DP_PWR_STATE_BANDGAP_TPLL, DP_PWR_STATE_MASK);
1404	mtk_dp_write(mtk_dp, MTK_DP_1040,
1405		     RG_DPAUX_RX_VALID_DEGLITCH_EN | RG_XTP_GLB_CKDET_EN |
1406		     RG_DPAUX_RX_EN);
1407	mtk_dp_update_bits(mtk_dp, MTK_DP_0034, 0, DA_CKM_CKTX0_EN_FORCE_EN);
1408}
1409
1410static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
1411{
1412	mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);
1413
1414	mtk_dp_update_bits(mtk_dp, MTK_DP_0034,
1415			   DA_CKM_CKTX0_EN_FORCE_EN, DA_CKM_CKTX0_EN_FORCE_EN);
1416
1417	/* Disable RX */
1418	mtk_dp_write(mtk_dp, MTK_DP_1040, 0);
1419	mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD,
1420		     0x550 | FUSE_SEL | MEM_ISO_EN);
1421}
1422
1423static void mtk_dp_initialize_priv_data(struct mtk_dp *mtk_dp)
1424{
1425	bool plugged_in = (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP);
1426
1427	mtk_dp->train_info.link_rate = DP_LINK_BW_5_4;
1428	mtk_dp->train_info.lane_count = mtk_dp->max_lanes;
1429	mtk_dp->train_info.cable_plugged_in = plugged_in;
1430
1431	mtk_dp->info.format = DP_PIXELFORMAT_RGB;
1432	memset(&mtk_dp->info.vm, 0, sizeof(struct videomode));
1433	mtk_dp->audio_enable = false;
1434}
1435
1436static void mtk_dp_sdp_set_down_cnt_init(struct mtk_dp *mtk_dp,
1437					 u32 sram_read_start)
1438{
1439	u32 sdp_down_cnt_init = 0;
1440	struct drm_display_mode mode;
1441	struct videomode *vm = &mtk_dp->info.vm;
1442
1443	drm_display_mode_from_videomode(vm, &mode);
1444
1445	if (mode.clock > 0)
1446		sdp_down_cnt_init = sram_read_start *
1447				    mtk_dp->train_info.link_rate * 2700 * 8 /
1448				    (mode.clock * 4);
1449
1450	switch (mtk_dp->train_info.lane_count) {
1451	case 1:
1452		sdp_down_cnt_init = max_t(u32, sdp_down_cnt_init, 0x1A);
1453		break;
1454	case 2:
1455		/* case for LowResolution && High Audio Sample Rate */
1456		sdp_down_cnt_init = max_t(u32, sdp_down_cnt_init, 0x10);
1457		sdp_down_cnt_init += mode.vtotal <= 525 ? 4 : 0;
1458		break;
1459	case 4:
1460	default:
1461		sdp_down_cnt_init = max_t(u32, sdp_down_cnt_init, 6);
1462		break;
1463	}
1464
1465	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040,
1466			   sdp_down_cnt_init,
1467			   SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK);
1468}
1469
1470static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
1471{
1472	int pix_clk_mhz;
1473	u32 dc_offset;
1474	u32 spd_down_cnt_init = 0;
1475	struct drm_display_mode mode;
1476	struct videomode *vm = &mtk_dp->info.vm;
1477
1478	drm_display_mode_from_videomode(vm, &mode);
1479
1480	pix_clk_mhz = mtk_dp->info.format == DP_PIXELFORMAT_YUV420 ?
1481		      mode.clock / 2000 : mode.clock / 1000;
1482
1483	switch (mtk_dp->train_info.lane_count) {
1484	case 1:
1485		spd_down_cnt_init = 0x20;
1486		break;
1487	case 2:
1488		dc_offset = (mode.vtotal <= 525) ? 0x14 : 0x00;
1489		spd_down_cnt_init = 0x18 + dc_offset;
1490		break;
1491	case 4:
1492	default:
1493		dc_offset = (mode.vtotal <= 525) ? 0x08 : 0x00;
1494		if (pix_clk_mhz > mtk_dp->train_info.link_rate * 27)
1495			spd_down_cnt_init = 0x8;
1496		else
1497			spd_down_cnt_init = 0x10 + dc_offset;
1498		break;
1499	}
1500
1501	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364, spd_down_cnt_init,
1502			   SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);
1503}
1504
1505static void mtk_dp_audio_sample_arrange_disable(struct mtk_dp *mtk_dp)
1506{
1507	/* arrange audio packets into the Hblanking and Vblanking area */
1508	if (!mtk_dp->data->audio_pkt_in_hblank_area)
1509		return;
1510
1511	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,
1512			   SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK);
1513	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,
1514			   SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK);
1515}
1516
1517static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
1518{
1519	u32 sram_read_start = min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR,
1520				    mtk_dp->info.vm.hactive /
1521				    mtk_dp->train_info.lane_count /
1522				    MTK_DP_4P1T / MTK_DP_HDE /
1523				    MTK_DP_PIX_PER_ADDR);
1524	mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
1525	mtk_dp_setup_encoder(mtk_dp);
1526	mtk_dp_audio_sample_arrange_disable(mtk_dp);
1527	mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);
1528	mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);
1529}
1530
1531static void mtk_dp_set_tx_out(struct mtk_dp *mtk_dp)
1532{
1533	mtk_dp_setup_tu(mtk_dp);
1534}
1535
1536static void mtk_dp_train_update_swing_pre(struct mtk_dp *mtk_dp, int lanes,
1537					  u8 dpcd_adjust_req[2])
1538{
1539	int lane;
1540
1541	for (lane = 0; lane < lanes; ++lane) {
1542		u8 val;
1543		u8 swing;
1544		u8 preemphasis;
1545		int index = lane / 2;
1546		int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0;
1547
1548		swing = (dpcd_adjust_req[index] >> shift) &
1549			DP_ADJUST_VOLTAGE_SWING_LANE0_MASK;
1550		preemphasis = ((dpcd_adjust_req[index] >> shift) &
1551			       DP_ADJUST_PRE_EMPHASIS_LANE0_MASK) >>
1552			      DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT;
1553		val = swing << DP_TRAIN_VOLTAGE_SWING_SHIFT |
1554		      preemphasis << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1555
1556		if (swing == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
1557			val |= DP_TRAIN_MAX_SWING_REACHED;
1558		if (preemphasis == 3)
1559			val |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1560
1561		mtk_dp_set_swing_pre_emphasis(mtk_dp, lane, swing, preemphasis);
1562		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_LANE0_SET + lane,
1563				   val);
1564	}
1565}
1566
1567static void mtk_dp_pattern(struct mtk_dp *mtk_dp, bool is_tps1)
1568{
1569	int pattern;
1570	unsigned int aux_offset;
1571
1572	if (is_tps1) {
1573		pattern = 1;
1574		aux_offset = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1;
1575	} else {
1576		aux_offset = mtk_dp->train_info.channel_eq_pattern;
1577
1578		switch (mtk_dp->train_info.channel_eq_pattern) {
1579		case DP_TRAINING_PATTERN_4:
1580			pattern = 4;
1581			break;
1582		case DP_TRAINING_PATTERN_3:
1583			pattern = 3;
1584			aux_offset |= DP_LINK_SCRAMBLING_DISABLE;
1585			break;
1586		case DP_TRAINING_PATTERN_2:
1587		default:
1588			pattern = 2;
1589			aux_offset |= DP_LINK_SCRAMBLING_DISABLE;
1590			break;
1591		}
1592	}
1593
1594	mtk_dp_train_set_pattern(mtk_dp, pattern);
1595	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, aux_offset);
1596}
1597
1598static int mtk_dp_train_setting(struct mtk_dp *mtk_dp, u8 target_link_rate,
1599				u8 target_lane_count)
1600{
1601	int ret;
1602
1603	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, target_link_rate);
1604	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,
1605			   target_lane_count | DP_LANE_COUNT_ENHANCED_FRAME_EN);
1606
1607	if (mtk_dp->train_info.sink_ssc)
1608		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL,
1609				   DP_SPREAD_AMP_0_5);
1610
1611	mtk_dp_set_lanes(mtk_dp, target_lane_count / 2);
1612	ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, target_lane_count);
1613	if (ret)
1614		return ret;
1615
1616	dev_dbg(mtk_dp->dev,
1617		"Link train target_link_rate = 0x%x, target_lane_count = 0x%x\n",
1618		target_link_rate, target_lane_count);
1619
1620	return 0;
1621}
1622
1623static int mtk_dp_train_cr(struct mtk_dp *mtk_dp, u8 target_lane_count)
1624{
1625	u8 lane_adjust[2] = {};
1626	u8 link_status[DP_LINK_STATUS_SIZE] = {};
1627	u8 prev_lane_adjust = 0xff;
1628	int train_retries = 0;
1629	int voltage_retries = 0;
1630
1631	mtk_dp_pattern(mtk_dp, true);
1632
1633	/* In DP spec 1.4, the retry count of CR is defined as 10. */
1634	do {
1635		train_retries++;
1636		if (!mtk_dp->train_info.cable_plugged_in) {
1637			mtk_dp_train_set_pattern(mtk_dp, 0);
1638			return -ENODEV;
1639		}
1640
1641		drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,
1642				 lane_adjust, sizeof(lane_adjust));
1643		mtk_dp_train_update_swing_pre(mtk_dp, target_lane_count,
1644					      lane_adjust);
1645
1646		drm_dp_link_train_clock_recovery_delay(&mtk_dp->aux,
1647						       mtk_dp->rx_cap);
1648
1649		/* check link status from sink device */
1650		drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
1651		if (drm_dp_clock_recovery_ok(link_status,
1652					     target_lane_count)) {
1653			dev_dbg(mtk_dp->dev, "Link train CR pass\n");
1654			return 0;
1655		}
1656
1657		/*
1658		 * In DP spec 1.4, if current voltage level is the same
1659		 * with previous voltage level, we need to retry 5 times.
1660		 */
1661		if (prev_lane_adjust == link_status[4]) {
1662			voltage_retries++;
1663			/*
1664			 * Condition of CR fail:
1665			 * 1. Failed to pass CR using the same voltage
1666			 *    level over five times.
1667			 * 2. Failed to pass CR when the current voltage
1668			 *    level is the same with previous voltage
1669			 *    level and reach max voltage level (3).
1670			 */
1671			if (voltage_retries > MTK_DP_TRAIN_VOLTAGE_LEVEL_RETRY ||
1672			    (prev_lane_adjust & DP_ADJUST_VOLTAGE_SWING_LANE0_MASK) == 3) {
1673				dev_dbg(mtk_dp->dev, "Link train CR fail\n");
1674				break;
1675			}
1676		} else {
1677			/*
1678			 * If the voltage level is changed, we need to
1679			 * re-calculate this retry count.
1680			 */
1681			voltage_retries = 0;
1682		}
1683		prev_lane_adjust = link_status[4];
1684	} while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);
1685
1686	/* Failed to train CR, and disable pattern. */
1687	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
1688			   DP_TRAINING_PATTERN_DISABLE);
1689	mtk_dp_train_set_pattern(mtk_dp, 0);
1690
1691	return -ETIMEDOUT;
1692}
1693
1694static int mtk_dp_train_eq(struct mtk_dp *mtk_dp, u8 target_lane_count)
1695{
1696	u8 lane_adjust[2] = {};
1697	u8 link_status[DP_LINK_STATUS_SIZE] = {};
1698	int train_retries = 0;
1699
1700	mtk_dp_pattern(mtk_dp, false);
1701
1702	do {
1703		train_retries++;
1704		if (!mtk_dp->train_info.cable_plugged_in) {
1705			mtk_dp_train_set_pattern(mtk_dp, 0);
1706			return -ENODEV;
1707		}
1708
1709		drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,
1710				 lane_adjust, sizeof(lane_adjust));
1711		mtk_dp_train_update_swing_pre(mtk_dp, target_lane_count,
1712					      lane_adjust);
1713
1714		drm_dp_link_train_channel_eq_delay(&mtk_dp->aux,
1715						   mtk_dp->rx_cap);
1716
1717		/* check link status from sink device */
1718		drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
1719		if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {
1720			dev_dbg(mtk_dp->dev, "Link train EQ pass\n");
1721
1722			/* Training done, and disable pattern. */
1723			drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
1724					   DP_TRAINING_PATTERN_DISABLE);
1725			mtk_dp_train_set_pattern(mtk_dp, 0);
1726			return 0;
1727		}
1728		dev_dbg(mtk_dp->dev, "Link train EQ fail\n");
1729	} while (train_retries < MTK_DP_TRAIN_DOWNSCALE_RETRY);
1730
1731	/* Failed to train EQ, and disable pattern. */
1732	drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,
1733			   DP_TRAINING_PATTERN_DISABLE);
1734	mtk_dp_train_set_pattern(mtk_dp, 0);
1735
1736	return -ETIMEDOUT;
1737}
1738
1739static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp)
1740{
1741	u8 val;
1742	ssize_t ret;
1743
1744	/*
1745	 * If we're eDP and capabilities were already parsed we can skip
1746	 * reading again because eDP panels aren't hotpluggable hence the
1747	 * caps and training information won't ever change in a boot life
1748	 */
1749	if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP &&
1750	    mtk_dp->rx_cap[DP_MAX_LINK_RATE] &&
1751	    mtk_dp->train_info.sink_ssc)
1752		return 0;
1753
1754	ret = drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap);
1755	if (ret < 0)
1756		return ret;
1757
1758	if (drm_dp_tps4_supported(mtk_dp->rx_cap))
1759		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_4;
1760	else if (drm_dp_tps3_supported(mtk_dp->rx_cap))
1761		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_3;
1762	else
1763		mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_2;
1764
1765	mtk_dp->train_info.sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap);
1766
1767	ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);
1768	if (ret < 1) {
1769		dev_err(mtk_dp->dev, "Read mstm cap failed: %zd\n", ret);
1770		return ret == 0 ? -EIO : ret;
1771	}
1772
1773	if (val & DP_MST_CAP) {
1774		/* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */
1775		ret = drm_dp_dpcd_readb(&mtk_dp->aux,
1776					DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,
1777					&val);
1778		if (ret < 1) {
1779			dev_err(mtk_dp->dev, "Read irq vector failed: %zd\n", ret);
1780			return ret == 0 ? -EIO : ret;
1781		}
1782
1783		if (val) {
1784			ret = drm_dp_dpcd_writeb(&mtk_dp->aux,
1785						 DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0,
1786						 val);
1787			if (ret < 0)
1788				return ret;
1789		}
1790	}
1791
1792	return 0;
1793}
1794
1795static bool mtk_dp_edid_parse_audio_capabilities(struct mtk_dp *mtk_dp,
1796						 struct mtk_dp_audio_cfg *cfg)
1797{
1798	if (!mtk_dp->data->audio_supported)
1799		return false;
1800
1801	if (mtk_dp->info.audio_cur_cfg.sad_count <= 0) {
1802		drm_info(mtk_dp->drm_dev, "The SADs is NULL\n");
1803		return false;
1804	}
1805
1806	return true;
1807}
1808
1809static void mtk_dp_train_change_mode(struct mtk_dp *mtk_dp)
1810{
1811	phy_reset(mtk_dp->phy);
1812	mtk_dp_reset_swing_pre_emphasis(mtk_dp);
1813}
1814
1815static int mtk_dp_training(struct mtk_dp *mtk_dp)
1816{
1817	int ret;
1818	u8 lane_count, link_rate, train_limit, max_link_rate;
1819
1820	link_rate = min_t(u8, mtk_dp->max_linkrate,
1821			  mtk_dp->rx_cap[DP_MAX_LINK_RATE]);
1822	max_link_rate = link_rate;
1823	lane_count = min_t(u8, mtk_dp->max_lanes,
1824			   drm_dp_max_lane_count(mtk_dp->rx_cap));
1825
1826	/*
1827	 * TPS are generated by the hardware pattern generator. From the
1828	 * hardware setting we need to disable this scramble setting before
1829	 * use the TPS pattern generator.
1830	 */
1831	mtk_dp_training_set_scramble(mtk_dp, false);
1832
1833	for (train_limit = 6; train_limit > 0; train_limit--) {
1834		mtk_dp_train_change_mode(mtk_dp);
1835
1836		ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count);
1837		if (ret)
1838			return ret;
1839
1840		ret = mtk_dp_train_cr(mtk_dp, lane_count);
1841		if (ret == -ENODEV) {
1842			return ret;
1843		} else if (ret) {
1844			/* reduce link rate */
1845			switch (link_rate) {
1846			case DP_LINK_BW_1_62:
1847				lane_count = lane_count / 2;
1848				link_rate = max_link_rate;
1849				if (lane_count == 0)
1850					return -EIO;
1851				break;
1852			case DP_LINK_BW_2_7:
1853				link_rate = DP_LINK_BW_1_62;
1854				break;
1855			case DP_LINK_BW_5_4:
1856				link_rate = DP_LINK_BW_2_7;
1857				break;
1858			case DP_LINK_BW_8_1:
1859				link_rate = DP_LINK_BW_5_4;
1860				break;
1861			default:
1862				return -EINVAL;
1863			}
1864			continue;
1865		}
1866
1867		ret = mtk_dp_train_eq(mtk_dp, lane_count);
1868		if (ret == -ENODEV) {
1869			return ret;
1870		} else if (ret) {
1871			/* reduce lane count */
1872			if (lane_count == 0)
1873				return -EIO;
1874			lane_count /= 2;
1875			continue;
1876		}
1877
1878		/* if we can run to this, training is done. */
1879		break;
1880	}
1881
1882	if (train_limit == 0)
1883		return -ETIMEDOUT;
1884
1885	mtk_dp->train_info.link_rate = link_rate;
1886	mtk_dp->train_info.lane_count = lane_count;
1887
1888	/*
1889	 * After training done, we need to output normal stream instead of TPS,
1890	 * so we need to enable scramble.
1891	 */
1892	mtk_dp_training_set_scramble(mtk_dp, true);
1893	mtk_dp_set_enhanced_frame_mode(mtk_dp);
1894
1895	return 0;
1896}
1897
1898static void mtk_dp_video_enable(struct mtk_dp *mtk_dp, bool enable)
1899{
1900	/* the mute sequence is different between enable and disable */
1901	if (enable) {
1902		mtk_dp_msa_bypass_enable(mtk_dp, false);
1903		mtk_dp_pg_enable(mtk_dp, false);
1904		mtk_dp_set_tx_out(mtk_dp);
1905		mtk_dp_video_mute(mtk_dp, false);
1906	} else {
1907		mtk_dp_video_mute(mtk_dp, true);
1908		mtk_dp_pg_enable(mtk_dp, true);
1909		mtk_dp_msa_bypass_enable(mtk_dp, true);
1910	}
1911}
1912
1913static void mtk_dp_audio_sdp_setup(struct mtk_dp *mtk_dp,
1914				   struct mtk_dp_audio_cfg *cfg)
1915{
1916	struct dp_sdp sdp;
1917	struct hdmi_audio_infoframe frame;
1918
1919	hdmi_audio_infoframe_init(&frame);
1920	frame.coding_type = HDMI_AUDIO_CODING_TYPE_PCM;
1921	frame.channels = cfg->channels;
1922	frame.sample_frequency = cfg->sample_rate;
1923
1924	switch (cfg->word_length_bits) {
1925	case 16:
1926		frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1927		break;
1928	case 20:
1929		frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_20;
1930		break;
1931	case 24:
1932	default:
1933		frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_24;
1934		break;
1935	}
1936
1937	hdmi_audio_infoframe_pack_for_dp(&frame, &sdp, MTK_DP_VERSION);
1938
1939	mtk_dp_audio_sdp_asp_set_channels(mtk_dp, cfg->channels);
1940	mtk_dp_setup_sdp_aui(mtk_dp, &sdp);
1941}
1942
1943static void mtk_dp_audio_setup(struct mtk_dp *mtk_dp,
1944			       struct mtk_dp_audio_cfg *cfg)
1945{
1946	mtk_dp_audio_sdp_setup(mtk_dp, cfg);
1947	mtk_dp_audio_channel_status_set(mtk_dp, cfg);
1948
1949	mtk_dp_audio_setup_channels(mtk_dp, cfg);
1950	mtk_dp_audio_set_divider(mtk_dp);
1951}
1952
1953static int mtk_dp_video_config(struct mtk_dp *mtk_dp)
1954{
1955	mtk_dp_config_mn_mode(mtk_dp);
1956	mtk_dp_set_msa(mtk_dp);
1957	mtk_dp_set_color_depth(mtk_dp);
1958	return mtk_dp_set_color_format(mtk_dp, mtk_dp->info.format);
1959}
1960
1961static void mtk_dp_init_port(struct mtk_dp *mtk_dp)
1962{
1963	mtk_dp_set_idle_pattern(mtk_dp, true);
1964	mtk_dp_initialize_priv_data(mtk_dp);
1965
1966	mtk_dp_initialize_settings(mtk_dp);
1967	mtk_dp_initialize_aux_settings(mtk_dp);
1968	mtk_dp_initialize_digital_settings(mtk_dp);
1969	mtk_dp_initialize_hpd_detect_settings(mtk_dp);
1970
1971	mtk_dp_digital_sw_reset(mtk_dp);
1972}
1973
1974static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
1975{
1976	struct mtk_dp *mtk_dp = dev;
1977	unsigned long flags;
1978	u32 status;
1979
1980	if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
1981		msleep(100);
1982
1983	spin_lock_irqsave(&mtk_dp->irq_thread_lock, flags);
1984	status = mtk_dp->irq_thread_handle;
1985	mtk_dp->irq_thread_handle = 0;
1986	spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);
1987
1988	if (status & MTK_DP_THREAD_CABLE_STATE_CHG) {
1989		if (mtk_dp->bridge.dev)
1990			drm_helper_hpd_irq_event(mtk_dp->bridge.dev);
1991
1992		if (!mtk_dp->train_info.cable_plugged_in) {
1993			mtk_dp_disable_sdp_aui(mtk_dp);
1994			memset(&mtk_dp->info.audio_cur_cfg, 0,
1995			       sizeof(mtk_dp->info.audio_cur_cfg));
1996
1997			mtk_dp->need_debounce = false;
1998			mod_timer(&mtk_dp->debounce_timer,
1999				  jiffies + msecs_to_jiffies(100) - 1);
2000		}
2001	}
2002
2003	if (status & MTK_DP_THREAD_HPD_EVENT)
2004		dev_dbg(mtk_dp->dev, "Receive IRQ from sink devices\n");
2005
2006	return IRQ_HANDLED;
2007}
2008
2009static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)
2010{
2011	struct mtk_dp *mtk_dp = dev;
2012	bool cable_sta_chg = false;
2013	unsigned long flags;
2014	u32 irq_status = mtk_dp_swirq_get_clear(mtk_dp) |
2015			 mtk_dp_hwirq_get_clear(mtk_dp);
2016
2017	if (!irq_status)
2018		return IRQ_HANDLED;
2019
2020	spin_lock_irqsave(&mtk_dp->irq_thread_lock, flags);
2021
2022	if (irq_status & MTK_DP_HPD_INTERRUPT)
2023		mtk_dp->irq_thread_handle |= MTK_DP_THREAD_HPD_EVENT;
2024
2025	/* Cable state is changed. */
2026	if (irq_status != MTK_DP_HPD_INTERRUPT) {
2027		mtk_dp->irq_thread_handle |= MTK_DP_THREAD_CABLE_STATE_CHG;
2028		cable_sta_chg = true;
2029	}
2030
2031	spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);
2032
2033	if (cable_sta_chg) {
2034		if (!!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) &
2035		       HPD_DB_DP_TRANS_P0_MASK))
2036			mtk_dp->train_info.cable_plugged_in = true;
2037		else
2038			mtk_dp->train_info.cable_plugged_in = false;
2039	}
2040
2041	return IRQ_WAKE_THREAD;
2042}
2043
2044static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wait_us)
2045{
2046	struct mtk_dp *mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);
2047	u32 val;
2048	int ret;
2049
2050	ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_TRANS_P0_3414,
2051				       val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
2052				       wait_us / 100, wait_us);
2053	if (ret) {
2054		mtk_dp->train_info.cable_plugged_in = false;
2055		return ret;
2056	}
2057
2058	mtk_dp->train_info.cable_plugged_in = true;
2059
2060	ret = mtk_dp_parse_capabilities(mtk_dp);
2061	if (ret) {
2062		dev_err(mtk_dp->dev, "Can't parse capabilities: %d\n", ret);
2063		return ret;
2064	}
2065
2066	return 0;
2067}
2068
2069static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,
2070			   struct platform_device *pdev)
2071{
2072	struct device_node *endpoint;
2073	struct device *dev = &pdev->dev;
2074	int ret;
2075	void __iomem *base;
2076	u32 linkrate;
2077	int len;
2078
2079	base = devm_platform_ioremap_resource(pdev, 0);
2080	if (IS_ERR(base))
2081		return PTR_ERR(base);
2082
2083	mtk_dp->regs = devm_regmap_init_mmio(dev, base, &mtk_dp_regmap_config);
2084	if (IS_ERR(mtk_dp->regs))
2085		return PTR_ERR(mtk_dp->regs);
2086
2087	endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 1, -1);
2088	len = of_property_count_elems_of_size(endpoint,
2089					      "data-lanes", sizeof(u32));
2090	of_node_put(endpoint);
2091	if (len < 0 || len > 4 || len == 3) {
2092		dev_err(dev, "invalid data lane size: %d\n", len);
2093		return -EINVAL;
2094	}
2095
2096	mtk_dp->max_lanes = len;
2097
2098	ret = device_property_read_u32(dev, "max-linkrate-mhz", &linkrate);
2099	if (ret) {
2100		dev_err(dev, "failed to read max linkrate: %d\n", ret);
2101		return ret;
2102	}
2103
2104	mtk_dp->max_linkrate = drm_dp_link_rate_to_bw_code(linkrate * 100);
2105
2106	return 0;
2107}
2108
2109static void mtk_dp_update_plugged_status(struct mtk_dp *mtk_dp)
2110{
2111	if (!mtk_dp->data->audio_supported || !mtk_dp->audio_enable)
2112		return;
2113
2114	mutex_lock(&mtk_dp->update_plugged_status_lock);
2115	if (mtk_dp->plugged_cb && mtk_dp->codec_dev)
2116		mtk_dp->plugged_cb(mtk_dp->codec_dev,
2117				   mtk_dp->enabled &
2118				   mtk_dp->info.audio_cur_cfg.detect_monitor);
2119	mutex_unlock(&mtk_dp->update_plugged_status_lock);
2120}
2121
2122static enum drm_connector_status
2123mtk_dp_bdg_detect(struct drm_bridge *bridge, struct drm_connector *connector)
2124{
2125	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2126	enum drm_connector_status ret = connector_status_disconnected;
2127	bool enabled = mtk_dp->enabled;
2128
2129	if (!mtk_dp->train_info.cable_plugged_in)
2130		return ret;
2131
2132	if (!enabled)
2133		mtk_dp_aux_panel_poweron(mtk_dp, true);
2134
2135	/*
2136	 * Some dongles still source HPD when they do not connect to any
2137	 * sink device. To avoid this, we need to read the sink count
2138	 * to make sure we do connect to sink devices. After this detect
2139	 * function, we just need to check the HPD connection to check
2140	 * whether we connect to a sink device.
2141	 */
2142
2143	if (drm_dp_read_sink_count(&mtk_dp->aux) > 0)
2144		ret = connector_status_connected;
2145
2146	if (!enabled)
2147		mtk_dp_aux_panel_poweron(mtk_dp, false);
2148
2149	return ret;
2150}
2151
2152static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge,
2153					       struct drm_connector *connector)
2154{
2155	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2156	bool enabled = mtk_dp->enabled;
2157	const struct drm_edid *drm_edid;
2158	struct mtk_dp_audio_cfg *audio_caps = &mtk_dp->info.audio_cur_cfg;
2159
2160	if (!enabled) {
2161		drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state);
2162		mtk_dp_aux_panel_poweron(mtk_dp, true);
2163	}
2164
2165	drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);
2166
2167	/*
2168	 * Parse capability here to let atomic_get_input_bus_fmts and
2169	 * mode_valid use the capability to calculate sink bitrates.
2170	 */
2171	if (mtk_dp_parse_capabilities(mtk_dp)) {
2172		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
2173		drm_edid_free(drm_edid);
2174		drm_edid = NULL;
2175	}
2176
2177	if (drm_edid) {
2178		/*
2179		 * FIXME: get rid of drm_edid_raw()
2180		 */
2181		const struct edid *edid = drm_edid_raw(drm_edid);
2182		struct cea_sad *sads;
2183		int ret;
2184
2185		ret = drm_edid_to_sad(edid, &sads);
2186		/* Ignore any errors */
2187		if (ret < 0)
2188			ret = 0;
2189		if (ret)
2190			kfree(sads);
2191		audio_caps->sad_count = ret;
2192
2193		/*
2194		 * FIXME: This should use connector->display_info.has_audio from
2195		 * a path that has read the EDID and called
2196		 * drm_edid_connector_update().
2197		 */
2198		audio_caps->detect_monitor = drm_detect_monitor_audio(edid);
2199	}
2200
2201	if (!enabled) {
2202		mtk_dp_aux_panel_poweron(mtk_dp, false);
2203		drm_atomic_bridge_chain_post_disable(bridge, connector->state->state);
2204	}
2205
2206	return drm_edid;
2207}
2208
2209static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux *mtk_aux,
2210				   struct drm_dp_aux_msg *msg)
2211{
2212	struct mtk_dp *mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);
2213	bool is_read;
2214	u8 request;
2215	size_t accessed_bytes = 0;
2216	int ret;
2217
2218	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP &&
2219	    !mtk_dp->train_info.cable_plugged_in) {
2220		ret = -EIO;
2221		goto err;
2222	}
2223
2224	switch (msg->request) {
2225	case DP_AUX_I2C_MOT:
2226	case DP_AUX_I2C_WRITE:
2227	case DP_AUX_NATIVE_WRITE:
2228	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
2229	case DP_AUX_I2C_WRITE_STATUS_UPDATE | DP_AUX_I2C_MOT:
2230		request = msg->request & ~DP_AUX_I2C_WRITE_STATUS_UPDATE;
2231		is_read = false;
2232		break;
2233	case DP_AUX_I2C_READ:
2234	case DP_AUX_NATIVE_READ:
2235	case DP_AUX_I2C_READ | DP_AUX_I2C_MOT:
2236		request = msg->request;
2237		is_read = true;
2238		break;
2239	default:
2240		dev_err(mtk_dp->dev, "invalid aux cmd = %d\n",
2241			msg->request);
2242		ret = -EINVAL;
2243		goto err;
2244	}
2245
2246	do {
2247		size_t to_access = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES,
2248					 msg->size - accessed_bytes);
2249
2250		ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, request,
2251					     msg->address + accessed_bytes,
2252					     msg->buffer + accessed_bytes,
2253					     to_access, &msg->reply);
2254
2255		if (ret) {
2256			dev_info(mtk_dp->dev,
2257				 "Failed to do AUX transfer: %d\n", ret);
2258			goto err;
2259		}
2260		accessed_bytes += to_access;
2261	} while (accessed_bytes < msg->size);
2262
2263	return msg->size;
2264err:
2265	msg->reply = DP_AUX_NATIVE_REPLY_NACK | DP_AUX_I2C_REPLY_NACK;
2266	return ret;
2267}
2268
2269static int mtk_dp_poweron(struct mtk_dp *mtk_dp)
2270{
2271	int ret;
2272
2273	ret = phy_init(mtk_dp->phy);
2274	if (ret) {
2275		dev_err(mtk_dp->dev, "Failed to initialize phy: %d\n", ret);
2276		return ret;
2277	}
2278
2279	mtk_dp_init_port(mtk_dp);
2280	mtk_dp_power_enable(mtk_dp);
2281
2282	return 0;
2283}
2284
2285static void mtk_dp_poweroff(struct mtk_dp *mtk_dp)
2286{
2287	mtk_dp_power_disable(mtk_dp);
2288	phy_exit(mtk_dp->phy);
2289}
2290
2291static int mtk_dp_bridge_attach(struct drm_bridge *bridge,
2292				struct drm_encoder *encoder,
2293				enum drm_bridge_attach_flags flags)
2294{
2295	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2296	int ret;
2297
2298	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2299		dev_err(mtk_dp->dev, "Driver does not provide a connector!");
2300		return -EINVAL;
2301	}
2302
2303	mtk_dp->aux.drm_dev = bridge->dev;
2304	ret = drm_dp_aux_register(&mtk_dp->aux);
2305	if (ret) {
2306		dev_err(mtk_dp->dev,
2307			"failed to register DP AUX channel: %d\n", ret);
2308		return ret;
2309	}
2310
2311	ret = mtk_dp_poweron(mtk_dp);
2312	if (ret)
2313		goto err_aux_register;
2314
2315	if (mtk_dp->next_bridge) {
2316		ret = drm_bridge_attach(encoder, mtk_dp->next_bridge,
2317					&mtk_dp->bridge, flags);
2318		if (ret) {
2319			drm_warn(mtk_dp->drm_dev,
2320				 "Failed to attach external bridge: %d\n", ret);
2321			goto err_bridge_attach;
2322		}
2323	}
2324
2325	mtk_dp->drm_dev = bridge->dev;
2326
2327	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP) {
2328		irq_clear_status_flags(mtk_dp->irq, IRQ_NOAUTOEN);
2329		enable_irq(mtk_dp->irq);
2330		mtk_dp_hwirq_enable(mtk_dp, true);
2331	}
2332
2333	return 0;
2334
2335err_bridge_attach:
2336	mtk_dp_poweroff(mtk_dp);
2337err_aux_register:
2338	drm_dp_aux_unregister(&mtk_dp->aux);
2339	return ret;
2340}
2341
2342static void mtk_dp_bridge_detach(struct drm_bridge *bridge)
2343{
2344	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2345
2346	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP) {
2347		mtk_dp_hwirq_enable(mtk_dp, false);
2348		disable_irq(mtk_dp->irq);
2349	}
2350	mtk_dp->drm_dev = NULL;
2351	mtk_dp_poweroff(mtk_dp);
2352	drm_dp_aux_unregister(&mtk_dp->aux);
2353}
2354
2355static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
2356					struct drm_atomic_state *state)
2357{
2358	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2359	int ret;
2360
2361	mtk_dp->conn = drm_atomic_get_new_connector_for_encoder(state,
2362								bridge->encoder);
2363	if (!mtk_dp->conn) {
2364		drm_err(mtk_dp->drm_dev,
2365			"Can't enable bridge as connector is missing\n");
2366		return;
2367	}
2368
2369	mtk_dp_aux_panel_poweron(mtk_dp, true);
2370
2371	/* Training */
2372	ret = mtk_dp_training(mtk_dp);
2373	if (ret) {
2374		drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
2375		goto power_off_aux;
2376	}
2377
2378	ret = mtk_dp_video_config(mtk_dp);
2379	if (ret)
2380		goto power_off_aux;
2381
2382	mtk_dp_video_enable(mtk_dp, true);
2383
2384	mtk_dp->audio_enable =
2385		mtk_dp_edid_parse_audio_capabilities(mtk_dp,
2386						     &mtk_dp->info.audio_cur_cfg);
2387	if (mtk_dp->audio_enable) {
2388		mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_cur_cfg);
2389		mtk_dp_audio_mute(mtk_dp, false);
2390	} else {
2391		memset(&mtk_dp->info.audio_cur_cfg, 0,
2392		       sizeof(mtk_dp->info.audio_cur_cfg));
2393	}
2394
2395	mtk_dp->enabled = true;
2396	mtk_dp_update_plugged_status(mtk_dp);
2397
2398	return;
2399power_off_aux:
2400	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
2401			   DP_PWR_STATE_BANDGAP_TPLL,
2402			   DP_PWR_STATE_MASK);
2403}
2404
2405static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge,
2406					 struct drm_atomic_state *state)
2407{
2408	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2409
2410	mtk_dp->enabled = false;
2411	mtk_dp_update_plugged_status(mtk_dp);
2412	mtk_dp_video_enable(mtk_dp, false);
2413	mtk_dp_audio_mute(mtk_dp, true);
2414
2415	if (mtk_dp->train_info.cable_plugged_in) {
2416		drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
2417		usleep_range(2000, 3000);
2418	}
2419
2420	/* power off aux */
2421	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
2422			   DP_PWR_STATE_BANDGAP_TPLL,
2423			   DP_PWR_STATE_MASK);
2424
2425	/* SDP path reset sw*/
2426	mtk_dp_sdp_path_reset(mtk_dp);
2427
2428	/* Ensure the sink is muted */
2429	msleep(20);
2430}
2431
2432static enum drm_mode_status
2433mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,
2434			 const struct drm_display_info *info,
2435			 const struct drm_display_mode *mode)
2436{
2437	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2438	u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;
2439	u32 lane_count_min = mtk_dp->train_info.lane_count;
2440	u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
2441		   lane_count_min;
2442
2443	/*
2444	 *FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2.
2445	 *The down-spread amplitude shall either be disabled (0.0%) or up
2446	 *to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead.
2447	 *
2448	 *Because rate is already divided by 10,
2449	 *mode->clock does not need to be multiplied by 10
2450	 */
2451	if ((rate * 97 / 100) < (mode->clock * bpp / 8))
2452		return MODE_CLOCK_HIGH;
2453
2454	return MODE_OK;
2455}
2456
2457static u32 *mtk_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2458						     struct drm_bridge_state *bridge_state,
2459						     struct drm_crtc_state *crtc_state,
2460						     struct drm_connector_state *conn_state,
2461						     unsigned int *num_output_fmts)
2462{
2463	u32 *output_fmts;
2464
2465	*num_output_fmts = 0;
2466	output_fmts = kmalloc(sizeof(*output_fmts), GFP_KERNEL);
2467	if (!output_fmts)
2468		return NULL;
2469	*num_output_fmts = 1;
2470	output_fmts[0] = MEDIA_BUS_FMT_FIXED;
2471	return output_fmts;
2472}
2473
2474static const u32 mt8195_input_fmts[] = {
2475	MEDIA_BUS_FMT_RGB888_1X24,
2476	MEDIA_BUS_FMT_YUV8_1X24,
2477	MEDIA_BUS_FMT_YUYV8_1X16,
2478};
2479
2480static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2481						    struct drm_bridge_state *bridge_state,
2482						    struct drm_crtc_state *crtc_state,
2483						    struct drm_connector_state *conn_state,
2484						    u32 output_fmt,
2485						    unsigned int *num_input_fmts)
2486{
2487	u32 *input_fmts;
2488	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2489	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2490	struct drm_display_info *display_info =
2491		&conn_state->connector->display_info;
2492	u32 lane_count_min = mtk_dp->train_info.lane_count;
2493	u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
2494		   lane_count_min;
2495
2496	*num_input_fmts = 0;
2497
2498	/*
2499	 * If the linkrate is smaller than datarate of RGB888, larger than
2500	 * datarate of YUV422 and sink device supports YUV422, we output YUV422
2501	 * format. Use this condition, we can support more resolution.
2502	 */
2503	if (((rate * 97 / 100) < (mode->clock * 24 / 8)) &&
2504	    ((rate * 97 / 100) > (mode->clock * 16 / 8)) &&
2505	    (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
2506		input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);
2507		if (!input_fmts)
2508			return NULL;
2509		*num_input_fmts = 1;
2510		input_fmts[0] = MEDIA_BUS_FMT_YUYV8_1X16;
2511	} else {
2512		input_fmts = kcalloc(ARRAY_SIZE(mt8195_input_fmts),
2513				     sizeof(*input_fmts),
2514				     GFP_KERNEL);
2515		if (!input_fmts)
2516			return NULL;
2517
2518		*num_input_fmts = ARRAY_SIZE(mt8195_input_fmts);
2519		memcpy(input_fmts, mt8195_input_fmts, sizeof(mt8195_input_fmts));
2520	}
2521
2522	return input_fmts;
2523}
2524
2525static int mtk_dp_bridge_atomic_check(struct drm_bridge *bridge,
2526				      struct drm_bridge_state *bridge_state,
2527				      struct drm_crtc_state *crtc_state,
2528				      struct drm_connector_state *conn_state)
2529{
2530	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
2531	struct drm_crtc *crtc = conn_state->crtc;
2532	unsigned int input_bus_format;
2533
2534	input_bus_format = bridge_state->input_bus_cfg.format;
2535
2536	dev_dbg(mtk_dp->dev, "input format 0x%04x, output format 0x%04x\n",
2537		bridge_state->input_bus_cfg.format,
2538		 bridge_state->output_bus_cfg.format);
2539
2540	if (input_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
2541		mtk_dp->info.format = DP_PIXELFORMAT_YUV422;
2542	else
2543		mtk_dp->info.format = DP_PIXELFORMAT_RGB;
2544
2545	if (!crtc) {
2546		drm_err(mtk_dp->drm_dev,
2547			"Can't enable bridge as connector state doesn't have a crtc\n");
2548		return -EINVAL;
2549	}
2550
2551	drm_display_mode_to_videomode(&crtc_state->adjusted_mode, &mtk_dp->info.vm);
2552
2553	return 0;
2554}
2555
2556static const struct drm_bridge_funcs mtk_dp_bridge_funcs = {
2557	.atomic_check = mtk_dp_bridge_atomic_check,
2558	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2559	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2560	.atomic_get_output_bus_fmts = mtk_dp_bridge_atomic_get_output_bus_fmts,
2561	.atomic_get_input_bus_fmts = mtk_dp_bridge_atomic_get_input_bus_fmts,
2562	.atomic_reset = drm_atomic_helper_bridge_reset,
2563	.attach = mtk_dp_bridge_attach,
2564	.detach = mtk_dp_bridge_detach,
2565	.atomic_enable = mtk_dp_bridge_atomic_enable,
2566	.atomic_disable = mtk_dp_bridge_atomic_disable,
2567	.mode_valid = mtk_dp_bridge_mode_valid,
2568	.edid_read = mtk_dp_edid_read,
2569	.detect = mtk_dp_bdg_detect,
2570};
2571
2572static void mtk_dp_debounce_timer(struct timer_list *t)
2573{
2574	struct mtk_dp *mtk_dp = timer_container_of(mtk_dp, t, debounce_timer);
2575
2576	mtk_dp->need_debounce = true;
2577}
2578
2579/*
2580 * HDMI audio codec callbacks
2581 */
2582static int mtk_dp_audio_hw_params(struct device *dev, void *data,
2583				  struct hdmi_codec_daifmt *daifmt,
2584				  struct hdmi_codec_params *params)
2585{
2586	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2587
2588	if (!mtk_dp->enabled) {
2589		dev_err(mtk_dp->dev, "%s, DP is not ready!\n", __func__);
2590		return -ENODEV;
2591	}
2592
2593	mtk_dp->info.audio_cur_cfg.channels = params->cea.channels;
2594	mtk_dp->info.audio_cur_cfg.sample_rate = params->sample_rate;
2595
2596	mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_cur_cfg);
2597
2598	return 0;
2599}
2600
2601static int mtk_dp_audio_startup(struct device *dev, void *data)
2602{
2603	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2604
2605	mtk_dp_audio_mute(mtk_dp, false);
2606
2607	return 0;
2608}
2609
2610static void mtk_dp_audio_shutdown(struct device *dev, void *data)
2611{
2612	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2613
2614	mtk_dp_audio_mute(mtk_dp, true);
2615}
2616
2617static int mtk_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
2618				size_t len)
2619{
2620	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2621
2622	if (mtk_dp->enabled)
2623		memcpy(buf, mtk_dp->conn->eld, len);
2624	else
2625		memset(buf, 0, len);
2626
2627	return 0;
2628}
2629
2630static int mtk_dp_audio_hook_plugged_cb(struct device *dev, void *data,
2631					hdmi_codec_plugged_cb fn,
2632					struct device *codec_dev)
2633{
2634	struct mtk_dp *mtk_dp = data;
2635
2636	mutex_lock(&mtk_dp->update_plugged_status_lock);
2637	mtk_dp->plugged_cb = fn;
2638	mtk_dp->codec_dev = codec_dev;
2639	mutex_unlock(&mtk_dp->update_plugged_status_lock);
2640
2641	mtk_dp_update_plugged_status(mtk_dp);
2642
2643	return 0;
2644}
2645
2646static const struct hdmi_codec_ops mtk_dp_audio_codec_ops = {
2647	.hw_params = mtk_dp_audio_hw_params,
2648	.audio_startup = mtk_dp_audio_startup,
2649	.audio_shutdown = mtk_dp_audio_shutdown,
2650	.get_eld = mtk_dp_audio_get_eld,
2651	.hook_plugged_cb = mtk_dp_audio_hook_plugged_cb,
2652};
2653
2654static int mtk_dp_register_audio_driver(struct device *dev)
2655{
2656	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2657	struct hdmi_codec_pdata codec_data = {
2658		.ops = &mtk_dp_audio_codec_ops,
2659		.max_i2s_channels = 8,
2660		.i2s = 1,
2661		.data = mtk_dp,
2662		.no_capture_mute = 1,
2663	};
2664
2665	mtk_dp->audio_pdev = platform_device_register_data(dev,
2666							   HDMI_CODEC_DRV_NAME,
2667							   PLATFORM_DEVID_AUTO,
2668							   &codec_data,
2669							   sizeof(codec_data));
2670	return PTR_ERR_OR_ZERO(mtk_dp->audio_pdev);
2671}
2672
2673static int mtk_dp_register_phy(struct mtk_dp *mtk_dp)
2674{
2675	struct device *dev = mtk_dp->dev;
2676
2677	mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek-dp-phy",
2678							PLATFORM_DEVID_AUTO,
2679							&mtk_dp->regs,
2680							sizeof(struct regmap *));
2681	if (IS_ERR(mtk_dp->phy_dev))
2682		return dev_err_probe(dev, PTR_ERR(mtk_dp->phy_dev),
2683				     "Failed to create device mediatek-dp-phy\n");
2684
2685	mtk_dp_get_calibration_data(mtk_dp);
2686
2687	mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp");
2688	if (IS_ERR(mtk_dp->phy)) {
2689		platform_device_unregister(mtk_dp->phy_dev);
2690		return dev_err_probe(dev, PTR_ERR(mtk_dp->phy), "Failed to get phy\n");
2691	}
2692
2693	return 0;
2694}
2695
2696static int mtk_dp_edp_link_panel(struct drm_dp_aux *mtk_aux)
2697{
2698	struct mtk_dp *mtk_dp = container_of(mtk_aux, struct mtk_dp, aux);
2699	struct device *dev = mtk_aux->dev;
2700	int ret;
2701
2702	mtk_dp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
2703
2704	/* Power off the DP and AUX: either detection is done, or no panel present */
2705	mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
2706			   DP_PWR_STATE_BANDGAP_TPLL,
2707			   DP_PWR_STATE_MASK);
2708	mtk_dp_power_disable(mtk_dp);
2709
2710	if (IS_ERR(mtk_dp->next_bridge)) {
2711		ret = PTR_ERR(mtk_dp->next_bridge);
2712		mtk_dp->next_bridge = NULL;
2713		return ret;
2714	}
2715
2716	/* For eDP, we add the bridge only if the panel was found */
2717	ret = devm_drm_bridge_add(dev, &mtk_dp->bridge);
2718	if (ret)
2719		return ret;
2720
2721	return 0;
2722}
2723
2724static int mtk_dp_probe(struct platform_device *pdev)
2725{
2726	struct mtk_dp *mtk_dp;
2727	struct device *dev = &pdev->dev;
2728	int ret;
2729
2730	mtk_dp = devm_drm_bridge_alloc(dev, struct mtk_dp, bridge,
2731				       &mtk_dp_bridge_funcs);
2732	if (IS_ERR(mtk_dp))
2733		return PTR_ERR(mtk_dp);
2734
2735	mtk_dp->dev = dev;
2736	mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);
2737
2738	ret = mtk_dp_dt_parse(mtk_dp, pdev);
2739	if (ret)
2740		return dev_err_probe(dev, ret, "Failed to parse dt\n");
2741
2742	/*
2743	 * Request the interrupt and install service routine only if we are
2744	 * on full DisplayPort.
2745	 * For eDP, polling the HPD instead is more convenient because we
2746	 * don't expect any (un)plug events during runtime, hence we can
2747	 * avoid some locking.
2748	 */
2749	if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP) {
2750		mtk_dp->irq = platform_get_irq(pdev, 0);
2751		if (mtk_dp->irq < 0)
2752			return dev_err_probe(dev, mtk_dp->irq,
2753					     "failed to request dp irq resource\n");
2754
2755		spin_lock_init(&mtk_dp->irq_thread_lock);
2756
2757		irq_set_status_flags(mtk_dp->irq, IRQ_NOAUTOEN);
2758		ret = devm_request_threaded_irq(dev, mtk_dp->irq, mtk_dp_hpd_event,
2759						mtk_dp_hpd_event_thread,
2760						IRQ_TYPE_LEVEL_HIGH, dev_name(dev),
2761						mtk_dp);
2762		if (ret)
2763			return dev_err_probe(dev, ret,
2764					     "failed to request mediatek dptx irq\n");
2765
2766		mtk_dp->need_debounce = true;
2767		timer_setup(&mtk_dp->debounce_timer, mtk_dp_debounce_timer, 0);
2768	}
2769
2770	mtk_dp->aux.name = "aux_mtk_dp";
2771	mtk_dp->aux.dev = dev;
2772	mtk_dp->aux.transfer = mtk_dp_aux_transfer;
2773	mtk_dp->aux.wait_hpd_asserted = mtk_dp_wait_hpd_asserted;
2774	drm_dp_aux_init(&mtk_dp->aux);
2775
2776	platform_set_drvdata(pdev, mtk_dp);
2777
2778	if (mtk_dp->data->audio_supported) {
2779		mutex_init(&mtk_dp->update_plugged_status_lock);
2780
2781		ret = mtk_dp_register_audio_driver(dev);
2782		if (ret)
2783			return dev_err_probe(dev, ret,
2784					     "Failed to register audio driver\n");
2785	}
2786
2787	ret = mtk_dp_register_phy(mtk_dp);
2788	if (ret)
2789		return ret;
2790
2791	mtk_dp->bridge.of_node = dev->of_node;
2792	mtk_dp->bridge.type = mtk_dp->data->bridge_type;
2793
2794	if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP) {
2795		/*
2796		 * Set the data lanes to idle in case the bootloader didn't
2797		 * properly close the eDP port to avoid stalls and then
2798		 * reinitialize, reset and power on the AUX block.
2799		 */
2800		mtk_dp_set_idle_pattern(mtk_dp, true);
2801		mtk_dp_initialize_aux_settings(mtk_dp);
2802		mtk_dp_power_enable(mtk_dp);
2803
2804		/* Disable HW interrupts: we don't need any for eDP */
2805		mtk_dp_hwirq_enable(mtk_dp, false);
2806
2807		/*
2808		 * Power on the AUX to allow reading the EDID from aux-bus:
2809		 * please note that it is necessary to call power off in the
2810		 * .done_probing() callback (mtk_dp_edp_link_panel), as only
2811		 * there we can safely assume that we finished reading EDID.
2812		 */
2813		mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
2814				   DP_PWR_STATE_BANDGAP_TPLL_LANE,
2815				   DP_PWR_STATE_MASK);
2816
2817		ret = devm_of_dp_aux_populate_bus(&mtk_dp->aux, mtk_dp_edp_link_panel);
2818		if (ret) {
2819			/* -ENODEV this means that the panel is not on the aux-bus */
2820			if (ret == -ENODEV) {
2821				ret = mtk_dp_edp_link_panel(&mtk_dp->aux);
2822				if (ret)
2823					return ret;
2824			} else {
2825				mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
2826						   DP_PWR_STATE_BANDGAP_TPLL,
2827						   DP_PWR_STATE_MASK);
2828				mtk_dp_power_disable(mtk_dp);
2829				return ret;
2830			}
2831		}
2832	} else {
2833		mtk_dp->bridge.ops = DRM_BRIDGE_OP_DETECT |
2834				     DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
2835		ret = devm_drm_bridge_add(dev, &mtk_dp->bridge);
2836		if (ret)
2837			return dev_err_probe(dev, ret, "Failed to add bridge\n");
2838	}
2839
2840	pm_runtime_enable(dev);
2841	pm_runtime_get_sync(dev);
2842
2843	return 0;
2844}
2845
2846static void mtk_dp_remove(struct platform_device *pdev)
2847{
2848	struct mtk_dp *mtk_dp = platform_get_drvdata(pdev);
2849
2850	pm_runtime_put(&pdev->dev);
2851	pm_runtime_disable(&pdev->dev);
2852	if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP)
2853		timer_delete_sync(&mtk_dp->debounce_timer);
2854	platform_device_unregister(mtk_dp->phy_dev);
2855	if (mtk_dp->audio_pdev)
2856		platform_device_unregister(mtk_dp->audio_pdev);
2857}
2858
2859#ifdef CONFIG_PM_SLEEP
2860static int mtk_dp_suspend(struct device *dev)
2861{
2862	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2863
2864	mtk_dp_power_disable(mtk_dp);
2865	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP)
2866		mtk_dp_hwirq_enable(mtk_dp, false);
2867	pm_runtime_put_sync(dev);
2868
2869	return 0;
2870}
2871
2872static int mtk_dp_resume(struct device *dev)
2873{
2874	struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
2875
2876	pm_runtime_get_sync(dev);
2877	mtk_dp_init_port(mtk_dp);
2878	if (mtk_dp->bridge.type != DRM_MODE_CONNECTOR_eDP)
2879		mtk_dp_hwirq_enable(mtk_dp, true);
2880	mtk_dp_power_enable(mtk_dp);
2881
2882	return 0;
2883}
2884#endif
2885
2886static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume);
2887
2888static const struct mtk_dp_data mt8188_dp_data = {
2889	.bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
2890	.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
2891	.efuse_fmt = mt8188_dp_efuse_fmt,
2892	.audio_supported = true,
2893	.audio_pkt_in_hblank_area = true,
2894	.audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
2895};
2896
2897static const struct mtk_dp_data mt8195_edp_data = {
2898	.bridge_type = DRM_MODE_CONNECTOR_eDP,
2899	.smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,
2900	.efuse_fmt = mt8195_edp_efuse_fmt,
2901	.audio_supported = false,
2902	.audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
2903};
2904
2905static const struct mtk_dp_data mt8195_dp_data = {
2906	.bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
2907	.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
2908	.efuse_fmt = mt8195_dp_efuse_fmt,
2909	.audio_supported = true,
2910	.audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
2911};
2912
2913static const struct of_device_id mtk_dp_of_match[] = {
2914	{
2915		.compatible = "mediatek,mt8188-edp-tx",
2916		.data = &mt8195_edp_data,
2917	},
2918	{
2919		.compatible = "mediatek,mt8188-dp-tx",
2920		.data = &mt8188_dp_data,
2921	},
2922	{
2923		.compatible = "mediatek,mt8195-edp-tx",
2924		.data = &mt8195_edp_data,
2925	},
2926	{
2927		.compatible = "mediatek,mt8195-dp-tx",
2928		.data = &mt8195_dp_data,
2929	},
2930	{},
2931};
2932MODULE_DEVICE_TABLE(of, mtk_dp_of_match);
2933
2934static struct platform_driver mtk_dp_driver = {
2935	.probe = mtk_dp_probe,
2936	.remove = mtk_dp_remove,
2937	.driver = {
2938		.name = "mediatek-drm-dp",
2939		.of_match_table = mtk_dp_of_match,
2940		.pm = &mtk_dp_pm_ops,
2941	},
2942};
2943
2944module_platform_driver(mtk_dp_driver);
2945
2946MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
2947MODULE_AUTHOR("Markus Schneider-Pargmann <msp@baylibre.com>");
2948MODULE_AUTHOR("Bo-Chen Chen <rex-bc.chen@mediatek.com>");
2949MODULE_DESCRIPTION("MediaTek DisplayPort Driver");
2950MODULE_LICENSE("GPL");
2951MODULE_SOFTDEP("pre: phy_mtk_dp");