kmb_drv.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright © 2018-2020 Intel Corporation
  4 */
  5
  6#include <linux/clk.h>
  7#include <linux/module.h>
  8#include <linux/of_graph.h>
  9#include <linux/of_platform.h>
 10#include <linux/of_reserved_mem.h>
 11#include <linux/mfd/syscon.h>
 12#include <linux/platform_device.h>
 13#include <linux/pm_runtime.h>
 14#include <linux/regmap.h>
 15
 16#include <drm/clients/drm_client_setup.h>
 17#include <drm/drm_atomic_helper.h>
 18#include <drm/drm_drv.h>
 19#include <drm/drm_fbdev_dma.h>
 20#include <drm/drm_gem_dma_helper.h>
 21#include <drm/drm_gem_framebuffer_helper.h>
 22#include <drm/drm_module.h>
 23#include <drm/drm_print.h>
 24#include <drm/drm_probe_helper.h>
 25#include <drm/drm_vblank.h>
 26
 27#include "kmb_drv.h"
 28#include "kmb_dsi.h"
 29#include "kmb_regs.h"
 30
 31static int kmb_display_clk_enable(struct kmb_drm_private *kmb)
 32{
 33	int ret = 0;
 34
 35	ret = clk_prepare_enable(kmb->kmb_clk.clk_lcd);
 36	if (ret) {
 37		drm_err(&kmb->drm, "Failed to enable LCD clock: %d\n", ret);
 38		return ret;
 39	}
 40	DRM_INFO("SUCCESS : enabled LCD clocks\n");
 41	return 0;
 42}
 43
 44static int kmb_initialize_clocks(struct kmb_drm_private *kmb, struct device *dev)
 45{
 46	int ret = 0;
 47	struct regmap *msscam;
 48
 49	kmb->kmb_clk.clk_lcd = devm_clk_get(dev, "clk_lcd");
 50	if (IS_ERR(kmb->kmb_clk.clk_lcd)) {
 51		drm_err(&kmb->drm, "clk_get() failed clk_lcd\n");
 52		return PTR_ERR(kmb->kmb_clk.clk_lcd);
 53	}
 54
 55	kmb->kmb_clk.clk_pll0 = devm_clk_get(dev, "clk_pll0");
 56	if (IS_ERR(kmb->kmb_clk.clk_pll0)) {
 57		drm_err(&kmb->drm, "clk_get() failed clk_pll0 ");
 58		return PTR_ERR(kmb->kmb_clk.clk_pll0);
 59	}
 60	kmb->sys_clk_mhz = clk_get_rate(kmb->kmb_clk.clk_pll0) / 1000000;
 61	drm_info(&kmb->drm, "system clk = %d Mhz", kmb->sys_clk_mhz);
 62
 63	ret =  kmb_dsi_clk_init(kmb->kmb_dsi);
 64
 65	/* Set LCD clock to 200 Mhz */
 66	clk_set_rate(kmb->kmb_clk.clk_lcd, KMB_LCD_DEFAULT_CLK);
 67	if (clk_get_rate(kmb->kmb_clk.clk_lcd) != KMB_LCD_DEFAULT_CLK) {
 68		drm_err(&kmb->drm, "failed to set to clk_lcd to %d\n",
 69			KMB_LCD_DEFAULT_CLK);
 70		return -1;
 71	}
 72	drm_dbg(&kmb->drm, "clk_lcd = %ld\n", clk_get_rate(kmb->kmb_clk.clk_lcd));
 73
 74	ret = kmb_display_clk_enable(kmb);
 75	if (ret)
 76		return ret;
 77
 78	msscam = syscon_regmap_lookup_by_compatible("intel,keembay-msscam");
 79	if (IS_ERR(msscam)) {
 80		drm_err(&kmb->drm, "failed to get msscam syscon");
 81		return -1;
 82	}
 83
 84	/* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */
 85	regmap_update_bits(msscam, MSS_CAM_CLK_CTRL, 0x1fff, 0x1fff);
 86	regmap_update_bits(msscam, MSS_CAM_RSTN_CTRL, 0xffffffff, 0xffffffff);
 87	return 0;
 88}
 89
 90static void kmb_display_clk_disable(struct kmb_drm_private *kmb)
 91{
 92	clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
 93}
 94
 95static void __iomem *kmb_map_mmio(struct drm_device *drm,
 96				  struct platform_device *pdev,
 97				  char *name)
 98{
 99	struct resource *res;
100	void __iomem *mem;
101
102	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
103	if (!res) {
104		drm_err(drm, "failed to get resource for %s", name);
105		return ERR_PTR(-ENOMEM);
106	}
107	mem = devm_ioremap_resource(drm->dev, res);
108	if (IS_ERR(mem))
109		drm_err(drm, "failed to ioremap %s registers", name);
110	return mem;
111}
112
113static int kmb_hw_init(struct drm_device *drm, unsigned long flags)
114{
115	struct kmb_drm_private *kmb = to_kmb(drm);
116	struct platform_device *pdev = to_platform_device(drm->dev);
117	int irq_lcd;
118	int ret = 0;
119
120	/* Map LCD MMIO registers */
121	kmb->lcd_mmio = kmb_map_mmio(drm, pdev, "lcd");
122	if (IS_ERR(kmb->lcd_mmio)) {
123		drm_err(&kmb->drm, "failed to map LCD registers\n");
124		return -ENOMEM;
125	}
126
127	/* Map MIPI MMIO registers */
128	ret = kmb_dsi_map_mmio(kmb->kmb_dsi);
129	if (ret)
130		return ret;
131
132	/* Enable display clocks */
133	kmb_initialize_clocks(kmb, &pdev->dev);
134
135	/* Register irqs here - section 17.3 in databook
136	 * lists LCD at 79 and 82 for MIPI under MSS CPU -
137	 * firmware has redirected 79 to A53 IRQ 33
138	 */
139
140	/* Allocate LCD interrupt resources */
141	irq_lcd = platform_get_irq(pdev, 0);
142	if (irq_lcd < 0) {
143		ret = irq_lcd;
144		drm_err(&kmb->drm, "irq_lcd not found");
145		goto setup_fail;
146	}
147
148	/* Get the optional framebuffer memory resource */
149	ret = of_reserved_mem_device_init(drm->dev);
150	if (ret && ret != -ENODEV)
151		return ret;
152
153	spin_lock_init(&kmb->irq_lock);
154
155	kmb->irq_lcd = irq_lcd;
156
157	return 0;
158
159 setup_fail:
160	of_reserved_mem_device_release(drm->dev);
161
162	return ret;
163}
164
165static const struct drm_mode_config_funcs kmb_mode_config_funcs = {
166	.fb_create = drm_gem_fb_create,
167	.atomic_check = drm_atomic_helper_check,
168	.atomic_commit = drm_atomic_helper_commit,
169};
170
171static int kmb_setup_mode_config(struct drm_device *drm)
172{
173	int ret;
174	struct kmb_drm_private *kmb = to_kmb(drm);
175
176	ret = drmm_mode_config_init(drm);
177	if (ret)
178		return ret;
179	drm->mode_config.min_width = KMB_FB_MIN_WIDTH;
180	drm->mode_config.min_height = KMB_FB_MIN_HEIGHT;
181	drm->mode_config.max_width = KMB_FB_MAX_WIDTH;
182	drm->mode_config.max_height = KMB_FB_MAX_HEIGHT;
183	drm->mode_config.preferred_depth = 24;
184	drm->mode_config.funcs = &kmb_mode_config_funcs;
185
186	ret = kmb_setup_crtc(drm);
187	if (ret < 0) {
188		drm_err(drm, "failed to create crtc\n");
189		return ret;
190	}
191	ret = kmb_dsi_encoder_init(drm, kmb->kmb_dsi);
192	/* Set the CRTC's port so that the encoder component can find it */
193	kmb->crtc.port = of_graph_get_port_by_id(drm->dev->of_node, 0);
194	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
195	if (ret < 0) {
196		drm_err(drm, "failed to initialize vblank\n");
197		pm_runtime_disable(drm->dev);
198		return ret;
199	}
200
201	drm_mode_config_reset(drm);
202	return 0;
203}
204
205static irqreturn_t handle_lcd_irq(struct drm_device *dev)
206{
207	unsigned long status, val, val1;
208	int plane_id, dma0_state, dma1_state;
209	struct kmb_drm_private *kmb = to_kmb(dev);
210	u32 ctrl = 0;
211
212	status = kmb_read_lcd(kmb, LCD_INT_STATUS);
213
214	spin_lock(&kmb->irq_lock);
215	if (status & LCD_INT_EOF) {
216		kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF);
217
218		/* When disabling/enabling LCD layers, the change takes effect
219		 * immediately and does not wait for EOF (end of frame).
220		 * When kmb_plane_atomic_disable is called, mark the plane as
221		 * disabled but actually disable the plane when EOF irq is
222		 * being handled.
223		 */
224		for (plane_id = LAYER_0;
225				plane_id < KMB_MAX_PLANES; plane_id++) {
226			if (kmb->plane_status[plane_id].disable) {
227				kmb_clr_bitmask_lcd(kmb,
228						    LCD_LAYERn_DMA_CFG
229						    (plane_id),
230						    LCD_DMA_LAYER_ENABLE);
231
232				kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
233						    kmb->plane_status[plane_id].ctrl);
234
235				ctrl = kmb_read_lcd(kmb, LCD_CONTROL);
236				if (!(ctrl & (LCD_CTRL_VL1_ENABLE |
237				    LCD_CTRL_VL2_ENABLE |
238				    LCD_CTRL_GL1_ENABLE |
239				    LCD_CTRL_GL2_ENABLE))) {
240					/* If no LCD layers are using DMA,
241					 * then disable DMA pipelined AXI read
242					 * transactions.
243					 */
244					kmb_clr_bitmask_lcd(kmb, LCD_CONTROL,
245							    LCD_CTRL_PIPELINE_DMA);
246				}
247
248				kmb->plane_status[plane_id].disable = false;
249			}
250		}
251		if (kmb->kmb_under_flow) {
252			/* DMA Recovery after underflow */
253			dma0_state = (kmb->layer_no == 0) ?
254			    LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE;
255			dma1_state = (kmb->layer_no == 0) ?
256			    LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE;
257
258			do {
259				kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
260				val = kmb_read_lcd(kmb, dma0_state)
261				    & LCD_DMA_STATE_ACTIVE;
262				val1 = kmb_read_lcd(kmb, dma1_state)
263				    & LCD_DMA_STATE_ACTIVE;
264			} while ((val || val1));
265			/* disable dma */
266			kmb_clr_bitmask_lcd(kmb,
267					    LCD_LAYERn_DMA_CFG(kmb->layer_no),
268					    LCD_DMA_LAYER_ENABLE);
269			kmb_write_lcd(kmb, LCD_FIFO_FLUSH, 1);
270			kmb->kmb_flush_done = 1;
271			kmb->kmb_under_flow = 0;
272		}
273	}
274
275	if (status & LCD_INT_LINE_CMP) {
276		/* clear line compare interrupt */
277		kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LINE_CMP);
278	}
279
280	if (status & LCD_INT_VERT_COMP) {
281		/* Read VSTATUS */
282		val = kmb_read_lcd(kmb, LCD_VSTATUS);
283		val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK);
284		switch (val) {
285		case LCD_VSTATUS_COMPARE_VSYNC:
286			/* Clear vertical compare interrupt */
287			kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
288			if (kmb->kmb_flush_done) {
289				kmb_set_bitmask_lcd(kmb,
290						    LCD_LAYERn_DMA_CFG
291						    (kmb->layer_no),
292						    LCD_DMA_LAYER_ENABLE);
293				kmb->kmb_flush_done = 0;
294			}
295			drm_crtc_handle_vblank(&kmb->crtc);
296			break;
297		case LCD_VSTATUS_COMPARE_BACKPORCH:
298		case LCD_VSTATUS_COMPARE_ACTIVE:
299		case LCD_VSTATUS_COMPARE_FRONT_PORCH:
300			kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
301			break;
302		}
303	}
304	if (status & LCD_INT_DMA_ERR) {
305		val =
306		    (status & LCD_INT_DMA_ERR &
307		     kmb_read_lcd(kmb, LCD_INT_ENABLE));
308		/* LAYER0 - VL0 */
309		if (val & (LAYER0_DMA_FIFO_UNDERFLOW |
310			   LAYER0_DMA_CB_FIFO_UNDERFLOW |
311			   LAYER0_DMA_CR_FIFO_UNDERFLOW)) {
312			kmb->kmb_under_flow++;
313			drm_info(&kmb->drm,
314				 "!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d",
315			     val, kmb->kmb_under_flow);
316			/* disable underflow interrupt */
317			kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
318					    LAYER0_DMA_FIFO_UNDERFLOW |
319					    LAYER0_DMA_CB_FIFO_UNDERFLOW |
320					    LAYER0_DMA_CR_FIFO_UNDERFLOW);
321			kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
322					    LAYER0_DMA_CB_FIFO_UNDERFLOW |
323					    LAYER0_DMA_FIFO_UNDERFLOW |
324					    LAYER0_DMA_CR_FIFO_UNDERFLOW);
325			/* disable auto restart mode */
326			kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(0),
327					    LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
328
329			kmb->layer_no = 0;
330		}
331
332		if (val & LAYER0_DMA_FIFO_OVERFLOW)
333			drm_dbg(&kmb->drm,
334				"LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val);
335		if (val & LAYER0_DMA_CB_FIFO_OVERFLOW)
336			drm_dbg(&kmb->drm,
337				"LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val);
338		if (val & LAYER0_DMA_CR_FIFO_OVERFLOW)
339			drm_dbg(&kmb->drm,
340				"LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val);
341
342		/* LAYER1 - VL1 */
343		if (val & (LAYER1_DMA_FIFO_UNDERFLOW |
344			   LAYER1_DMA_CB_FIFO_UNDERFLOW |
345			   LAYER1_DMA_CR_FIFO_UNDERFLOW)) {
346			kmb->kmb_under_flow++;
347			drm_info(&kmb->drm,
348				 "!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d",
349			     val, kmb->kmb_under_flow);
350			/* disable underflow interrupt */
351			kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
352					    LAYER1_DMA_FIFO_UNDERFLOW |
353					    LAYER1_DMA_CB_FIFO_UNDERFLOW |
354					    LAYER1_DMA_CR_FIFO_UNDERFLOW);
355			kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR,
356					    LAYER1_DMA_CB_FIFO_UNDERFLOW |
357					    LAYER1_DMA_FIFO_UNDERFLOW |
358					    LAYER1_DMA_CR_FIFO_UNDERFLOW);
359			/* disable auto restart mode */
360			kmb_clr_bitmask_lcd(kmb, LCD_LAYERn_DMA_CFG(1),
361					    LCD_DMA_LAYER_CONT_PING_PONG_UPDATE);
362			kmb->layer_no = 1;
363		}
364
365		/* LAYER1 - VL1 */
366		if (val & LAYER1_DMA_FIFO_OVERFLOW)
367			drm_dbg(&kmb->drm,
368				"LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val);
369		if (val & LAYER1_DMA_CB_FIFO_OVERFLOW)
370			drm_dbg(&kmb->drm,
371				"LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val);
372		if (val & LAYER1_DMA_CR_FIFO_OVERFLOW)
373			drm_dbg(&kmb->drm,
374				"LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val);
375
376		/* LAYER2 - GL0 */
377		if (val & LAYER2_DMA_FIFO_UNDERFLOW)
378			drm_dbg(&kmb->drm,
379				"LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val);
380		if (val & LAYER2_DMA_FIFO_OVERFLOW)
381			drm_dbg(&kmb->drm,
382				"LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val);
383
384		/* LAYER3 - GL1 */
385		if (val & LAYER3_DMA_FIFO_UNDERFLOW)
386			drm_dbg(&kmb->drm,
387				"LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
388		if (val & LAYER3_DMA_FIFO_OVERFLOW)
389			drm_dbg(&kmb->drm,
390				"LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
391	}
392
393	spin_unlock(&kmb->irq_lock);
394
395	if (status & LCD_INT_LAYER) {
396		/* Clear layer interrupts */
397		kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_LAYER);
398	}
399
400	/* Clear all interrupts */
401	kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, 1);
402	return IRQ_HANDLED;
403}
404
405/* IRQ handler */
406static irqreturn_t kmb_isr(int irq, void *arg)
407{
408	struct drm_device *dev = (struct drm_device *)arg;
409
410	handle_lcd_irq(dev);
411	return IRQ_HANDLED;
412}
413
414static void kmb_irq_reset(struct drm_device *drm)
415{
416	kmb_write_lcd(to_kmb(drm), LCD_INT_CLEAR, 0xFFFF);
417	kmb_write_lcd(to_kmb(drm), LCD_INT_ENABLE, 0);
418}
419
420static int kmb_irq_install(struct drm_device *drm, unsigned int irq)
421{
422	if (irq == IRQ_NOTCONNECTED)
423		return -ENOTCONN;
424
425	kmb_irq_reset(drm);
426
427	return request_irq(irq, kmb_isr, 0, drm->driver->name, drm);
428}
429
430static void kmb_irq_uninstall(struct drm_device *drm)
431{
432	struct kmb_drm_private *kmb = to_kmb(drm);
433
434	kmb_irq_reset(drm);
435	free_irq(kmb->irq_lcd, drm);
436}
437
438DEFINE_DRM_GEM_DMA_FOPS(fops);
439
440static const struct drm_driver kmb_driver = {
441	.driver_features = DRIVER_GEM |
442	    DRIVER_MODESET | DRIVER_ATOMIC,
443	/* GEM Operations */
444	.fops = &fops,
445	DRM_GEM_DMA_DRIVER_OPS_VMAP,
446	DRM_FBDEV_DMA_DRIVER_OPS,
447	.name = "kmb-drm",
448	.desc = "KEEMBAY DISPLAY DRIVER",
449	.major = DRIVER_MAJOR,
450	.minor = DRIVER_MINOR,
451};
452
453static void kmb_remove(struct platform_device *pdev)
454{
455	struct device *dev = &pdev->dev;
456	struct drm_device *drm = dev_get_drvdata(dev);
457	struct kmb_drm_private *kmb = to_kmb(drm);
458
459	drm_dev_unregister(drm);
460	drm_kms_helper_poll_fini(drm);
461	of_node_put(kmb->crtc.port);
462	kmb->crtc.port = NULL;
463	pm_runtime_get_sync(drm->dev);
464	kmb_irq_uninstall(drm);
465	pm_runtime_put_sync(drm->dev);
466	pm_runtime_disable(drm->dev);
467
468	of_reserved_mem_device_release(drm->dev);
469
470	/* Release clks */
471	kmb_display_clk_disable(kmb);
472
473	dev_set_drvdata(dev, NULL);
474
475	/* Unregister DSI host */
476	kmb_dsi_host_unregister(kmb->kmb_dsi);
477	drm_atomic_helper_shutdown(drm);
478}
479
480static int kmb_probe(struct platform_device *pdev)
481{
482	struct device *dev = get_device(&pdev->dev);
483	struct kmb_drm_private *kmb;
484	int ret = 0;
485	struct device_node *dsi_in;
486	struct device_node *dsi_node;
487	struct platform_device *dsi_pdev;
488
489	/* The bridge (ADV 7535) will return -EPROBE_DEFER until it
490	 * has a mipi_dsi_host to register its device to. So, we
491	 * first register the DSI host during probe time, and then return
492	 * -EPROBE_DEFER until the bridge is loaded. Probe will be called again
493	 *  and then the rest of the driver initialization can proceed
494	 *  afterwards and the bridge can be successfully attached.
495	 */
496	dsi_in = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
497	if (!dsi_in) {
498		DRM_ERROR("Failed to get dsi_in node info from DT");
499		return -EINVAL;
500	}
501	dsi_node = of_graph_get_remote_port_parent(dsi_in);
502	if (!dsi_node) {
503		of_node_put(dsi_in);
504		DRM_ERROR("Failed to get dsi node from DT\n");
505		return -EINVAL;
506	}
507
508	dsi_pdev = of_find_device_by_node(dsi_node);
509	if (!dsi_pdev) {
510		of_node_put(dsi_in);
511		of_node_put(dsi_node);
512		DRM_ERROR("Failed to get dsi platform device\n");
513		return -EINVAL;
514	}
515
516	of_node_put(dsi_in);
517	of_node_put(dsi_node);
518	ret = kmb_dsi_host_bridge_init(get_device(&dsi_pdev->dev));
519
520	if (ret == -EPROBE_DEFER) {
521		return -EPROBE_DEFER;
522	} else if (ret) {
523		DRM_ERROR("probe failed to initialize DSI host bridge\n");
524		return ret;
525	}
526
527	/* Create DRM device */
528	kmb = devm_drm_dev_alloc(dev, &kmb_driver,
529				 struct kmb_drm_private, drm);
530	if (IS_ERR(kmb))
531		return PTR_ERR(kmb);
532
533	dev_set_drvdata(dev, &kmb->drm);
534
535	/* Initialize MIPI DSI */
536	kmb->kmb_dsi = kmb_dsi_init(dsi_pdev);
537	if (IS_ERR(kmb->kmb_dsi)) {
538		drm_err(&kmb->drm, "failed to initialize DSI\n");
539		ret = PTR_ERR(kmb->kmb_dsi);
540		goto err_free1;
541	}
542
543	kmb->kmb_dsi->dev = &dsi_pdev->dev;
544	kmb->kmb_dsi->pdev = dsi_pdev;
545	ret = kmb_hw_init(&kmb->drm, 0);
546	if (ret)
547		goto err_free1;
548
549	ret = kmb_setup_mode_config(&kmb->drm);
550	if (ret)
551		goto err_free;
552
553	ret = kmb_irq_install(&kmb->drm, kmb->irq_lcd);
554	if (ret < 0) {
555		drm_err(&kmb->drm, "failed to install IRQ handler\n");
556		goto err_irq;
557	}
558
559	drm_kms_helper_poll_init(&kmb->drm);
560
561	/* Register graphics device with the kernel */
562	ret = drm_dev_register(&kmb->drm, 0);
563	if (ret)
564		goto err_register;
565
566	drm_client_setup(&kmb->drm, NULL);
567
568	return 0;
569
570 err_register:
571	drm_kms_helper_poll_fini(&kmb->drm);
572 err_irq:
573	pm_runtime_disable(kmb->drm.dev);
574 err_free:
575	drm_crtc_cleanup(&kmb->crtc);
576	drm_mode_config_cleanup(&kmb->drm);
577 err_free1:
578	dev_set_drvdata(dev, NULL);
579	kmb_dsi_host_unregister(kmb->kmb_dsi);
580
581	return ret;
582}
583
584static const struct of_device_id kmb_of_match[] = {
585	{.compatible = "intel,keembay-display"},
586	{},
587};
588
589MODULE_DEVICE_TABLE(of, kmb_of_match);
590
591static int __maybe_unused kmb_pm_suspend(struct device *dev)
592{
593	struct drm_device *drm = dev_get_drvdata(dev);
594	struct kmb_drm_private *kmb = to_kmb(drm);
595
596	drm_kms_helper_poll_disable(drm);
597
598	kmb->state = drm_atomic_helper_suspend(drm);
599	if (IS_ERR(kmb->state)) {
600		drm_kms_helper_poll_enable(drm);
601		return PTR_ERR(kmb->state);
602	}
603
604	return 0;
605}
606
607static int __maybe_unused kmb_pm_resume(struct device *dev)
608{
609	struct drm_device *drm = dev_get_drvdata(dev);
610	struct kmb_drm_private *kmb = drm ? to_kmb(drm) : NULL;
611
612	if (!kmb)
613		return 0;
614
615	drm_atomic_helper_resume(drm, kmb->state);
616	drm_kms_helper_poll_enable(drm);
617
618	return 0;
619}
620
621static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume);
622
623static struct platform_driver kmb_platform_driver = {
624	.probe = kmb_probe,
625	.remove = kmb_remove,
626	.driver = {
627		.name = "kmb-drm",
628		.pm = &kmb_pm_ops,
629		.of_match_table = kmb_of_match,
630	},
631};
632
633drm_module_platform_driver(kmb_platform_driver);
634
635MODULE_AUTHOR("Intel Corporation");
636MODULE_DESCRIPTION("Keembay Display driver");
637MODULE_LICENSE("GPL v2");