pvr_fw_meta.c

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/* Copyright (c) 2023 Imagination Technologies Ltd. */
  3
  4#include "pvr_device.h"
  5#include "pvr_fw.h"
  6#include "pvr_fw_info.h"
  7#include "pvr_fw_meta.h"
  8#include "pvr_gem.h"
  9#include "pvr_rogue_cr_defs.h"
 10#include "pvr_rogue_meta.h"
 11#include "pvr_vm.h"
 12
 13#include <linux/compiler.h>
 14#include <linux/delay.h>
 15#include <linux/firmware.h>
 16#include <linux/ktime.h>
 17#include <linux/types.h>
 18
 19#include <drm/drm_print.h>
 20
 21#define ROGUE_FW_HEAP_META_SHIFT 25 /* 32 MB */
 22
 23#define POLL_TIMEOUT_USEC 1000000
 24
 25/**
 26 * pvr_meta_cr_read32() - Read a META register via the Slave Port
 27 * @pvr_dev: Device pointer.
 28 * @reg_addr: Address of register to read.
 29 * @reg_value_out: Pointer to location to store register value.
 30 *
 31 * Returns:
 32 *  * 0 on success, or
 33 *  * Any error returned by pvr_cr_poll_reg32().
 34 */
 35int
 36pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out)
 37{
 38	int err;
 39
 40	/* Wait for Slave Port to be Ready. */
 41	err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
 42				ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
 43					ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
 44				ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
 45					ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
 46				POLL_TIMEOUT_USEC);
 47	if (err)
 48		return err;
 49
 50	/* Issue a Read. */
 51	pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0,
 52		       reg_addr | ROGUE_CR_META_SP_MSLVCTRL0_RD_EN);
 53	(void)pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0); /* Fence write. */
 54
 55	/* Wait for Slave Port to be Ready. */
 56	err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
 57				ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
 58					ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
 59				ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
 60					ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
 61				POLL_TIMEOUT_USEC);
 62	if (err)
 63		return err;
 64
 65	*reg_value_out = pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVDATAX);
 66
 67	return 0;
 68}
 69
 70static int
 71pvr_meta_wrapper_init(struct pvr_device *pvr_dev)
 72{
 73	u64 garten_config;
 74
 75	/* Configure META to Master boot. */
 76	pvr_cr_write64(pvr_dev, ROGUE_CR_META_BOOT, ROGUE_CR_META_BOOT_MODE_EN);
 77
 78	/* Set Garten IDLE to META idle and Set the Garten Wrapper BIF Fence address. */
 79
 80	/* Garten IDLE bit controlled by META. */
 81	garten_config = ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META;
 82
 83	/* The fence addr is set during the fw init sequence. */
 84
 85	/* Set PC = 0 for fences. */
 86	garten_config &=
 87		ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK;
 88	garten_config |=
 89		(u64)MMU_CONTEXT_MAPPING_FWPRIV
 90		<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT;
 91
 92	/* Set SLC DM=META. */
 93	garten_config |= ((u64)ROGUE_FW_SEGMMU_META_BIFDM_ID)
 94			 << ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT;
 95
 96	pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, garten_config);
 97
 98	return 0;
 99}
100
101static __always_inline void
102add_boot_arg(u32 **boot_conf, u32 param, u32 data)
103{
104	*(*boot_conf)++ = param;
105	*(*boot_conf)++ = data;
106}
107
108static int
109meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
110		     struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr,
111		     u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, const u32 fw_size)
112{
113	struct rogue_meta_ldr_l2_data_blk *l2_block =
114		(struct rogue_meta_ldr_l2_data_blk *)(fw +
115						      l1_data->cmd_data[1]);
116	struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
117	u32 offset = l1_data->cmd_data[0];
118	u32 data_size;
119	void *write_addr;
120	int err;
121
122	/* Verify header is within bounds. */
123	if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size)
124		return -EINVAL;
125
126	data_size = l2_block->length - 6 /* L2 Tag length and checksum */;
127
128	/* Verify data is within bounds. */
129	if (((u8 *)l2_block->block_data - fw) >= fw_size ||
130	    ((((u8 *)l2_block->block_data) + data_size) - fw) >= fw_size)
131		return -EINVAL;
132
133	if (!ROGUE_META_IS_COREMEM_CODE(offset, coremem_size) &&
134	    !ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
135		/* Global range is aliased to local range */
136		offset &= ~META_MEM_GLOBAL_RANGE_BIT;
137	}
138
139	err = pvr_fw_find_mmu_segment(pvr_dev, offset, data_size, fw_code_ptr, fw_data_ptr,
140				      fw_core_code_ptr, fw_core_data_ptr, &write_addr);
141	if (err) {
142		drm_err(drm_dev,
143			"Addr 0x%x (size: %d) not found in any firmware segment",
144			offset, data_size);
145		return err;
146	}
147
148	memcpy(write_addr, l2_block->block_data, data_size);
149
150	return 0;
151}
152
153static int
154meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
155		     struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size,
156		     u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr)
157{
158	struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
159	u32 offset = l1_data->cmd_data[0];
160	u32 byte_count = l1_data->cmd_data[1];
161	void *write_addr;
162	int err;
163
164	if (ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
165		/* cannot zero coremem directly */
166		return 0;
167	}
168
169	/* Global range is aliased to local range */
170	offset &= ~META_MEM_GLOBAL_RANGE_BIT;
171
172	err = pvr_fw_find_mmu_segment(pvr_dev, offset, byte_count, fw_code_ptr, fw_data_ptr,
173				      fw_core_code_ptr, fw_core_data_ptr, &write_addr);
174	if (err) {
175		drm_err(drm_dev,
176			"Addr 0x%x (size: %d) not found in any firmware segment",
177			offset, byte_count);
178		return err;
179	}
180
181	memset(write_addr, 0, byte_count);
182
183	return 0;
184}
185
186static int
187meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
188		    struct rogue_meta_ldr_l1_data_blk *l1_data,
189		    const u32 fw_size, u32 **boot_conf_ptr)
190{
191	struct rogue_meta_ldr_l2_data_blk *l2_block =
192		(struct rogue_meta_ldr_l2_data_blk *)(fw +
193						      l1_data->cmd_data[0]);
194	struct rogue_meta_ldr_cfg_blk *config_command;
195	u32 l2_block_size;
196	u32 curr_block_size = 0;
197	u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
198
199	/* Verify block header is within bounds. */
200	if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size)
201		return -EINVAL;
202
203	l2_block_size = l2_block->length - 6 /* L2 Tag length and checksum */;
204	config_command = (struct rogue_meta_ldr_cfg_blk *)l2_block->block_data;
205
206	if (((u8 *)config_command - fw) >= fw_size ||
207	    ((((u8 *)config_command) + l2_block_size) - fw) >= fw_size)
208		return -EINVAL;
209
210	while (l2_block_size >= 12) {
211		if (config_command->type != ROGUE_META_LDR_CFG_WRITE)
212			return -EINVAL;
213
214		/*
215		 * Only write to bootloader if we got a valid pointer to the FW
216		 * code allocation.
217		 */
218		if (boot_conf) {
219			u32 register_offset = config_command->block_data[0];
220			u32 register_value = config_command->block_data[1];
221
222			/* Do register write */
223			add_boot_arg(&boot_conf, register_offset,
224				     register_value);
225		}
226
227		curr_block_size = 12;
228		l2_block_size -= curr_block_size;
229		config_command = (struct rogue_meta_ldr_cfg_blk
230					  *)((uintptr_t)config_command +
231					     curr_block_size);
232	}
233
234	if (boot_conf_ptr)
235		*boot_conf_ptr = boot_conf;
236
237	return 0;
238}
239
240/**
241 * process_ldr_command_stream() - Process LDR firmware image and populate
242 *                                firmware sections
243 * @pvr_dev: Device pointer.
244 * @fw: Pointer to firmware image.
245 * @fw_code_ptr: Pointer to FW code section.
246 * @fw_data_ptr: Pointer to FW data section.
247 * @fw_core_code_ptr: Pointer to FW coremem code section.
248 * @fw_core_data_ptr: Pointer to FW coremem data section.
249 * @boot_conf_ptr: Pointer to boot config argument pointer.
250 *
251 * Returns :
252 *  * 0 on success, or
253 *  * -EINVAL on any error in LDR command stream.
254 */
255static int
256process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr,
257			   u8 *fw_data_ptr, u8 *fw_core_code_ptr,
258			   u8 *fw_core_data_ptr, u32 **boot_conf_ptr)
259{
260	struct drm_device *drm_dev = from_pvr_device(pvr_dev);
261	struct rogue_meta_ldr_block_hdr *ldr_header =
262		(struct rogue_meta_ldr_block_hdr *)fw;
263	struct rogue_meta_ldr_l1_data_blk *l1_data =
264		(struct rogue_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
265	const u32 fw_size = pvr_dev->fw_dev.firmware->size;
266	int err;
267
268	u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
269	u32 coremem_size;
270
271	err = PVR_FEATURE_VALUE(pvr_dev, meta_coremem_size, &coremem_size);
272	if (err)
273		return err;
274
275	coremem_size *= SZ_1K;
276
277	while (l1_data) {
278		/* Verify block header is within bounds. */
279		if (((u8 *)l1_data - fw) >= fw_size || ((u8 *)(l1_data + 1) - fw) >= fw_size)
280			return -EINVAL;
281
282		if (ROGUE_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
283			/* Don't process comment blocks */
284			goto next_block;
285		}
286
287		switch (l1_data->cmd & ROGUE_META_LDR_CMD_MASK)
288		case ROGUE_META_LDR_CMD_LOADMEM: {
289			err = meta_ldr_cmd_loadmem(drm_dev, fw, l1_data,
290						   coremem_size,
291						   fw_code_ptr, fw_data_ptr,
292						   fw_core_code_ptr,
293						   fw_core_data_ptr, fw_size);
294			if (err)
295				return err;
296			break;
297
298		case ROGUE_META_LDR_CMD_START_THREADS:
299			/* Don't process this block */
300			break;
301
302		case ROGUE_META_LDR_CMD_ZEROMEM:
303			err = meta_ldr_cmd_zeromem(drm_dev, l1_data,
304						   coremem_size,
305						   fw_code_ptr, fw_data_ptr,
306						   fw_core_code_ptr,
307						   fw_core_data_ptr);
308			if (err)
309				return err;
310			break;
311
312		case ROGUE_META_LDR_CMD_CONFIG:
313			err = meta_ldr_cmd_config(drm_dev, fw, l1_data, fw_size,
314						  &boot_conf);
315			if (err)
316				return err;
317			break;
318
319		default:
320			return -EINVAL;
321		}
322
323next_block:
324		if (l1_data->next == 0xFFFFFFFF)
325			break;
326
327		l1_data = (struct rogue_meta_ldr_l1_data_blk *)(fw +
328								l1_data->next);
329	}
330
331	if (boot_conf_ptr)
332		*boot_conf_ptr = boot_conf;
333
334	return 0;
335}
336
337static void
338configure_seg_id(u64 seg_out_addr, u32 seg_base, u32 seg_limit, u32 seg_id,
339		 u32 **boot_conf_ptr)
340{
341	u32 seg_out_addr0 = seg_out_addr & 0x00000000FFFFFFFFUL;
342	u32 seg_out_addr1 = (seg_out_addr >> 32) & 0x00000000FFFFFFFFUL;
343	u32 *boot_conf = *boot_conf_ptr;
344
345	/* META segments have a minimum size. */
346	u32 limit_off = max(seg_limit, ROGUE_FW_SEGMMU_ALIGN);
347
348	/* The limit is an offset, therefore off = size - 1. */
349	limit_off -= 1;
350
351	seg_base |= ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE;
352
353	add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_BASE(seg_id), seg_base);
354	add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_LIMIT(seg_id), limit_off);
355	add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA0(seg_id), seg_out_addr0);
356	add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA1(seg_id), seg_out_addr1);
357
358	*boot_conf_ptr = boot_conf;
359}
360
361static u64 get_fw_obj_gpu_addr(struct pvr_fw_object *fw_obj)
362{
363	struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev);
364	struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
365
366	return fw_obj->fw_addr_offset + fw_dev->fw_heap_info.gpu_addr;
367}
368
369static void
370configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr)
371{
372	const struct pvr_fw_layout_entry *layout_entries = pvr_dev->fw_dev.layout_entries;
373	u32 num_layout_entries = pvr_dev->fw_dev.header->layout_entry_num;
374	u64 seg_out_addr_top;
375
376	seg_out_addr_top =
377		ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
378						ROGUE_FW_SEGMMU_META_BIFDM_ID);
379
380	for (u32 i = 0; i < num_layout_entries; i++) {
381		/*
382		 * FW code is using the bootloader segment which is already
383		 * configured on boot. FW coremem code and data don't use the
384		 * segment MMU. Only the FW data segment needs to be configured.
385		 */
386		if (layout_entries[i].type == FW_DATA) {
387			u32 seg_id = ROGUE_FW_SEGMMU_DATA_ID;
388			u64 seg_out_addr = get_fw_obj_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
389
390			seg_out_addr += layout_entries[i].alloc_offset;
391			seg_out_addr |= seg_out_addr_top;
392
393			/* Write the sequence to the bootldr. */
394			configure_seg_id(seg_out_addr,
395					 layout_entries[i].base_addr,
396					 layout_entries[i].alloc_size, seg_id,
397					 boot_conf_ptr);
398
399			break;
400		}
401	}
402}
403
404static void
405configure_meta_caches(u32 **boot_conf_ptr)
406{
407	u32 *boot_conf = *boot_conf_ptr;
408	u32 d_cache_t0, i_cache_t0;
409	u32 d_cache_t1, i_cache_t1;
410	u32 d_cache_t2, i_cache_t2;
411	u32 d_cache_t3, i_cache_t3;
412
413	/* Initialise I/Dcache settings */
414	d_cache_t0 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
415	d_cache_t1 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
416	d_cache_t2 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
417	d_cache_t3 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
418	i_cache_t0 = 0;
419	i_cache_t1 = 0;
420	i_cache_t2 = 0;
421	i_cache_t3 = 0;
422
423	d_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
424	i_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
425
426	/* Local region MMU enhanced bypass: WIN-3 mode for code and data caches */
427	add_boot_arg(&boot_conf, META_CR_MMCU_LOCAL_EBCTRL,
428		     META_CR_MMCU_LOCAL_EBCTRL_ICWIN |
429			     META_CR_MMCU_LOCAL_EBCTRL_DCWIN);
430
431	/* Data cache partitioning thread 0 to 3 */
432	add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(0), d_cache_t0);
433	add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(1), d_cache_t1);
434	add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(2), d_cache_t2);
435	add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(3), d_cache_t3);
436
437	/* Enable data cache hits */
438	add_boot_arg(&boot_conf, META_CR_MMCU_DCACHE_CTRL,
439		     META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
440
441	/* Instruction cache partitioning thread 0 to 3 */
442	add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(0), i_cache_t0);
443	add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(1), i_cache_t1);
444	add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(2), i_cache_t2);
445	add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(3), i_cache_t3);
446
447	/* Enable instruction cache hits */
448	add_boot_arg(&boot_conf, META_CR_MMCU_ICACHE_CTRL,
449		     META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
450
451	add_boot_arg(&boot_conf, 0x040000C0, 0);
452
453	*boot_conf_ptr = boot_conf;
454}
455
456static int
457pvr_meta_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
458		    u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
459		    u32 core_code_alloc_size)
460{
461	struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
462	u32 *boot_conf;
463	int err;
464
465	boot_conf = ((u32 *)fw_code_ptr) + ROGUE_FW_BOOTLDR_CONF_OFFSET;
466
467	/* Slave port and JTAG accesses are privileged. */
468	add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD,
469		     META_CR_SYSC_JTAG_THREAD_PRIV_EN);
470
471	configure_seg_mmu(pvr_dev, &boot_conf);
472
473	/* Populate FW sections from LDR image. */
474	err = process_ldr_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, fw_core_code_ptr,
475					 fw_core_data_ptr, &boot_conf);
476	if (err)
477		return err;
478
479	configure_meta_caches(&boot_conf);
480
481	/* End argument list. */
482	add_boot_arg(&boot_conf, 0, 0);
483
484	if (fw_dev->mem.core_code_obj) {
485		u32 core_code_fw_addr;
486
487		pvr_fw_object_get_fw_addr(fw_dev->mem.core_code_obj, &core_code_fw_addr);
488		add_boot_arg(&boot_conf, core_code_fw_addr, core_code_alloc_size);
489	} else {
490		add_boot_arg(&boot_conf, 0, 0);
491	}
492	/* None of the cores supported by this driver have META DMA. */
493	add_boot_arg(&boot_conf, 0, 0);
494
495	return 0;
496}
497
498static int
499pvr_meta_init(struct pvr_device *pvr_dev)
500{
501	pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_META_SHIFT, 0);
502
503	return 0;
504}
505
506static u32
507pvr_meta_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
508{
509	u32 fw_addr = fw_obj->fw_addr_offset + offset + ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS;
510
511	/* META cacheability is determined by address. */
512	if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
513		fw_addr |= ROGUE_FW_SEGMMU_DATA_META_UNCACHED |
514			   ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
515
516	return fw_addr;
517}
518
519static int
520pvr_meta_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
521{
522	struct pvr_gem_object *pvr_obj = fw_obj->gem;
523
524	return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.start,
525			  pvr_gem_object_size(pvr_obj));
526}
527
528static void
529pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
530{
531	struct pvr_gem_object *pvr_obj = fw_obj->gem;
532
533	pvr_vm_unmap_obj(pvr_dev->kernel_vm_ctx, pvr_obj,
534			 fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size);
535}
536
537static bool
538pvr_meta_irq_pending(struct pvr_device *pvr_dev)
539{
540	return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) &
541	       ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN;
542}
543
544static void
545pvr_meta_irq_clear(struct pvr_device *pvr_dev)
546{
547	pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS,
548		       ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK);
549}
550
551const struct pvr_fw_defs pvr_fw_defs_meta = {
552	.init = pvr_meta_init,
553	.fw_process = pvr_meta_fw_process,
554	.vm_map = pvr_meta_vm_map,
555	.vm_unmap = pvr_meta_vm_unmap,
556	.get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset,
557	.wrapper_init = pvr_meta_wrapper_init,
558	.irq_pending = pvr_meta_irq_pending,
559	.irq_clear = pvr_meta_irq_clear,
560	.has_fixed_data_addr = false,
561};