intel_uncore.h

  1/*
  2 * Copyright © 2017 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 */
 24
 25#ifndef __INTEL_UNCORE_H__
 26#define __INTEL_UNCORE_H__
 27
 28#include <linux/spinlock.h>
 29#include <linux/notifier.h>
 30#include <linux/hrtimer.h>
 31#include <linux/io-64-nonatomic-lo-hi.h>
 32#include <linux/types.h>
 33
 34#include "i915_reg_defs.h"
 35
 36struct drm_device;
 37struct drm_i915_private;
 38struct intel_runtime_pm;
 39struct intel_uncore;
 40struct intel_gt;
 41
 42struct intel_uncore_mmio_debug {
 43	spinlock_t lock; /** lock is also taken in irq contexts. */
 44	int unclaimed_mmio_check;
 45	int saved_mmio_check;
 46	u32 suspend_count;
 47};
 48
 49enum forcewake_domain_id {
 50	FW_DOMAIN_ID_RENDER = 0,
 51	FW_DOMAIN_ID_GT,        /* also includes blitter engine */
 52	FW_DOMAIN_ID_MEDIA,
 53	FW_DOMAIN_ID_MEDIA_VDBOX0,
 54	FW_DOMAIN_ID_MEDIA_VDBOX1,
 55	FW_DOMAIN_ID_MEDIA_VDBOX2,
 56	FW_DOMAIN_ID_MEDIA_VDBOX3,
 57	FW_DOMAIN_ID_MEDIA_VDBOX4,
 58	FW_DOMAIN_ID_MEDIA_VDBOX5,
 59	FW_DOMAIN_ID_MEDIA_VDBOX6,
 60	FW_DOMAIN_ID_MEDIA_VDBOX7,
 61	FW_DOMAIN_ID_MEDIA_VEBOX0,
 62	FW_DOMAIN_ID_MEDIA_VEBOX1,
 63	FW_DOMAIN_ID_MEDIA_VEBOX2,
 64	FW_DOMAIN_ID_MEDIA_VEBOX3,
 65	FW_DOMAIN_ID_GSC,
 66
 67	FW_DOMAIN_ID_COUNT
 68};
 69
 70enum forcewake_domains {
 71	FORCEWAKE_RENDER	= BIT(FW_DOMAIN_ID_RENDER),
 72	FORCEWAKE_GT		= BIT(FW_DOMAIN_ID_GT),
 73	FORCEWAKE_MEDIA		= BIT(FW_DOMAIN_ID_MEDIA),
 74	FORCEWAKE_MEDIA_VDBOX0	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
 75	FORCEWAKE_MEDIA_VDBOX1	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
 76	FORCEWAKE_MEDIA_VDBOX2	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
 77	FORCEWAKE_MEDIA_VDBOX3	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
 78	FORCEWAKE_MEDIA_VDBOX4	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX4),
 79	FORCEWAKE_MEDIA_VDBOX5	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX5),
 80	FORCEWAKE_MEDIA_VDBOX6	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX6),
 81	FORCEWAKE_MEDIA_VDBOX7	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX7),
 82	FORCEWAKE_MEDIA_VEBOX0	= BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
 83	FORCEWAKE_MEDIA_VEBOX1	= BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
 84	FORCEWAKE_MEDIA_VEBOX2	= BIT(FW_DOMAIN_ID_MEDIA_VEBOX2),
 85	FORCEWAKE_MEDIA_VEBOX3	= BIT(FW_DOMAIN_ID_MEDIA_VEBOX3),
 86	FORCEWAKE_GSC		= BIT(FW_DOMAIN_ID_GSC),
 87
 88	FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
 89};
 90
 91struct intel_uncore_fw_get {
 92	void (*force_wake_get)(struct intel_uncore *uncore,
 93			       enum forcewake_domains domains);
 94};
 95
 96struct intel_uncore_funcs {
 97	enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
 98						  i915_reg_t r);
 99	enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
100						   i915_reg_t r);
101
102	u8 (*mmio_readb)(struct intel_uncore *uncore,
103			 i915_reg_t r, bool trace);
104	u16 (*mmio_readw)(struct intel_uncore *uncore,
105			  i915_reg_t r, bool trace);
106	u32 (*mmio_readl)(struct intel_uncore *uncore,
107			  i915_reg_t r, bool trace);
108	u64 (*mmio_readq)(struct intel_uncore *uncore,
109			  i915_reg_t r, bool trace);
110
111	void (*mmio_writeb)(struct intel_uncore *uncore,
112			    i915_reg_t r, u8 val, bool trace);
113	void (*mmio_writew)(struct intel_uncore *uncore,
114			    i915_reg_t r, u16 val, bool trace);
115	void (*mmio_writel)(struct intel_uncore *uncore,
116			    i915_reg_t r, u32 val, bool trace);
117};
118
119struct intel_forcewake_range {
120	u32 start;
121	u32 end;
122
123	enum forcewake_domains domains;
124};
125
126struct intel_uncore {
127	void __iomem *regs;
128
129	struct drm_i915_private *i915;
130	struct intel_gt *gt;
131	struct intel_runtime_pm *rpm;
132
133	spinlock_t lock; /** lock is also taken in irq contexts. */
134
135	/*
136	 * Do we need to apply an additional offset to reach the beginning
137	 * of the basic non-engine GT registers (referred to as "GSI" on
138	 * newer platforms, or "GT block" on older platforms)?  If so, we'll
139	 * track that here and apply it transparently to registers in the
140	 * appropriate range to maintain compatibility with our existing
141	 * register definitions and GT code.
142	 */
143	u32 gsi_offset;
144
145	unsigned int flags;
146#define UNCORE_HAS_FORCEWAKE		BIT(0)
147#define UNCORE_HAS_FPGA_DBG_UNCLAIMED	BIT(1)
148#define UNCORE_HAS_DBG_UNCLAIMED	BIT(2)
149#define UNCORE_HAS_FIFO			BIT(3)
150#define UNCORE_NEEDS_FLR_ON_FINI	BIT(4)
151
152	const struct intel_forcewake_range *fw_domains_table;
153	unsigned int fw_domains_table_entries;
154
155	/*
156	 * Shadowed registers are special cases where we can safely write
157	 * to the register *without* grabbing forcewake.
158	 */
159	const struct i915_mmio_range *shadowed_reg_table;
160	unsigned int shadowed_reg_table_entries;
161
162	struct notifier_block pmic_bus_access_nb;
163	const struct intel_uncore_fw_get *fw_get_funcs;
164	struct intel_uncore_funcs funcs;
165
166	unsigned int fifo_count;
167
168	enum forcewake_domains fw_domains;
169	enum forcewake_domains fw_domains_active;
170	enum forcewake_domains fw_domains_timer;
171	enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
172
173	struct intel_uncore_forcewake_domain {
174		struct intel_uncore *uncore;
175		enum forcewake_domain_id id;
176		enum forcewake_domains mask;
177		unsigned int wake_count;
178		bool active;
179		struct hrtimer timer;
180		u32 __iomem *reg_set;
181		u32 __iomem *reg_ack;
182	} *fw_domain[FW_DOMAIN_ID_COUNT];
183
184	unsigned int user_forcewake_count;
185
186	struct intel_uncore_mmio_debug *debug;
187};
188
189/* Iterate over initialised fw domains */
190#define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
191	for (tmp__ = (mask__); tmp__ ;) \
192		for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
193
194#define for_each_fw_domain(domain__, uncore__, tmp__) \
195	for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
196
197static inline bool
198intel_uncore_has_forcewake(const struct intel_uncore *uncore)
199{
200	return uncore->flags & UNCORE_HAS_FORCEWAKE;
201}
202
203static inline bool
204intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
205{
206	return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
207}
208
209static inline bool
210intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
211{
212	return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
213}
214
215static inline bool
216intel_uncore_has_fifo(const struct intel_uncore *uncore)
217{
218	return uncore->flags & UNCORE_HAS_FIFO;
219}
220
221static inline bool
222intel_uncore_needs_flr_on_fini(const struct intel_uncore *uncore)
223{
224	return uncore->flags & UNCORE_NEEDS_FLR_ON_FINI;
225}
226
227static inline bool
228intel_uncore_set_flr_on_fini(struct intel_uncore *uncore)
229{
230	return uncore->flags |= UNCORE_NEEDS_FLR_ON_FINI;
231}
232
233void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
234void intel_uncore_init_early(struct intel_uncore *uncore,
235			     struct intel_gt *gt);
236int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
237int intel_uncore_init_mmio(struct intel_uncore *uncore);
238void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
239					  struct intel_gt *gt);
240bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
241bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
242void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
243void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
244void intel_uncore_suspend(struct intel_uncore *uncore);
245void intel_uncore_resume_early(struct intel_uncore *uncore);
246void intel_uncore_runtime_resume(struct intel_uncore *uncore);
247
248void assert_forcewakes_inactive(struct intel_uncore *uncore);
249void assert_forcewakes_active(struct intel_uncore *uncore,
250			      enum forcewake_domains fw_domains);
251const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
252
253enum forcewake_domains
254intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
255			       i915_reg_t reg, unsigned int op);
256#define FW_REG_READ  (1)
257#define FW_REG_WRITE (2)
258
259void intel_uncore_forcewake_get(struct intel_uncore *uncore,
260				enum forcewake_domains domains);
261void intel_uncore_forcewake_put(struct intel_uncore *uncore,
262				enum forcewake_domains domains);
263void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
264					enum forcewake_domains domains);
265void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
266				  enum forcewake_domains fw_domains);
267
268/*
269 * Like above but the caller must manage the uncore.lock itself.
270 * Must be used with intel_uncore_read_fw() and friends.
271 */
272void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
273					enum forcewake_domains domains);
274void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
275					enum forcewake_domains domains);
276
277void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
278void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
279
280int __intel_wait_for_register(struct intel_uncore *uncore,
281			      i915_reg_t reg,
282			      u32 mask,
283			      u32 value,
284			      unsigned int fast_timeout_us,
285			      unsigned int slow_timeout_ms,
286			      u32 *out_value);
287static inline int
288intel_wait_for_register(struct intel_uncore *uncore,
289			i915_reg_t reg,
290			u32 mask,
291			u32 value,
292			unsigned int timeout_ms)
293{
294	return __intel_wait_for_register(uncore, reg, mask, value, 2,
295					 timeout_ms, NULL);
296}
297
298int __intel_wait_for_register_fw(struct intel_uncore *uncore,
299				 i915_reg_t reg,
300				 u32 mask,
301				 u32 value,
302				 unsigned int fast_timeout_us,
303				 unsigned int slow_timeout_ms,
304				 u32 *out_value);
305static inline int
306intel_wait_for_register_fw(struct intel_uncore *uncore,
307			   i915_reg_t reg,
308			   u32 mask,
309			   u32 value,
310			   unsigned int timeout_ms,
311			   u32 *out_value)
312{
313	return __intel_wait_for_register_fw(uncore, reg, mask, value,
314					    2, timeout_ms, out_value);
315}
316
317#define IS_GSI_REG(reg) ((reg) < 0x40000)
318
319/* register access functions */
320#define __raw_read(x__, s__) \
321static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
322					    i915_reg_t reg) \
323{ \
324	u32 offset = i915_mmio_reg_offset(reg); \
325	if (IS_GSI_REG(offset)) \
326		offset += uncore->gsi_offset; \
327	return read##s__(uncore->regs + offset); \
328}
329
330#define __raw_write(x__, s__) \
331static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
332					   i915_reg_t reg, u##x__ val) \
333{ \
334	u32 offset = i915_mmio_reg_offset(reg); \
335	if (IS_GSI_REG(offset)) \
336		offset += uncore->gsi_offset; \
337	write##s__(val, uncore->regs + offset); \
338}
339__raw_read(8, b)
340__raw_read(16, w)
341__raw_read(32, l)
342__raw_read(64, q)
343
344__raw_write(8, b)
345__raw_write(16, w)
346__raw_write(32, l)
347__raw_write(64, q)
348
349#undef __raw_read
350#undef __raw_write
351
352#define __uncore_read(name__, x__, s__, trace__) \
353static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
354					   i915_reg_t reg) \
355{ \
356	return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
357}
358
359#define __uncore_write(name__, x__, s__, trace__) \
360static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
361					 i915_reg_t reg, u##x__ val) \
362{ \
363	uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
364}
365
366__uncore_read(read8, 8, b, true)
367__uncore_read(read16, 16, w, true)
368__uncore_read(read, 32, l, true)
369__uncore_read(read16_notrace, 16, w, false)
370__uncore_read(read_notrace, 32, l, false)
371
372__uncore_write(write8, 8, b, true)
373__uncore_write(write16, 16, w, true)
374__uncore_write(write, 32, l, true)
375__uncore_write(write_notrace, 32, l, false)
376
377/* Be very careful with read/write 64-bit values. On 32-bit machines, they
378 * will be implemented using 2 32-bit writes in an arbitrary order with
379 * an arbitrary delay between them. This can cause the hardware to
380 * act upon the intermediate value, possibly leading to corruption and
381 * machine death. For this reason we do not support intel_uncore_write64,
382 * or uncore->funcs.mmio_writeq.
383 *
384 * When reading a 64-bit value as two 32-bit values, the delay may cause
385 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
386 * occasionally a 64-bit register does not actually support a full readq
387 * and must be read using two 32-bit reads.
388 *
389 * You have been warned.
390 */
391__uncore_read(read64, 64, q, true)
392
393#define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
394#define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
395
396#undef __uncore_read
397#undef __uncore_write
398
399/* These are untraced mmio-accessors that are only valid to be used inside
400 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
401 * controlled.
402 *
403 * Think twice, and think again, before using these.
404 *
405 * As an example, these accessors can possibly be used between:
406 *
407 * spin_lock_irq(&uncore->lock);
408 * intel_uncore_forcewake_get__locked();
409 *
410 * and
411 *
412 * intel_uncore_forcewake_put__locked();
413 * spin_unlock_irq(&uncore->lock);
414 *
415 *
416 * Note: some registers may not need forcewake held, so
417 * intel_uncore_forcewake_{get,put} can be omitted, see
418 * intel_uncore_forcewake_for_reg().
419 *
420 * Certain architectures will die if the same cacheline is concurrently accessed
421 * by different clients (e.g. on Ivybridge). Access to registers should
422 * therefore generally be serialised, by either the dev_priv->uncore.lock or
423 * a more localised lock guarding all access to that bank of registers.
424 */
425#define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
426#define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
427#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
428#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
429
430static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
431				   i915_reg_t reg, u32 clear, u32 set)
432{
433	u32 old, val;
434
435	old = intel_uncore_read(uncore, reg);
436	val = (old & ~clear) | set;
437	intel_uncore_write(uncore, reg, val);
438	return old;
439}
440
441static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
442				       i915_reg_t reg, u32 clear, u32 set)
443{
444	u32 old, val;
445
446	old = intel_uncore_read_fw(uncore, reg);
447	val = (old & ~clear) | set;
448	if (val != old)
449		intel_uncore_write_fw(uncore, reg, val);
450}
451
452static inline u64
453intel_uncore_read64_2x32(struct intel_uncore *uncore,
454			 i915_reg_t lower_reg, i915_reg_t upper_reg)
455{
456	u32 upper, lower, old_upper, loop = 0;
457	enum forcewake_domains fw_domains;
458	unsigned long flags;
459
460	fw_domains = intel_uncore_forcewake_for_reg(uncore, lower_reg,
461						    FW_REG_READ);
462
463	fw_domains |= intel_uncore_forcewake_for_reg(uncore, upper_reg,
464						    FW_REG_READ);
465
466	spin_lock_irqsave(&uncore->lock, flags);
467	intel_uncore_forcewake_get__locked(uncore, fw_domains);
468
469	upper = intel_uncore_read_fw(uncore, upper_reg);
470	do {
471		old_upper = upper;
472		lower = intel_uncore_read_fw(uncore, lower_reg);
473		upper = intel_uncore_read_fw(uncore, upper_reg);
474	} while (upper != old_upper && loop++ < 2);
475
476	intel_uncore_forcewake_put__locked(uncore, fw_domains);
477	spin_unlock_irqrestore(&uncore->lock, flags);
478
479	return (u64)upper << 32 | lower;
480}
481
482static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
483						i915_reg_t reg, u32 val,
484						u32 mask, u32 expected_val)
485{
486	u32 reg_val;
487
488	intel_uncore_write(uncore, reg, val);
489	reg_val = intel_uncore_read(uncore, reg);
490
491	return (reg_val & mask) != expected_val ? -EINVAL : 0;
492}
493
494static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)
495{
496	return uncore->regs;
497}
498
499struct intel_uncore *to_intel_uncore(struct drm_device *drm);
500
501/*
502 * The raw_reg_{read,write} macros are intended as a micro-optimization for
503 * interrupt handlers so that the pointer indirection on uncore->regs can
504 * be computed once (and presumably cached in a register) instead of generating
505 * extra load instructions for each MMIO access.
506 *
507 * Given that these macros are only intended for non-GSI interrupt registers
508 * (and the goal is to avoid extra instructions generated by the compiler),
509 * these macros do not account for uncore->gsi_offset.  Any caller that needs
510 * to use these macros on a GSI register is responsible for adding the
511 * appropriate GSI offset to the 'base' parameter.
512 */
513#define raw_reg_read(base, reg) \
514	readl(base + i915_mmio_reg_offset(reg))
515#define raw_reg_write(base, reg, value) \
516	writel(value, base + i915_mmio_reg_offset(reg))
517
518#endif /* !__INTEL_UNCORE_H__ */