i915_gpu_error.h

  1/*
  2 * SPDX-License-Identifier: MIT
  3 *
  4 * Copyright © 2008-2018 Intel Corporation
  5 */
  6
  7#ifndef _I915_GPU_ERROR_H_
  8#define _I915_GPU_ERROR_H_
  9
 10#include <linux/atomic.h>
 11#include <linux/kref.h>
 12#include <linux/ktime.h>
 13#include <linux/sched.h>
 14
 15#include <drm/drm_mm.h>
 16
 17#include "gt/intel_engine.h"
 18#include "gt/intel_engine_types.h"
 19#include "gt/intel_gt_types.h"
 20#include "gt/uc/intel_uc_fw.h"
 21
 22#include "intel_device_info.h"
 23
 24#include "i915_gem.h"
 25#include "i915_gem_gtt.h"
 26#include "i915_params.h"
 27#include "i915_scheduler.h"
 28
 29struct drm_i915_private;
 30struct i915_vma_compress;
 31struct intel_engine_capture_vma;
 32struct intel_display_snapshot;
 33
 34struct i915_vma_coredump {
 35	struct i915_vma_coredump *next;
 36
 37	char name[20];
 38
 39	u64 gtt_offset;
 40	u64 gtt_size;
 41	u32 gtt_page_sizes;
 42
 43	int unused;
 44	struct list_head page_list;
 45};
 46
 47struct i915_request_coredump {
 48	unsigned long flags;
 49	pid_t pid;
 50	u32 context;
 51	u32 seqno;
 52	u32 head;
 53	u32 tail;
 54	struct i915_sched_attr sched_attr;
 55};
 56
 57struct __guc_capture_parsed_output;
 58
 59struct intel_engine_coredump {
 60	const struct intel_engine_cs *engine;
 61
 62	bool hung;
 63	bool simulated;
 64	u32 reset_count;
 65
 66	/* position of active request inside the ring */
 67	u32 rq_head, rq_post, rq_tail;
 68
 69	/* Register state */
 70	u32 ccid;
 71	u32 start;
 72	u32 tail;
 73	u32 head;
 74	u32 ctl;
 75	u32 mode;
 76	u32 hws;
 77	u32 ipeir;
 78	u32 ipehr;
 79	u32 esr;
 80	u32 bbstate;
 81	u32 instpm;
 82	u32 instps;
 83	u64 bbaddr;
 84	u64 acthd;
 85	u32 fault_reg;
 86	u64 faddr;
 87	u32 rc_psmi; /* sleep state */
 88	u32 nopid;
 89	u32 excc;
 90	u32 cmd_cctl;
 91	u32 cscmdop;
 92	u32 ctx_sr_ctl;
 93	u32 dma_faddr_hi;
 94	u32 dma_faddr_lo;
 95	struct intel_instdone instdone;
 96
 97	/* GuC matched capture-lists info */
 98	struct intel_guc_state_capture *guc_capture;
 99	struct __guc_capture_parsed_output *guc_capture_node;
100
101	struct i915_gem_context_coredump {
102		char comm[TASK_COMM_LEN];
103
104		u64 total_runtime;
105		u64 avg_runtime;
106
107		pid_t pid;
108		int active;
109		int guilty;
110		struct i915_sched_attr sched_attr;
111		u32 hwsp_seqno;
112	} context;
113
114	struct i915_vma_coredump *vma;
115
116	struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
117	unsigned int num_ports;
118
119	struct {
120		u32 gfx_mode;
121		union {
122			u64 pdp[4];
123			u32 pp_dir_base;
124		};
125	} vm_info;
126
127	struct intel_engine_coredump *next;
128};
129
130struct intel_ctb_coredump {
131	u32 raw_head, head;
132	u32 raw_tail, tail;
133	u32 raw_status;
134	u32 desc_offset;
135	u32 cmds_offset;
136	u32 size;
137};
138
139struct intel_gt_coredump {
140	const struct intel_gt *_gt;
141	bool awake;
142	bool simulated;
143
144	struct intel_gt_info info;
145
146	/* Generic register state */
147	u32 eir;
148	u32 pgtbl_er;
149	u32 gtier[6], ngtier;
150	u32 forcewake;
151	u32 error; /* gen6+ */
152	u32 err_int; /* gen7 */
153	u32 fault_data0; /* gen8, gen9 */
154	u32 fault_data1; /* gen8, gen9 */
155	u32 done_reg;
156	u32 gac_eco;
157	u32 gam_ecochk;
158	u32 gab_ctl;
159	u32 gfx_mode;
160	u32 gtt_cache;
161	u32 aux_err; /* gen12 */
162	u32 gam_done; /* gen12 */
163	u32 clock_frequency;
164	u32 clock_period_ns;
165
166	u32 sfc_done[I915_MAX_SFC]; /* gen12 */
167
168	u32 nfence;
169	u64 fence[I915_MAX_NUM_FENCES];
170
171	struct intel_engine_coredump *engine;
172
173	struct intel_uc_coredump {
174		struct intel_uc_fw guc_fw;
175		struct intel_uc_fw huc_fw;
176		struct guc_info {
177			struct intel_ctb_coredump ctb[2];
178			struct i915_vma_coredump *vma_ctb;
179			struct i915_vma_coredump *vma_log;
180			u32 *hw_state;
181			u32 timestamp;
182			u16 last_fence;
183			bool is_guc_capture;
184		} guc;
185	} *uc;
186
187	struct intel_gt_coredump *next;
188};
189
190struct i915_gpu_coredump {
191	struct kref ref;
192	ktime_t time;
193	ktime_t boottime;
194	ktime_t uptime;
195	unsigned long capture;
196
197	struct drm_i915_private *i915;
198
199	struct intel_gt_coredump *gt;
200
201	char error_msg[128];
202	bool simulated;
203	bool wakelock;
204	bool suspended;
205	int iommu;
206	u32 reset_count;
207	u32 suspend_count;
208
209	struct intel_device_info device_info;
210	struct intel_runtime_info runtime_info;
211	struct intel_driver_caps driver_caps;
212	struct i915_params params;
213
214	struct scatterlist *sgl, *fit;
215
216	struct intel_display_snapshot *display_snapshot;
217};
218
219struct i915_gpu_error {
220	/* For reset and error_state handling. */
221	spinlock_t lock;
222	/* Protected by the above dev->gpu_error.lock. */
223	struct i915_gpu_coredump *first_error;
224
225	/** Number of times the device has been reset (global) */
226	atomic_t reset_count;
227
228	/** Number of times an engine has been reset */
229	atomic_t reset_engine_count[MAX_ENGINE_CLASS];
230};
231
232struct drm_i915_error_state_buf {
233	struct drm_i915_private *i915;
234	struct scatterlist *sgl, *cur, *end;
235
236	char *buf;
237	size_t bytes;
238	size_t size;
239	loff_t iter;
240
241	int err;
242};
243
244static inline u32 i915_reset_count(struct i915_gpu_error *error)
245{
246	return atomic_read(&error->reset_count);
247}
248
249static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
250					  const struct intel_engine_cs *engine)
251{
252	return atomic_read(&error->reset_engine_count[engine->class]);
253}
254
255static inline void
256i915_increase_reset_engine_count(struct i915_gpu_error *error,
257				 const struct intel_engine_cs *engine)
258{
259	atomic_inc(&error->reset_engine_count[engine->class]);
260}
261
262#define CORE_DUMP_FLAG_NONE           0x0
263#define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
264
265#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
266void intel_klog_error_capture(struct intel_gt *gt,
267			      intel_engine_mask_t engine_mask);
268#else
269static inline void intel_klog_error_capture(struct intel_gt *gt,
270					    intel_engine_mask_t engine_mask)
271{
272}
273#endif
274
275#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
276
277__printf(2, 3)
278void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
279
280void i915_capture_error_state(struct intel_gt *gt,
281			      intel_engine_mask_t engine_mask, u32 dump_flags);
282
283struct i915_gpu_coredump *
284i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
285
286struct intel_gt_coredump *
287intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags);
288
289struct intel_engine_coredump *
290intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);
291
292struct intel_engine_capture_vma *
293intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
294				  struct i915_request *rq,
295				  gfp_t gfp);
296
297void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
298				   struct intel_engine_capture_vma *capture,
299				   struct i915_vma_compress *compress);
300
301struct i915_vma_compress *
302i915_vma_capture_prepare(struct intel_gt_coredump *gt);
303
304void i915_vma_capture_finish(struct intel_gt_coredump *gt,
305			     struct i915_vma_compress *compress);
306
307void i915_error_state_store(struct i915_gpu_coredump *error);
308
309static inline struct i915_gpu_coredump *
310i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
311{
312	kref_get(&gpu->ref);
313	return gpu;
314}
315
316ssize_t
317i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
318				 char *buf, loff_t offset, size_t count);
319
320void __i915_gpu_coredump_free(struct kref *kref);
321static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
322{
323	if (gpu)
324		kref_put(&gpu->ref, __i915_gpu_coredump_free);
325}
326
327void i915_reset_error_state(struct drm_i915_private *i915);
328void i915_disable_error_state(struct drm_i915_private *i915, int err);
329
330void i915_gpu_error_debugfs_register(struct drm_i915_private *i915);
331void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915);
332void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915);
333
334#else
335
336__printf(2, 3)
337static inline void
338i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
339{
340}
341
342static inline void
343i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
344{
345}
346
347static inline struct i915_gpu_coredump *
348i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
349{
350	return NULL;
351}
352
353static inline struct intel_gt_coredump *
354intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
355{
356	return NULL;
357}
358
359static inline struct intel_engine_coredump *
360intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
361{
362	return NULL;
363}
364
365static inline struct intel_engine_capture_vma *
366intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
367				  struct i915_request *rq,
368				  gfp_t gfp)
369{
370	return NULL;
371}
372
373static inline void
374intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
375			      struct intel_engine_capture_vma *capture,
376			      struct i915_vma_compress *compress)
377{
378}
379
380static inline struct i915_vma_compress *
381i915_vma_capture_prepare(struct intel_gt_coredump *gt)
382{
383	return NULL;
384}
385
386static inline void
387i915_vma_capture_finish(struct intel_gt_coredump *gt,
388			struct i915_vma_compress *compress)
389{
390}
391
392static inline void
393i915_error_state_store(struct i915_gpu_coredump *error)
394{
395}
396
397static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
398{
399}
400
401static inline void i915_reset_error_state(struct drm_i915_private *i915)
402{
403}
404
405static inline void i915_disable_error_state(struct drm_i915_private *i915,
406					    int err)
407{
408}
409
410static inline void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)
411{
412}
413
414static inline void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)
415{
416}
417
418static inline void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)
419{
420}
421
422#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
423
424#endif /* _I915_GPU_ERROR_H_ */