i915_debugfs.c

  1/*
  2 * Copyright © 2008 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Eric Anholt <eric@anholt.net>
 25 *    Keith Packard <keithp@keithp.com>
 26 *
 27 */
 28
 29#include <linux/debugfs.h>
 30#include <linux/sched/mm.h>
 31#include <linux/sort.h>
 32#include <linux/string_helpers.h>
 33
 34#include <drm/drm_debugfs.h>
 35#include <drm/drm_print.h>
 36
 37#include "gem/i915_gem_context.h"
 38#include "gt/intel_gt.h"
 39#include "gt/intel_gt_buffer_pool.h"
 40#include "gt/intel_gt_clock_utils.h"
 41#include "gt/intel_gt_debugfs.h"
 42#include "gt/intel_gt_pm.h"
 43#include "gt/intel_gt_pm_debugfs.h"
 44#include "gt/intel_gt_regs.h"
 45#include "gt/intel_gt_requests.h"
 46#include "gt/intel_rc6.h"
 47#include "gt/intel_reset.h"
 48#include "gt/intel_rps.h"
 49#include "gt/intel_sseu_debugfs.h"
 50
 51#include "i915_debugfs.h"
 52#include "i915_debugfs_params.h"
 53#include "i915_driver.h"
 54#include "i915_gpu_error.h"
 55#include "i915_irq.h"
 56#include "i915_reg.h"
 57#include "i915_scheduler.h"
 58#include "i915_wait_util.h"
 59#include "intel_mchbar_regs.h"
 60
 61static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
 62{
 63	return to_i915(node->minor->dev);
 64}
 65
 66static int i915_capabilities(struct seq_file *m, void *data)
 67{
 68	struct drm_i915_private *i915 = node_to_i915(m->private);
 69	struct drm_printer p = drm_seq_file_printer(m);
 70
 71	intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);
 72	i915_print_iommu_status(i915, &p);
 73	intel_gt_info_print(&to_gt(i915)->info, &p);
 74	intel_driver_caps_print(&i915->caps, &p);
 75
 76	i915_params_dump(&i915->params, &p);
 77
 78	return 0;
 79}
 80
 81static char get_tiling_flag(struct drm_i915_gem_object *obj)
 82{
 83	switch (i915_gem_object_get_tiling(obj)) {
 84	default:
 85	case I915_TILING_NONE: return ' ';
 86	case I915_TILING_X: return 'X';
 87	case I915_TILING_Y: return 'Y';
 88	}
 89}
 90
 91static char get_global_flag(struct drm_i915_gem_object *obj)
 92{
 93	return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
 94}
 95
 96static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 97{
 98	return obj->mm.mapping ? 'M' : ' ';
 99}
100
101static const char *
102stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
103{
104	size_t x = 0;
105
106	switch (page_sizes) {
107	case 0:
108		return "";
109	case I915_GTT_PAGE_SIZE_4K:
110		return "4K";
111	case I915_GTT_PAGE_SIZE_64K:
112		return "64K";
113	case I915_GTT_PAGE_SIZE_2M:
114		return "2M";
115	default:
116		if (!buf)
117			return "M";
118
119		if (page_sizes & I915_GTT_PAGE_SIZE_2M)
120			x += snprintf(buf + x, len - x, "2M, ");
121		if (page_sizes & I915_GTT_PAGE_SIZE_64K)
122			x += snprintf(buf + x, len - x, "64K, ");
123		if (page_sizes & I915_GTT_PAGE_SIZE_4K)
124			x += snprintf(buf + x, len - x, "4K, ");
125		buf[x-2] = '\0';
126
127		return buf;
128	}
129}
130
131static const char *stringify_vma_type(const struct i915_vma *vma)
132{
133	if (i915_vma_is_ggtt(vma))
134		return "ggtt";
135
136	if (i915_vma_is_dpt(vma))
137		return "dpt";
138
139	return "ppgtt";
140}
141
142static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
143{
144	struct drm_i915_private *i915 = obj_to_i915(obj);
145
146	if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
147		switch (obj->pat_index) {
148		case 0: return " WB";
149		case 1: return " WT";
150		case 2: return " UC";
151		case 3: return " WB (1-Way Coh)";
152		case 4: return " WB (2-Way Coh)";
153		default: return " not defined";
154		}
155	} else if (GRAPHICS_VER(i915) >= 12) {
156		switch (obj->pat_index) {
157		case 0: return " WB";
158		case 1: return " WC";
159		case 2: return " WT";
160		case 3: return " UC";
161		default: return " not defined";
162		}
163	} else {
164		switch (obj->pat_index) {
165		case 0: return " UC";
166		case 1: return HAS_LLC(i915) ?
167			       " LLC" : " snooped";
168		case 2: return " L3+LLC";
169		case 3: return " WT";
170		default: return " not defined";
171		}
172	}
173}
174
175void
176i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
177{
178	struct i915_vma *vma;
179	int pin_count = 0;
180
181	seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
182		   &obj->base,
183		   get_tiling_flag(obj),
184		   get_global_flag(obj),
185		   get_pin_mapped_flag(obj),
186		   obj->base.size / 1024,
187		   obj->read_domains,
188		   obj->write_domain,
189		   i915_cache_level_str(obj),
190		   obj->mm.dirty ? " dirty" : "",
191		   obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
192	if (obj->base.name)
193		seq_printf(m, " (name: %d)", obj->base.name);
194
195	spin_lock(&obj->vma.lock);
196	list_for_each_entry(vma, &obj->vma.list, obj_link) {
197		if (!drm_mm_node_allocated(&vma->node))
198			continue;
199
200		spin_unlock(&obj->vma.lock);
201
202		if (i915_vma_is_pinned(vma))
203			pin_count++;
204
205		seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
206			   stringify_vma_type(vma),
207			   i915_vma_offset(vma), i915_vma_size(vma),
208			   stringify_page_sizes(vma->resource->page_sizes_gtt,
209						NULL, 0));
210		if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
211			switch (vma->gtt_view.type) {
212			case I915_GTT_VIEW_NORMAL:
213				seq_puts(m, ", normal");
214				break;
215
216			case I915_GTT_VIEW_PARTIAL:
217				seq_printf(m, ", partial [%08llx+%x]",
218					   vma->gtt_view.partial.offset << PAGE_SHIFT,
219					   vma->gtt_view.partial.size << PAGE_SHIFT);
220				break;
221
222			case I915_GTT_VIEW_ROTATED:
223				seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
224					   vma->gtt_view.rotated.plane[0].width,
225					   vma->gtt_view.rotated.plane[0].height,
226					   vma->gtt_view.rotated.plane[0].src_stride,
227					   vma->gtt_view.rotated.plane[0].dst_stride,
228					   vma->gtt_view.rotated.plane[0].offset,
229					   vma->gtt_view.rotated.plane[1].width,
230					   vma->gtt_view.rotated.plane[1].height,
231					   vma->gtt_view.rotated.plane[1].src_stride,
232					   vma->gtt_view.rotated.plane[1].dst_stride,
233					   vma->gtt_view.rotated.plane[1].offset);
234				break;
235
236			case I915_GTT_VIEW_REMAPPED:
237				seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
238					   vma->gtt_view.remapped.plane[0].width,
239					   vma->gtt_view.remapped.plane[0].height,
240					   vma->gtt_view.remapped.plane[0].src_stride,
241					   vma->gtt_view.remapped.plane[0].dst_stride,
242					   vma->gtt_view.remapped.plane[0].offset,
243					   vma->gtt_view.remapped.plane[1].width,
244					   vma->gtt_view.remapped.plane[1].height,
245					   vma->gtt_view.remapped.plane[1].src_stride,
246					   vma->gtt_view.remapped.plane[1].dst_stride,
247					   vma->gtt_view.remapped.plane[1].offset);
248				break;
249
250			default:
251				MISSING_CASE(vma->gtt_view.type);
252				break;
253			}
254		}
255		if (vma->fence)
256			seq_printf(m, " , fence: %d", vma->fence->id);
257		seq_puts(m, ")");
258
259		spin_lock(&obj->vma.lock);
260	}
261	spin_unlock(&obj->vma.lock);
262
263	seq_printf(m, " (pinned x %d)", pin_count);
264	if (i915_gem_object_is_stolen(obj))
265		seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
266	if (i915_gem_object_is_framebuffer(obj))
267		seq_printf(m, " (fb)");
268}
269
270static int i915_gem_object_info(struct seq_file *m, void *data)
271{
272	struct drm_i915_private *i915 = node_to_i915(m->private);
273	struct drm_printer p = drm_seq_file_printer(m);
274	struct intel_memory_region *mr;
275	enum intel_region_id id;
276
277	seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
278		   i915->mm.shrink_count,
279		   atomic_read(&i915->mm.free_count),
280		   i915->mm.shrink_memory);
281	for_each_memory_region(mr, i915, id)
282		intel_memory_region_debug(mr, &p);
283
284	return 0;
285}
286
287static int i915_frequency_info(struct seq_file *m, void *unused)
288{
289	struct drm_i915_private *i915 = node_to_i915(m->private);
290	struct intel_gt *gt = to_gt(i915);
291	struct drm_printer p = drm_seq_file_printer(m);
292
293	intel_gt_pm_frequency_dump(gt, &p);
294
295	return 0;
296}
297
298static const char *swizzle_string(unsigned swizzle)
299{
300	switch (swizzle) {
301	case I915_BIT_6_SWIZZLE_NONE:
302		return "none";
303	case I915_BIT_6_SWIZZLE_9:
304		return "bit9";
305	case I915_BIT_6_SWIZZLE_9_10:
306		return "bit9/bit10";
307	case I915_BIT_6_SWIZZLE_9_11:
308		return "bit9/bit11";
309	case I915_BIT_6_SWIZZLE_9_10_11:
310		return "bit9/bit10/bit11";
311	case I915_BIT_6_SWIZZLE_9_17:
312		return "bit9/bit17";
313	case I915_BIT_6_SWIZZLE_9_10_17:
314		return "bit9/bit10/bit17";
315	case I915_BIT_6_SWIZZLE_UNKNOWN:
316		return "unknown";
317	}
318
319	return "bug";
320}
321
322static int i915_swizzle_info(struct seq_file *m, void *data)
323{
324	struct drm_i915_private *dev_priv = node_to_i915(m->private);
325	struct intel_uncore *uncore = &dev_priv->uncore;
326	intel_wakeref_t wakeref;
327
328	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
329		   swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
330	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
331		   swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
332
333	if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
334		seq_puts(m, "L-shaped memory detected\n");
335
336	/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
337	if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
338		return 0;
339
340	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
341
342	if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
343		seq_printf(m, "DDC = 0x%08x\n",
344			   intel_uncore_read(uncore, DCC));
345		seq_printf(m, "DDC2 = 0x%08x\n",
346			   intel_uncore_read(uncore, DCC2));
347		seq_printf(m, "C0DRB3 = 0x%04x\n",
348			   intel_uncore_read16(uncore, C0DRB3_BW));
349		seq_printf(m, "C1DRB3 = 0x%04x\n",
350			   intel_uncore_read16(uncore, C1DRB3_BW));
351	} else if (GRAPHICS_VER(dev_priv) >= 6) {
352		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
353			   intel_uncore_read(uncore, MAD_DIMM_C0));
354		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
355			   intel_uncore_read(uncore, MAD_DIMM_C1));
356		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
357			   intel_uncore_read(uncore, MAD_DIMM_C2));
358		seq_printf(m, "TILECTL = 0x%08x\n",
359			   intel_uncore_read(uncore, TILECTL));
360		if (GRAPHICS_VER(dev_priv) >= 8)
361			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
362				   intel_uncore_read(uncore, GAMTARBMODE));
363		else
364			seq_printf(m, "ARB_MODE = 0x%08x\n",
365				   intel_uncore_read(uncore, ARB_MODE));
366		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
367			   intel_uncore_read(uncore, DISP_ARB_CTL));
368	}
369
370	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
371
372	return 0;
373}
374
375static int i915_rps_boost_info(struct seq_file *m, void *data)
376{
377	struct drm_i915_private *dev_priv = node_to_i915(m->private);
378	struct intel_rps *rps = &to_gt(dev_priv)->rps;
379
380	seq_printf(m, "RPS enabled? %s\n",
381		   str_yes_no(intel_rps_is_enabled(rps)));
382	seq_printf(m, "RPS active? %s\n",
383		   str_yes_no(intel_rps_is_active(rps)));
384	seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake));
385	seq_printf(m, "Boosts outstanding? %d\n",
386		   atomic_read(&rps->num_waiters));
387	seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
388	seq_printf(m, "Frequency requested %d, actual %d\n",
389		   intel_gpu_freq(rps, rps->cur_freq),
390		   intel_rps_read_actual_frequency(rps));
391	seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
392		   intel_gpu_freq(rps, rps->min_freq),
393		   intel_gpu_freq(rps, rps->min_freq_softlimit),
394		   intel_gpu_freq(rps, rps->max_freq_softlimit),
395		   intel_gpu_freq(rps, rps->max_freq));
396	seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
397		   intel_gpu_freq(rps, rps->idle_freq),
398		   intel_gpu_freq(rps, rps->efficient_freq),
399		   intel_gpu_freq(rps, rps->boost_freq));
400
401	seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
402
403	return 0;
404}
405
406static int i915_runtime_pm_status(struct seq_file *m, void *unused)
407{
408	struct drm_i915_private *dev_priv = node_to_i915(m->private);
409	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
410
411	if (!HAS_RUNTIME_PM(dev_priv))
412		seq_puts(m, "Runtime power management not supported\n");
413
414	seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));
415	seq_printf(m, "IRQs disabled: %s\n",
416		   str_yes_no(!intel_irqs_enabled(dev_priv)));
417#ifdef CONFIG_PM
418	seq_printf(m, "Usage count: %d\n",
419		   atomic_read(&dev_priv->drm.dev->power.usage_count));
420#else
421	seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
422#endif
423	seq_printf(m, "PCI device power state: %s [%d]\n",
424		   pci_power_name(pdev->current_state),
425		   pdev->current_state);
426
427	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
428		struct drm_printer p = drm_seq_file_printer(m);
429
430		print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
431	}
432
433	return 0;
434}
435
436static int i915_engine_info(struct seq_file *m, void *unused)
437{
438	struct drm_i915_private *i915 = node_to_i915(m->private);
439	struct intel_engine_cs *engine;
440	intel_wakeref_t wakeref;
441	struct drm_printer p;
442
443	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
444
445	seq_printf(m, "GT awake? %s [%d], %llums\n",
446		   str_yes_no(to_gt(i915)->awake),
447		   atomic_read(&to_gt(i915)->wakeref.count),
448		   ktime_to_ms(intel_gt_get_awake_time(to_gt(i915))));
449	seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
450		   to_gt(i915)->clock_frequency,
451		   to_gt(i915)->clock_period_ns);
452
453	p = drm_seq_file_printer(m);
454	for_each_uabi_engine(engine, i915)
455		intel_engine_dump(engine, &p, "%s\n", engine->name);
456
457	intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule);
458
459	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
460
461	return 0;
462}
463
464static int i915_wa_registers(struct seq_file *m, void *unused)
465{
466	struct drm_i915_private *i915 = node_to_i915(m->private);
467	struct intel_engine_cs *engine;
468
469	for_each_uabi_engine(engine, i915) {
470		const struct i915_wa_list *wal = &engine->ctx_wa_list;
471		const struct i915_wa *wa;
472		unsigned int count;
473
474		count = wal->count;
475		if (!count)
476			continue;
477
478		seq_printf(m, "%s: Workarounds applied: %u\n",
479			   engine->name, count);
480
481		for (wa = wal->list; count--; wa++)
482			seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
483				   i915_mmio_reg_offset(wa->reg),
484				   wa->set, wa->clr);
485
486		seq_printf(m, "\n");
487	}
488
489	return 0;
490}
491
492static int i915_wedged_get(void *data, u64 *val)
493{
494	struct drm_i915_private *i915 = data;
495	struct intel_gt *gt;
496	unsigned int i;
497
498	*val = 0;
499
500	for_each_gt(gt, i915, i) {
501		int ret;
502
503		ret = intel_gt_debugfs_reset_show(gt, val);
504		if (ret)
505			return ret;
506
507		/* at least one tile should be wedged */
508		if (*val)
509			break;
510	}
511
512	return 0;
513}
514
515static int i915_wedged_set(void *data, u64 val)
516{
517	struct drm_i915_private *i915 = data;
518	struct intel_gt *gt;
519	unsigned int i;
520
521	for_each_gt(gt, i915, i)
522		intel_gt_debugfs_reset_store(gt, val);
523
524	return 0;
525}
526
527DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
528			i915_wedged_get, i915_wedged_set,
529			"%llu\n");
530
531static int
532i915_perf_noa_delay_set(void *data, u64 val)
533{
534	struct drm_i915_private *i915 = data;
535
536	/*
537	 * This would lead to infinite waits as we're doing timestamp
538	 * difference on the CS with only 32bits.
539	 */
540	if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)
541		return -EINVAL;
542
543	atomic64_set(&i915->perf.noa_programming_delay, val);
544	return 0;
545}
546
547static int
548i915_perf_noa_delay_get(void *data, u64 *val)
549{
550	struct drm_i915_private *i915 = data;
551
552	*val = atomic64_read(&i915->perf.noa_programming_delay);
553	return 0;
554}
555
556DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
557			i915_perf_noa_delay_get,
558			i915_perf_noa_delay_set,
559			"%llu\n");
560
561#define DROP_UNBOUND	BIT(0)
562#define DROP_BOUND	BIT(1)
563#define DROP_RETIRE	BIT(2)
564#define DROP_ACTIVE	BIT(3)
565#define DROP_FREED	BIT(4)
566#define DROP_SHRINK_ALL	BIT(5)
567#define DROP_IDLE	BIT(6)
568#define DROP_RESET_ACTIVE	BIT(7)
569#define DROP_RESET_SEQNO	BIT(8)
570#define DROP_RCU	BIT(9)
571#define DROP_ALL (DROP_UNBOUND	| \
572		  DROP_BOUND	| \
573		  DROP_RETIRE	| \
574		  DROP_ACTIVE	| \
575		  DROP_FREED	| \
576		  DROP_SHRINK_ALL |\
577		  DROP_IDLE	| \
578		  DROP_RESET_ACTIVE | \
579		  DROP_RESET_SEQNO | \
580		  DROP_RCU)
581static int
582i915_drop_caches_get(void *data, u64 *val)
583{
584	*val = DROP_ALL;
585
586	return 0;
587}
588
589static int
590gt_drop_caches(struct intel_gt *gt, u64 val)
591{
592	int ret;
593
594	if (val & DROP_RESET_ACTIVE &&
595	    wait_for(intel_engines_are_idle(gt), 200))
596		intel_gt_set_wedged(gt);
597
598	if (val & DROP_RETIRE)
599		intel_gt_retire_requests(gt);
600
601	if (val & (DROP_IDLE | DROP_ACTIVE)) {
602		ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
603		if (ret)
604			return ret;
605	}
606
607	if (val & DROP_IDLE) {
608		ret = intel_gt_pm_wait_for_idle(gt);
609		if (ret)
610			return ret;
611	}
612
613	if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
614		intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
615
616	if (val & DROP_FREED)
617		intel_gt_flush_buffer_pool(gt);
618
619	return 0;
620}
621
622static int
623i915_drop_caches_set(void *data, u64 val)
624{
625	struct drm_i915_private *i915 = data;
626	struct intel_gt *gt;
627	unsigned int flags;
628	unsigned int i;
629	int ret;
630
631	drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n",
632		val, val & DROP_ALL);
633
634	for_each_gt(gt, i915, i) {
635		ret = gt_drop_caches(gt, val);
636		if (ret)
637			return ret;
638	}
639
640	fs_reclaim_acquire(GFP_KERNEL);
641	flags = memalloc_noreclaim_save();
642	if (val & DROP_BOUND)
643		i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
644
645	if (val & DROP_UNBOUND)
646		i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
647
648	if (val & DROP_SHRINK_ALL)
649		i915_gem_shrink_all(i915);
650	memalloc_noreclaim_restore(flags);
651	fs_reclaim_release(GFP_KERNEL);
652
653	if (val & DROP_RCU)
654		rcu_barrier();
655
656	if (val & DROP_FREED)
657		i915_gem_drain_freed_objects(i915);
658
659	return 0;
660}
661
662DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
663			i915_drop_caches_get, i915_drop_caches_set,
664			"0x%08llx\n");
665
666static int i915_sseu_status(struct seq_file *m, void *unused)
667{
668	struct drm_i915_private *i915 = node_to_i915(m->private);
669	struct intel_gt *gt = to_gt(i915);
670
671	return intel_sseu_status(m, gt);
672}
673
674static int i915_forcewake_open(struct inode *inode, struct file *file)
675{
676	struct drm_i915_private *i915 = inode->i_private;
677	struct intel_gt *gt;
678	unsigned int i;
679
680	for_each_gt(gt, i915, i)
681		intel_gt_pm_debugfs_forcewake_user_open(gt);
682
683	return 0;
684}
685
686static int i915_forcewake_release(struct inode *inode, struct file *file)
687{
688	struct drm_i915_private *i915 = inode->i_private;
689	struct intel_gt *gt;
690	unsigned int i;
691
692	for_each_gt(gt, i915, i)
693		intel_gt_pm_debugfs_forcewake_user_release(gt);
694
695	return 0;
696}
697
698static const struct file_operations i915_forcewake_fops = {
699	.owner = THIS_MODULE,
700	.open = i915_forcewake_open,
701	.release = i915_forcewake_release,
702};
703
704static const struct drm_info_list i915_debugfs_list[] = {
705	{"i915_capabilities", i915_capabilities, 0},
706	{"i915_gem_objects", i915_gem_object_info, 0},
707	{"i915_frequency_info", i915_frequency_info, 0},
708	{"i915_swizzle_info", i915_swizzle_info, 0},
709	{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
710	{"i915_engine_info", i915_engine_info, 0},
711	{"i915_wa_registers", i915_wa_registers, 0},
712	{"i915_sseu_status", i915_sseu_status, 0},
713	{"i915_rps_boost_info", i915_rps_boost_info, 0},
714};
715
716static const struct i915_debugfs_files {
717	const char *name;
718	const struct file_operations *fops;
719} i915_debugfs_files[] = {
720	{"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
721	{"i915_wedged", &i915_wedged_fops},
722	{"i915_gem_drop_caches", &i915_drop_caches_fops},
723};
724
725void i915_debugfs_register(struct drm_i915_private *i915)
726{
727	struct dentry *debugfs_root = i915->drm.debugfs_root;
728	int i;
729
730	i915_debugfs_params(i915);
731
732	debugfs_create_file("i915_forcewake_user", S_IRUSR, debugfs_root,
733			    i915, &i915_forcewake_fops);
734	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
735		debugfs_create_file(i915_debugfs_files[i].name, S_IRUGO | S_IWUSR,
736				    debugfs_root, i915,
737				    i915_debugfs_files[i].fops);
738	}
739
740	drm_debugfs_create_files(i915_debugfs_list,
741				 ARRAY_SIZE(i915_debugfs_list),
742				 debugfs_root, i915->drm.primary);
743
744	i915_gpu_error_debugfs_register(i915);
745}