fb_decoder.c

  1/*
  2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 21 * SOFTWARE.
 22 *
 23 * Authors:
 24 *    Kevin Tian <kevin.tian@intel.com>
 25 *
 26 * Contributors:
 27 *    Bing Niu <bing.niu@intel.com>
 28 *    Xu Han <xu.han@intel.com>
 29 *    Ping Gao <ping.a.gao@intel.com>
 30 *    Xiaoguang Chen <xiaoguang.chen@intel.com>
 31 *    Yang Liu <yang2.liu@intel.com>
 32 *    Tina Zhang <tina.zhang@intel.com>
 33 *
 34 */
 35
 36#include <uapi/drm/drm_fourcc.h>
 37
 38#include "gvt.h"
 39#include "i915_drv.h"
 40#include "i915_pvinfo.h"
 41#include "i915_reg.h"
 42#include "display/intel_display_regs.h"
 43
 44#include "display/i9xx_plane_regs.h"
 45#include "display/intel_cursor_regs.h"
 46#include "display/intel_display_core.h"
 47#include "display/intel_sprite_regs.h"
 48#include "display/skl_universal_plane_regs.h"
 49
 50#define PRIMARY_FORMAT_NUM	16
 51struct pixel_format {
 52	int drm_format;	/* Pixel format in DRM definition */
 53	int bpp; /* Bits per pixel, 0 indicates invalid */
 54	const char *desc; /* The description */
 55};
 56
 57static const struct pixel_format bdw_pixel_formats[] = {
 58	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
 59	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
 60	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
 61	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
 62
 63	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
 64	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
 65
 66	/* non-supported format has bpp default to 0 */
 67	{}
 68};
 69
 70static const struct pixel_format skl_pixel_formats[] = {
 71	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
 72	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
 73	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
 74	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
 75
 76	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
 77	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
 78	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
 79	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
 80
 81	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
 82	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
 83	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
 84	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
 85
 86	/* non-supported format has bpp default to 0 */
 87	{}
 88};
 89
 90static int bdw_format_to_drm(int format)
 91{
 92	int bdw_pixel_formats_index = 6;
 93
 94	switch (format) {
 95	case DISP_FORMAT_8BPP:
 96		bdw_pixel_formats_index = 0;
 97		break;
 98	case DISP_FORMAT_BGRX565:
 99		bdw_pixel_formats_index = 1;
100		break;
101	case DISP_FORMAT_BGRX888:
102		bdw_pixel_formats_index = 2;
103		break;
104	case DISP_FORMAT_RGBX101010:
105		bdw_pixel_formats_index = 3;
106		break;
107	case DISP_FORMAT_BGRX101010:
108		bdw_pixel_formats_index = 4;
109		break;
110	case DISP_FORMAT_RGBX888:
111		bdw_pixel_formats_index = 5;
112		break;
113
114	default:
115		break;
116	}
117
118	return bdw_pixel_formats_index;
119}
120
121static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
122	int yuv_order)
123{
124	int skl_pixel_formats_index = 12;
125
126	switch (format) {
127	case PLANE_CTL_FORMAT_INDEXED:
128		skl_pixel_formats_index = 4;
129		break;
130	case PLANE_CTL_FORMAT_RGB_565:
131		skl_pixel_formats_index = 5;
132		break;
133	case PLANE_CTL_FORMAT_XRGB_8888:
134		if (rgb_order)
135			skl_pixel_formats_index = alpha ? 6 : 7;
136		else
137			skl_pixel_formats_index = alpha ? 8 : 9;
138		break;
139	case PLANE_CTL_FORMAT_XRGB_2101010:
140		skl_pixel_formats_index = rgb_order ? 10 : 11;
141		break;
142	case PLANE_CTL_FORMAT_YUV422:
143		skl_pixel_formats_index = yuv_order >> 16;
144		if (skl_pixel_formats_index > 3)
145			return -EINVAL;
146		break;
147
148	default:
149		break;
150	}
151
152	return skl_pixel_formats_index;
153}
154
155static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
156	u32 tiled, int stride_mask, int bpp)
157{
158	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
159	struct intel_display *display = dev_priv->display;
160
161	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask;
162	u32 stride = stride_reg;
163
164	if (GRAPHICS_VER(dev_priv) >= 9) {
165		switch (tiled) {
166		case PLANE_CTL_TILED_LINEAR:
167			stride = stride_reg * 64;
168			break;
169		case PLANE_CTL_TILED_X:
170			stride = stride_reg * 512;
171			break;
172		case PLANE_CTL_TILED_Y:
173			stride = stride_reg * 128;
174			break;
175		case PLANE_CTL_TILED_YF:
176			if (bpp == 8)
177				stride = stride_reg * 64;
178			else if (bpp == 16 || bpp == 32 || bpp == 64)
179				stride = stride_reg * 128;
180			else
181				gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
182			break;
183		default:
184			gvt_dbg_core("skl: unsupported tile format:%x\n",
185				tiled);
186		}
187	}
188
189	return stride;
190}
191
192static int get_active_pipe(struct intel_vgpu *vgpu)
193{
194	int i;
195
196	for (i = 0; i < I915_MAX_PIPES; i++)
197		if (pipe_is_enabled(vgpu, i))
198			break;
199
200	return i;
201}
202
203/**
204 * intel_vgpu_decode_primary_plane - Decode primary plane
205 * @vgpu: input vgpu
206 * @plane: primary plane to save decoded info
207 * This function is called for decoding plane
208 *
209 * Returns:
210 * 0 on success, non-zero if failed.
211 */
212int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
213	struct intel_vgpu_primary_plane_format *plane)
214{
215	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
216	struct intel_display *display = dev_priv->display;
217	u32 val, fmt;
218	int pipe;
219
220	pipe = get_active_pipe(vgpu);
221	if (pipe >= I915_MAX_PIPES)
222		return -ENODEV;
223
224	val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));
225	plane->enabled = !!(val & DISP_ENABLE);
226	if (!plane->enabled)
227		return -ENODEV;
228
229	if (GRAPHICS_VER(dev_priv) >= 9) {
230		plane->tiled = val & PLANE_CTL_TILED_MASK;
231		fmt = skl_format_to_drm(
232			val & PLANE_CTL_FORMAT_MASK_SKL,
233			val & PLANE_CTL_ORDER_RGBX,
234			val & PLANE_CTL_ALPHA_MASK,
235			val & PLANE_CTL_YUV422_ORDER_MASK);
236
237		if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
238			gvt_vgpu_err("Out-of-bounds pixel format index\n");
239			return -EINVAL;
240		}
241
242		plane->bpp = skl_pixel_formats[fmt].bpp;
243		plane->drm_format = skl_pixel_formats[fmt].drm_format;
244	} else {
245		plane->tiled = val & DISP_TILED;
246		fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
247		plane->bpp = bdw_pixel_formats[fmt].bpp;
248		plane->drm_format = bdw_pixel_formats[fmt].drm_format;
249	}
250
251	if (!plane->bpp) {
252		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
253		return -EINVAL;
254	}
255
256	plane->hw_format = fmt;
257
258	plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK;
259	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
260		return  -EINVAL;
261
262	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
263	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
264		gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
265				plane->base);
266		return  -EINVAL;
267	}
268
269	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
270		(GRAPHICS_VER(dev_priv) >= 9) ?
271		(_PRI_PLANE_STRIDE_MASK >> 6) :
272		_PRI_PLANE_STRIDE_MASK, plane->bpp);
273
274	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >>
275		_PIPE_H_SRCSZ_SHIFT;
276	plane->width += 1;
277	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) &
278			 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
279	plane->height += 1;	/* raw height is one minus the real value */
280
281	val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe));
282	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
283		_PRI_PLANE_X_OFF_SHIFT;
284	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
285		_PRI_PLANE_Y_OFF_SHIFT;
286
287	return 0;
288}
289
290#define CURSOR_FORMAT_NUM	(1 << 6)
291struct cursor_mode_format {
292	int drm_format;	/* Pixel format in DRM definition */
293	u8 bpp; /* Bits per pixel; 0 indicates invalid */
294	u32 width; /* In pixel */
295	u32 height; /* In lines */
296	const char *desc; /* The description */
297};
298
299static const struct cursor_mode_format cursor_pixel_formats[] = {
300	{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
301	{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
302	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
303	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
304
305	/* non-supported format has bpp default to 0 */
306	{}
307};
308
309static int cursor_mode_to_drm(int mode)
310{
311	int cursor_pixel_formats_index = 4;
312
313	switch (mode) {
314	case MCURSOR_MODE_128_ARGB_AX:
315		cursor_pixel_formats_index = 0;
316		break;
317	case MCURSOR_MODE_256_ARGB_AX:
318		cursor_pixel_formats_index = 1;
319		break;
320	case MCURSOR_MODE_64_ARGB_AX:
321		cursor_pixel_formats_index = 2;
322		break;
323	case MCURSOR_MODE_64_32B_AX:
324		cursor_pixel_formats_index = 3;
325		break;
326
327	default:
328		break;
329	}
330
331	return cursor_pixel_formats_index;
332}
333
334/**
335 * intel_vgpu_decode_cursor_plane - Decode sprite plane
336 * @vgpu: input vgpu
337 * @plane: cursor plane to save decoded info
338 * This function is called for decoding plane
339 *
340 * Returns:
341 * 0 on success, non-zero if failed.
342 */
343int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
344	struct intel_vgpu_cursor_plane_format *plane)
345{
346	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
347	struct intel_display *display = dev_priv->display;
348	u32 val, mode, index;
349	u32 alpha_plane, alpha_force;
350	int pipe;
351
352	pipe = get_active_pipe(vgpu);
353	if (pipe >= I915_MAX_PIPES)
354		return -ENODEV;
355
356	val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe));
357	mode = val & MCURSOR_MODE_MASK;
358	plane->enabled = (mode != MCURSOR_MODE_DISABLE);
359	if (!plane->enabled)
360		return -ENODEV;
361
362	index = cursor_mode_to_drm(mode);
363
364	if (!cursor_pixel_formats[index].bpp) {
365		gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
366		return -EINVAL;
367	}
368	plane->mode = mode;
369	plane->bpp = cursor_pixel_formats[index].bpp;
370	plane->drm_format = cursor_pixel_formats[index].drm_format;
371	plane->width = cursor_pixel_formats[index].width;
372	plane->height = cursor_pixel_formats[index].height;
373
374	alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
375				_CURSOR_ALPHA_PLANE_SHIFT;
376	alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
377				_CURSOR_ALPHA_FORCE_SHIFT;
378	if (alpha_plane || alpha_force)
379		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
380			alpha_plane, alpha_force);
381
382	plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK;
383	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
384		return  -EINVAL;
385
386	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
387	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
388		gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
389				plane->base);
390		return  -EINVAL;
391	}
392
393	val = vgpu_vreg_t(vgpu, CURPOS(display, pipe));
394	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
395	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
396	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
397	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
398
399	plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
400	plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
401	return 0;
402}