display.h

  1/*
  2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 21 * SOFTWARE.
 22 *
 23 * Authors:
 24 *    Ke Yu
 25 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
 26 *
 27 * Contributors:
 28 *    Terrence Xu <terrence.xu@intel.com>
 29 *    Changbin Du <changbin.du@intel.com>
 30 *    Bing Niu <bing.niu@intel.com>
 31 *    Zhi Wang <zhi.a.wang@intel.com>
 32 *
 33 */
 34
 35#ifndef _GVT_DISPLAY_H_
 36#define _GVT_DISPLAY_H_
 37
 38#include <linux/types.h>
 39#include <linux/hrtimer.h>
 40
 41struct intel_gvt;
 42struct intel_vgpu;
 43
 44#define SBI_REG_MAX	20
 45#define DPCD_SIZE	0x700
 46
 47#define intel_vgpu_port(vgpu, port) \
 48	(&(vgpu->display.ports[port]))
 49
 50#define intel_vgpu_has_monitor_on_port(vgpu, port) \
 51	(intel_vgpu_port(vgpu, port)->edid && \
 52		intel_vgpu_port(vgpu, port)->edid->data_valid)
 53
 54#define intel_vgpu_port_is_dp(vgpu, port) \
 55	((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
 56	(intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
 57	(intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
 58	(intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
 59
 60#define INTEL_GVT_MAX_UEVENT_VARS	3
 61
 62#define AUX_NATIVE_REPLY_NAK    (0x1 << 4)
 63
 64#define AUX_BURST_SIZE          20
 65
 66struct intel_vgpu_sbi_register {
 67	unsigned int offset;
 68	u32 value;
 69};
 70
 71struct intel_vgpu_sbi {
 72	int number;
 73	struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
 74};
 75
 76enum intel_gvt_plane_type {
 77	PRIMARY_PLANE = 0,
 78	CURSOR_PLANE,
 79	SPRITE_PLANE,
 80	MAX_PLANE
 81};
 82
 83struct intel_vgpu_dpcd_data {
 84	bool data_valid;
 85	u8 data[DPCD_SIZE];
 86};
 87
 88enum intel_vgpu_port_type {
 89	GVT_CRT = 0,
 90	GVT_DP_A,
 91	GVT_DP_B,
 92	GVT_DP_C,
 93	GVT_DP_D,
 94	GVT_HDMI_B,
 95	GVT_HDMI_C,
 96	GVT_HDMI_D,
 97	GVT_PORT_MAX
 98};
 99
100enum intel_vgpu_edid {
101	GVT_EDID_1024_768,
102	GVT_EDID_1920_1200,
103	GVT_EDID_NUM,
104};
105
106#define GVT_DEFAULT_REFRESH_RATE 60
107struct intel_vgpu_port {
108	/* per display EDID information */
109	struct intel_vgpu_edid_data *edid;
110	/* per display DPCD information */
111	struct intel_vgpu_dpcd_data *dpcd;
112	int type;
113	enum intel_vgpu_edid id;
114	/* x1000 to get accurate 59.94, 24.976, 29.94, etc. in timing std. */
115	u32 vrefresh_k;
116};
117
118struct intel_vgpu_vblank_timer {
119	struct hrtimer timer;
120	u32 vrefresh_k;
121	u64 period;
122};
123
124static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
125{
126	switch (id) {
127	case GVT_EDID_1024_768:
128		return "1024x768";
129	case GVT_EDID_1920_1200:
130		return "1920x1200";
131	default:
132		return "";
133	}
134}
135
136static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
137{
138	switch (id) {
139	case GVT_EDID_1024_768:
140		return 1024;
141	case GVT_EDID_1920_1200:
142		return 1920;
143	default:
144		return 0;
145	}
146}
147
148static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
149{
150	switch (id) {
151	case GVT_EDID_1024_768:
152		return 768;
153	case GVT_EDID_1920_1200:
154		return 1200;
155	default:
156		return 0;
157	}
158}
159
160void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu);
161void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
162
163int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
164void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
165void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
166
167int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
168
169#endif