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display.c
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linux-6.19.14/drivers/gpu/drm/i915/gvt/display.c
1/* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35#include <drm/display/drm_dp.h> 36#include <drm/drm_print.h> 37 38#include "i915_drv.h" 39#include "i915_reg.h" 40#include "display/intel_display_regs.h" 41#include "gvt.h" 42 43#include "display/bxt_dpio_phy_regs.h" 44#include "display/i9xx_plane_regs.h" 45#include "display/intel_crt_regs.h" 46#include "display/intel_cursor_regs.h" 47#include "display/intel_display.h" 48#include "display/intel_display_core.h" 49#include "display/intel_dpio_phy.h" 50#include "display/intel_sprite_regs.h" 51 52static int get_edp_pipe(struct intel_vgpu *vgpu) 53{ 54 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 55 int pipe = -1; 56 57 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 58 case TRANS_DDI_EDP_INPUT_A_ON: 59 case TRANS_DDI_EDP_INPUT_A_ONOFF: 60 pipe = PIPE_A; 61 break; 62 case TRANS_DDI_EDP_INPUT_B_ONOFF: 63 pipe = PIPE_B; 64 break; 65 case TRANS_DDI_EDP_INPUT_C_ONOFF: 66 pipe = PIPE_C; 67 break; 68 } 69 return pipe; 70} 71 72static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 73{ 74 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 75 struct intel_display *display = dev_priv->display; 76 77 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 78 return 0; 79 80 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 81 return 0; 82 return 1; 83} 84 85int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 86{ 87 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 88 struct intel_display *display = dev_priv->display; 89 90 if (drm_WARN_ON(&dev_priv->drm, 91 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 92 return -EINVAL; 93 94 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) 95 return 1; 96 97 if (edp_pipe_is_enabled(vgpu) && 98 get_edp_pipe(vgpu) == pipe) 99 return 1; 100 return 0; 101} 102 103static const unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 104 { 105/* EDID with 1024x768 as its resolution */ 106 /*Header*/ 107 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 108 /* Vendor & Product Identification */ 109 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 110 /* Version & Revision */ 111 0x01, 0x04, 112 /* Basic Display Parameters & Features */ 113 0xa5, 0x34, 0x20, 0x78, 0x23, 114 /* Color Characteristics */ 115 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 116 /* Established Timings: maximum resolution is 1024x768 */ 117 0x21, 0x08, 0x00, 118 /* Standard Timings. All invalid */ 119 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 120 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 121 /* 18 Byte Data Blocks 1: invalid */ 122 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 123 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 124 /* 18 Byte Data Blocks 2: invalid */ 125 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 126 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 127 /* 18 Byte Data Blocks 3: invalid */ 128 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 129 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 130 /* 18 Byte Data Blocks 4: invalid */ 131 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 132 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 133 /* Extension Block Count */ 134 0x00, 135 /* Checksum */ 136 0xef, 137 }, 138 { 139/* EDID with 1920x1200 as its resolution */ 140 /*Header*/ 141 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 142 /* Vendor & Product Identification */ 143 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 144 /* Version & Revision */ 145 0x01, 0x04, 146 /* Basic Display Parameters & Features */ 147 0xa5, 0x34, 0x20, 0x78, 0x23, 148 /* Color Characteristics */ 149 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 150 /* Established Timings: maximum resolution is 1024x768 */ 151 0x21, 0x08, 0x00, 152 /* 153 * Standard Timings. 154 * below new resolutions can be supported: 155 * 1920x1080, 1280x720, 1280x960, 1280x1024, 156 * 1440x900, 1600x1200, 1680x1050 157 */ 158 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 159 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 160 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 161 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 162 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 163 /* 18 Byte Data Blocks 2: invalid */ 164 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 165 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 166 /* 18 Byte Data Blocks 3: invalid */ 167 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 168 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 169 /* 18 Byte Data Blocks 4: invalid */ 170 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 171 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 172 /* Extension Block Count */ 173 0x00, 174 /* Checksum */ 175 0x45, 176 }, 177}; 178 179#define DPCD_HEADER_SIZE 0xb 180 181/* let the virtual display supports DP1.2 */ 182static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 183 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 184}; 185 186static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 187{ 188 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 189 struct intel_display *display = dev_priv->display; 190 int pipe; 191 192 if (IS_BROXTON(dev_priv)) { 193 enum transcoder trans; 194 enum port port; 195 196 /* Clear PIPE, DDI, PHY, HPD before setting new */ 197 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 198 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 199 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 200 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 201 202 for_each_pipe(display, pipe) { 203 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= 204 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 205 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 206 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 207 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 208 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 209 } 210 211 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 212 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= 213 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 214 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 215 } 216 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 217 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 218 TRANS_DDI_PORT_MASK); 219 220 for (port = PORT_A; port <= PORT_C; port++) { 221 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 222 ~BXT_PHY_LANE_ENABLED; 223 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 224 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 225 BXT_PHY_LANE_POWERDOWN_ACK); 226 227 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 228 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 229 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 230 PORT_PLL_ENABLE); 231 232 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 233 ~(DDI_INIT_DISPLAY_DETECTED | 234 DDI_BUF_CTL_ENABLE); 235 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 236 } 237 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 238 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 239 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 240 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 241 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 242 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 243 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 244 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 245 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 246 247 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 248 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 249 ~PHY_POWER_GOOD; 250 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 251 ~PHY_POWER_GOOD; 252 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 253 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 254 255 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 256 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 257 258 /* 259 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 260 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 261 * TRANSCODER_A can be enabled. PORT_x depends on the input of 262 * setup_virtual_dp_monitor. 263 */ 264 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 265 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 266 267 /* 268 * Golden M/N are calculated based on: 269 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 270 * DP link clk 1620 MHz and non-constant_n. 271 * TODO: calculate DP link symbol clk and stream clk m/n. 272 */ 273 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 274 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 275 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 276 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 277 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 278 279 /* Enable per-DDI/PORT vreg */ 280 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 281 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 282 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 283 PHY_POWER_GOOD; 284 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 285 BIT(30); 286 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 287 BXT_PHY_LANE_ENABLED; 288 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 289 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 290 BXT_PHY_LANE_POWERDOWN_ACK); 291 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 292 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 293 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 294 PORT_PLL_ENABLE); 295 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 296 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 297 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 298 ~DDI_BUF_IS_IDLE; 299 vgpu_vreg_t(vgpu, 300 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |= 301 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 302 TRANS_DDI_FUNC_ENABLE); 303 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 304 PORTA_HOTPLUG_ENABLE; 305 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 306 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 307 } 308 309 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 310 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 311 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 312 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 313 PHY_POWER_GOOD; 314 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 315 BIT(30); 316 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 317 BXT_PHY_LANE_ENABLED; 318 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 319 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 320 BXT_PHY_LANE_POWERDOWN_ACK); 321 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 322 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 323 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 324 PORT_PLL_ENABLE); 325 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 326 DDI_BUF_CTL_ENABLE; 327 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 328 ~DDI_BUF_IS_IDLE; 329 vgpu_vreg_t(vgpu, 330 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 331 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 332 (PORT_B << TRANS_DDI_PORT_SHIFT) | 333 TRANS_DDI_FUNC_ENABLE); 334 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 335 PORTB_HOTPLUG_ENABLE; 336 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 337 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 338 } 339 340 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 341 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 342 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 343 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 344 PHY_POWER_GOOD; 345 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 346 BIT(30); 347 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 348 BXT_PHY_LANE_ENABLED; 349 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 350 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 351 BXT_PHY_LANE_POWERDOWN_ACK); 352 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 353 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 354 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 355 PORT_PLL_ENABLE); 356 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 357 DDI_BUF_CTL_ENABLE; 358 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 359 ~DDI_BUF_IS_IDLE; 360 vgpu_vreg_t(vgpu, 361 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 362 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 363 (PORT_B << TRANS_DDI_PORT_SHIFT) | 364 TRANS_DDI_FUNC_ENABLE); 365 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 366 PORTC_HOTPLUG_ENABLE; 367 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 368 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 369 } 370 371 return; 372 } 373 374 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 375 SDE_PORTC_HOTPLUG_CPT | 376 SDE_PORTD_HOTPLUG_CPT); 377 378 if (IS_SKYLAKE(dev_priv) || 379 IS_KABYLAKE(dev_priv) || 380 IS_COFFEELAKE(dev_priv) || 381 IS_COMETLAKE(dev_priv)) { 382 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 383 SDE_PORTE_HOTPLUG_SPT); 384 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 385 SKL_FUSE_DOWNLOAD_STATUS | 386 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 387 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 388 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 389 /* 390 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 391 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 392 * TRANSCODER_A can be enabled. PORT_x depends on the input of 393 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 394 * so we fixed to DPLL0 here. 395 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 396 */ 397 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 398 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 399 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 400 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 401 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 402 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 403 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 404 /* 405 * Golden M/N are calculated based on: 406 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 407 * DP link clk 1620 MHz and non-constant_n. 408 * TODO: calculate DP link symbol clk and stream clk m/n. 409 */ 410 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 411 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 412 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 413 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 414 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 415 } 416 417 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 418 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 419 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 420 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 421 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 422 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 423 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 424 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 425 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 426 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 427 TRANS_DDI_PORT_MASK); 428 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 429 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 430 (PORT_B << TRANS_DDI_PORT_SHIFT) | 431 TRANS_DDI_FUNC_ENABLE); 432 if (IS_BROADWELL(dev_priv)) { 433 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 434 ~PORT_CLK_SEL_MASK; 435 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 436 PORT_CLK_SEL_LCPLL_810; 437 } 438 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 439 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 440 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 441 } 442 443 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 444 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 445 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 446 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 447 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 448 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 449 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 450 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 451 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 452 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 453 TRANS_DDI_PORT_MASK); 454 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 455 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 456 (PORT_C << TRANS_DDI_PORT_SHIFT) | 457 TRANS_DDI_FUNC_ENABLE); 458 if (IS_BROADWELL(dev_priv)) { 459 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 460 ~PORT_CLK_SEL_MASK; 461 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 462 PORT_CLK_SEL_LCPLL_810; 463 } 464 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 465 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 466 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 467 } 468 469 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 470 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 471 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 472 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 473 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 474 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 475 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 476 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 477 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 478 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 479 TRANS_DDI_PORT_MASK); 480 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 481 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 482 (PORT_D << TRANS_DDI_PORT_SHIFT) | 483 TRANS_DDI_FUNC_ENABLE); 484 if (IS_BROADWELL(dev_priv)) { 485 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 486 ~PORT_CLK_SEL_MASK; 487 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 488 PORT_CLK_SEL_LCPLL_810; 489 } 490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 491 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 492 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 493 } 494 495 if ((IS_SKYLAKE(dev_priv) || 496 IS_KABYLAKE(dev_priv) || 497 IS_COFFEELAKE(dev_priv) || 498 IS_COMETLAKE(dev_priv)) && 499 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 500 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 501 } 502 503 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 504 if (IS_BROADWELL(dev_priv)) 505 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 506 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 507 else 508 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 509 510 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 511 } 512 513 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 514 if (IS_BROADWELL(dev_priv)) 515 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 516 517 /* Disable Primary/Sprite/Cursor plane */ 518 for_each_pipe(display, pipe) { 519 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 520 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 521 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 522 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 523 } 524 525 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 526} 527 528static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 529{ 530 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 531 532 kfree(port->edid); 533 port->edid = NULL; 534 535 kfree(port->dpcd); 536 port->dpcd = NULL; 537} 538 539static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 540{ 541 struct intel_vgpu_vblank_timer *vblank_timer; 542 struct intel_vgpu *vgpu; 543 544 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 545 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 546 547 /* Set vblank emulation request per-vGPU bit */ 548 intel_gvt_request_service(vgpu->gvt, 549 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 550 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 551 return HRTIMER_RESTART; 552} 553 554static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 555 int type, unsigned int resolution) 556{ 557 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 558 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 559 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 560 561 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 562 return -EINVAL; 563 564 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 565 if (!port->edid) 566 return -ENOMEM; 567 568 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 569 if (!port->dpcd) { 570 kfree(port->edid); 571 return -ENOMEM; 572 } 573 574 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 575 EDID_SIZE); 576 port->edid->data_valid = true; 577 578 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 579 port->dpcd->data_valid = true; 580 port->dpcd->data[DP_SINK_COUNT] = 0x1; 581 port->type = type; 582 port->id = resolution; 583 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 584 vgpu->display.port_num = port_num; 585 586 /* Init hrtimer based on default refresh rate */ 587 hrtimer_setup(&vblank_timer->timer, vblank_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 588 vblank_timer->vrefresh_k = port->vrefresh_k; 589 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 590 591 emulate_monitor_status_change(vgpu); 592 593 return 0; 594} 595 596/** 597 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 598 * @vgpu: vGPU operated 599 * @turnon: Turn ON/OFF vblank_timer 600 * 601 * This function is used to turn on/off or update the per-vGPU vblank_timer 602 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated 603 * if guest changed the refresh rate. 604 * 605 */ 606void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 607{ 608 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 609 struct intel_vgpu_port *port = 610 intel_vgpu_port(vgpu, vgpu->display.port_num); 611 612 if (turnon) { 613 /* 614 * Skip the re-enable if already active and vrefresh unchanged. 615 * Otherwise, stop timer if already active and restart with new 616 * period. 617 */ 618 if (vblank_timer->vrefresh_k != port->vrefresh_k || 619 !hrtimer_active(&vblank_timer->timer)) { 620 /* Stop timer before start with new period if active */ 621 if (hrtimer_active(&vblank_timer->timer)) 622 hrtimer_cancel(&vblank_timer->timer); 623 624 /* Make sure new refresh rate updated to timer period */ 625 vblank_timer->vrefresh_k = port->vrefresh_k; 626 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 627 hrtimer_start(&vblank_timer->timer, 628 ktime_add_ns(ktime_get(), vblank_timer->period), 629 HRTIMER_MODE_ABS); 630 } 631 } else { 632 /* Caller request to stop vblank */ 633 hrtimer_cancel(&vblank_timer->timer); 634 } 635} 636 637static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 638{ 639 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 640 struct intel_display *display = dev_priv->display; 641 struct intel_vgpu_irq *irq = &vgpu->irq; 642 int vblank_event[] = { 643 [PIPE_A] = PIPE_A_VBLANK, 644 [PIPE_B] = PIPE_B_VBLANK, 645 [PIPE_C] = PIPE_C_VBLANK, 646 }; 647 int event; 648 649 if (pipe < PIPE_A || pipe > PIPE_C) 650 return; 651 652 for_each_set_bit(event, irq->flip_done_event[pipe], 653 INTEL_GVT_EVENT_MAX) { 654 clear_bit(event, irq->flip_done_event[pipe]); 655 if (!pipe_is_enabled(vgpu, pipe)) 656 continue; 657 658 intel_vgpu_trigger_virtual_event(vgpu, event); 659 } 660 661 if (pipe_is_enabled(vgpu, pipe)) { 662 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++; 663 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 664 } 665} 666 667void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 668{ 669 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 670 struct intel_display *display = i915->display; 671 int pipe; 672 673 mutex_lock(&vgpu->vgpu_lock); 674 for_each_pipe(display, pipe) 675 emulate_vblank_on_pipe(vgpu, pipe); 676 mutex_unlock(&vgpu->vgpu_lock); 677} 678 679/** 680 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 681 * @vgpu: a vGPU 682 * @connected: link state 683 * 684 * This function is used to trigger hotplug interrupt for vGPU 685 * 686 */ 687void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 688{ 689 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 690 691 /* TODO: add more platforms support */ 692 if (IS_SKYLAKE(i915) || 693 IS_KABYLAKE(i915) || 694 IS_COFFEELAKE(i915) || 695 IS_COMETLAKE(i915)) { 696 if (connected) { 697 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 698 SFUSE_STRAP_DDID_DETECTED; 699 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 700 } else { 701 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 702 ~SFUSE_STRAP_DDID_DETECTED; 703 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 704 } 705 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 706 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 707 PORTD_HOTPLUG_STATUS_MASK; 708 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 709 } else if (IS_BROXTON(i915)) { 710 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 711 if (connected) { 712 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 713 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 714 } else { 715 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 716 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 717 } 718 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 719 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 720 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 721 ~PORTA_HOTPLUG_STATUS_MASK; 722 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 723 PORTA_HOTPLUG_LONG_DETECT; 724 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 725 } 726 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 727 if (connected) { 728 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 729 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 730 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 731 SFUSE_STRAP_DDIB_DETECTED; 732 } else { 733 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 734 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 735 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 736 ~SFUSE_STRAP_DDIB_DETECTED; 737 } 738 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 739 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 740 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 741 ~PORTB_HOTPLUG_STATUS_MASK; 742 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 743 PORTB_HOTPLUG_LONG_DETECT; 744 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 745 } 746 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 747 if (connected) { 748 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 749 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 750 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 751 SFUSE_STRAP_DDIC_DETECTED; 752 } else { 753 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 754 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 755 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 756 ~SFUSE_STRAP_DDIC_DETECTED; 757 } 758 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 759 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 760 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 761 ~PORTC_HOTPLUG_STATUS_MASK; 762 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 763 PORTC_HOTPLUG_LONG_DETECT; 764 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 765 } 766 } 767} 768 769/** 770 * intel_vgpu_clean_display - clean vGPU virtual display emulation 771 * @vgpu: a vGPU 772 * 773 * This function is used to clean vGPU virtual display emulation stuffs 774 * 775 */ 776void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 777{ 778 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 779 780 if (IS_SKYLAKE(dev_priv) || 781 IS_KABYLAKE(dev_priv) || 782 IS_COFFEELAKE(dev_priv) || 783 IS_COMETLAKE(dev_priv)) 784 clean_virtual_dp_monitor(vgpu, PORT_D); 785 else 786 clean_virtual_dp_monitor(vgpu, PORT_B); 787 788 vgpu_update_vblank_emulation(vgpu, false); 789} 790 791/** 792 * intel_vgpu_init_display- initialize vGPU virtual display emulation 793 * @vgpu: a vGPU 794 * @resolution: resolution index for intel_vgpu_edid 795 * 796 * This function is used to initialize vGPU virtual display emulation stuffs 797 * 798 * Returns: 799 * Zero on success, negative error code if failed. 800 * 801 */ 802int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 803{ 804 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 805 806 intel_vgpu_init_i2c_edid(vgpu); 807 808 if (IS_SKYLAKE(dev_priv) || 809 IS_KABYLAKE(dev_priv) || 810 IS_COFFEELAKE(dev_priv) || 811 IS_COMETLAKE(dev_priv)) 812 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 813 resolution); 814 else 815 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 816 resolution); 817} 818 819/** 820 * intel_vgpu_reset_display- reset vGPU virtual display emulation 821 * @vgpu: a vGPU 822 * 823 * This function is used to reset vGPU virtual display emulation stuffs 824 * 825 */ 826void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 827{ 828 emulate_monitor_status_change(vgpu); 829}
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